ST STM6519 User Manual

STM6519

4-pin Smart Reset™

Features

■Operating voltage range 2 V to 5.5 V

■Low supply current 1 μA

■Integrated test mode

■Single Smart Reset™ push-button input with

fixed extended reset setup delay (tSRC) from 0.5 s to 10 s in 0.5 s steps (typ.), option with internal input pull-up resistor

■Push-button controlled reset pulse duration

– Option 1: fully push-button controlled, no fixed or minimum pulse width guaranteed

– Option 2: defined output reset pulse duration (tREC), factory-programmed

■Single reset output

– Active-low or active-high

– Push-pull or open drain with optional pull-up resistor

■Fixed Smart Reset input logic voltage levels

■Operating temperature: -40 °C to +85 °C

■UDFN4 package 1.00 mm x 1.45 mm and UDFN6 package 1.00 mm x 1.45 mm

■ECOPACK®2 (RoHS compliant, HalogenFree)

Datasheet −production data

UDFN4 1.00 mm x 1.45 mm

UDFN6 1.00 mm x 1.45 mm

Applications

■Mobile phones, smartphones, PDAs

■e-books

■MP3 players

■Games

■Portable navigation devices

■Any application that requires delayed reset push-button response for improved system stability

June 2012

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This is information on a product in full production.

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Contents	STM6519

Contents

1	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						. 5
	1.1	Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					5
	1.2	Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					6
	1.3	Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					6
2	Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						7
3	Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						8
	3.1	Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8
	3.2	Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					8
	3.3	Smart Reset input					8
					(SR)
	3.4	Reset output					8
			(RST)
4	Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						9
5	Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						10
6	Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						11
7	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						13
8	DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						14
9	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						16
10	Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						20
11	Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						21
12	Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						22
13	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						23

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STM6519	List of tables

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package mechanical data . . . . . 17 Table 6. UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package mechanical data . . . . . 18 Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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List of figures	STM6519

List of figures

Figure 1.	STM6519 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 2.	UDFN4 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 3.	UDFN6 pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 4.	STM6519 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 8
Figure 5.	Typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 9
Figure 6.	RST output without tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 7.	RST output with tREC option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10
Figure 8.	Supply current (ICC) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
Figure 9.	Smart Reset delay (tSRC) vs. temperature (TA), tSRC = 4.0 s (typ.) . . . . . . . . . . . . . . . . . .	11
Figure 10.	Test mode entry voltage (VTEST) vs. temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 11.	Initial test mode time (tSRC-INI) vs. temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
Figure 12.	UDFN4, 1.00 mm x 1.45 mm x 0.50 mm, 0.65 mm pitch package outline . . . . . . . . . . . . .	16
Figure 13.	Footprint recommendation for UDFN4, 1.00 mm x 1.45mm x 0.50 mm,
	0.65 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
Figure 14.	UDFN6, 1.00 mm x 1.45 mm x 0.50 mm, 0.50 mm pitch package outline . . . . . . . . . . . . .	18
Figure 15.	Footprint recommendation for UDFN6 1.00 mm x 1.45 mm x 0.50 mm,
	0.50 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 16.	Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 17.	Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 18.	Package marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22

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STM6519	Description

1 Description

The Smart ResetTM devices provide a useful feature which ensures that inadvertent short reset push-button closures do not cause system resets. This is done by implementing an extended Smart Reset input delay time (tSRC), which ensures a safe reset and eliminates the need for a specific dedicated reset button.

This reset configuration provides versatility and allows the application to distinguish between a software generated interrupt and a hard system reset. When the input push-button is connected to the microcontroller interrupt input, and is closed for a short time, the processor can only be interrupted. If the system still does not respond properly, continuing to keep the push-buttons closed for the extended setup time tSRC causes a hard reset of the processor through the reset output.

The STM6519 has one Smart Reset input (SR) with preset delayed Smart Reset setup time (tSRC). The reset output (RST) is asserted after the Smart Reset input is held active for the

selected tSRC delay time. The RST output remains asserted either until the SR input goes to inactive logic level (i.e. neither fixed nor minimum reset pulse width is set) or the output reset pulse duration is fixed for tREC (i.e. factory-programmed). The device fully operates over

a broad VCC range from 2.0 V to 5.5 V.

1.1Test mode

After pulling SR up to VTEST (VCC + 1.4 V) or above, the counter starts to count the initial shortened tSRC-INI (42 ms, typ.). After tSRC-INI expires, the RST output either goes down for tREC (if tREC option is used) or stays low as long as overvoltage on SR is detected (if tREC option is not used). This is feedback, and the user only knows that the device is locked in

test mode. Each time the SR input is connected to ground in test mode, a shortened

tSRC-SHORT (tSRC/128) is used instead of regular tSRC (0.5 s - 10 s). In this way the device can be quickly tested without repeating test mode triggering. Return to normal mode is

possible by performing a new startup of the device (i.e. VCC goes to 0 V and back to its original state).

The advantages of this solution are its high glitch immunity, user feedback regarding entry into test mode, and testability within the full VCC range.

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Description	STM6519

1.2Logic diagram

Figure 1. STM6519 logic diagram

6##

			34-
32						234

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!-

1.3Pin connections

Figure 2. UDFN4 pin connections (top view)

633
						234
				34-
					6##
	32

5$&.

!-

Figure 3. UDFN6 pin connections (top view)

			.#
234

	633		34-		.#
	32				6##

5$&.

!-6

1. Not connected (not bonded); should be connected to VSS.

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STM6519	Device overview

2 Device overview

	Table 1.	Signal names
	Pin number
			Name					Type	Description
	UDFN6	UDFN4
	1	4						Output	Reset output, active-low, open drain.
				RST
	2	1		VSS				Supply ground	Ground
	3	2						Input	Smart Reset input, active-low.
					SR
									Positive supply voltage for the device. A 0.1 µF
	4	3		VCC				Supply voltage	decoupling ceramic capacitor is recommended
									to be connected between VCC and VSS pins.
	5	-		NC				-	Not connected (not bonded); should be
									connected to VSS.
	6	-		NC				-	Not connected (not bonded); should be
									connected to VSS.

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Pin descriptions	STM6519

3 Pin descriptions

3.1Power supply (VCC)

This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the STM6519 device as possible.

3.2Ground (VSS)

This is the ground pin for the device.

3.3Smart Reset input (SR)

Push-button Smart Reset input, active-low with optional pull-up resistor. SR input needs to be asserted for at least tSRC to assert the reset output (RST).

By connecting a voltage higher than VCC + 1.4 V to the SR input the device enters test mode (see Section 1: Description on page 5 for more information).

3.4Reset output (RST)

RST is active-low or active-high, open drain or push-pull reset output with optional internal pull-up resistor.

Output reset pulse width is optional as follows:

●Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert)

●Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset input state.

Figure 4. STM6519 block diagram

		T32#	T2%#
	32		GENERATOR	234
		GENERATOR
			OPTIONAL
		/VERVOLTAGEGDETECT
		TEST MODE TRIGGER
				!-6

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