The Smart Reset™ device family STM65xx provides a useful feature that ensures
inadvertent short reset push-button closures do not cause system resets. This is done by
implementing an extended Smart Reset™ input delay (t
input levels and setup delay are met, the device generates an output reset pulse with userprogrammable timeout period (t
REC
).
The typical application hookup shows that the dual Smart Reset™ inputs can be also
connected to the applications interrupt to allow the control of both the interrupt pin and the
hard reset functions. If the push-buttons are closed for a short time, the processor is only
interrupted. If the system still does not respond properly, holding the push-buttons for the
extended setup time (t
) causes a hard reset of the processor through the reset output.
SRC
The Smart Reset™ feature helps significantly increase system stability.
The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset
circuits targeted at applications such as MP3 players, portable navigation devices or mobile
phones, generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset™
inputs (SRx). The delayed Smart Reset™ setup time (t
adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed
setup period ignores switch closures shorter than t
SRC
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST
output(s) with or without an internal pull-up resistor or push-pull as output options, with or
without the power-on reset function.
). Once the valid Smart Reset™
SRC
) options are adjustable by
SRC
, thus preventing undesired resets.
)
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V
reset output remains asserted for the reset timeout period (t
voltage goes above the specified threshold.
1.2 STM6510
The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™
setup delay (t
STM6510 feature is adjustable output reset pulse time t
(C
).
tREC
Additionally, the V
reset output goes active and remains active while V
defined duration of the reset pulse t
drops below the specified threshold. The
CC
) programmed by an external capacitor on the SRC pin. An additional
SRC
REC
is monitored and if it drops below the selected V
CC
REC
.
is below the V
CC
) after the monitored supply
REC
by adding an external capacitor
threshold, the
RST
threshold, plus the
RST
Doc ID 16788 Rev 25/26
DescriptionSTM6510
Figure 1.Logic diagram
V
CC
SR0
SR1
SRC
STM6510
V
SS
RST
TREC
ADJ
AM00389a
Figure 2.Pin connections
STM
6510
8
V
CC
7
SR0
6
TREC
ADJ
5
SRC
Table 1.Signal names
RST
V
SS
SR1
NC
1
2
3
4
SymbolInput/outputDescription
RST
SR0Input
SR1Input
SRCInput
TREC
ADJ
OutputReset output, active-low (open-drain).
Primary push-button Smart Reset™ input. Active-low, internal 65 kΩ
pull-up resistor to V
CC
.
Secondary push-button Smart Reset™ input. Active-low, internal 65 kΩ
pull-up resistor to V
CC
.
Smart Reset™ input delay setup control. Connect an external capacitor
to this pin to adjust the delay setup time (t
Input
Input pin for t
capacitor (C
reset pulse duration adjustment. Connect an external
REC
) to this pin to determine t
tREC
Supply voltage input. Power supply for the device and an input for the
V
CC
Supply
monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between V
V
SS
Supply Ground
NCNo connect (not bonded); should be connected to V