STM6502, STM6503
STM6504, STM6505
Dual push-button Smart ResetTM with user-adjustable setup delays
Features
■ Dual Smart Reset push-button inputs with
extended reset setup delay
■ Adjustable Smart Reset setup delay (t
by external capacitor or three-state logic
(product options): t
■ Power-on reset
■ Single RST output, active-low, open-drain
■ Factory-programmable thresholds to monitor
V
in the range of 1.575 to 4.625 V typ.
CC
■ Operating voltage 1.0 V (active-low output
= 2, 6, 10 s (min.)
SRC
valid) to 5.5 V
■ Low supply current
■ Operating temperature:
industrial grade –40 °C to +85 °C
■ TDFN8 package: 2 mm x 2 mm x 0.75 mm
■ RoHS compliant
SRC
):
TDFN8 (DG)
2 mm x 2 mm
Applications
■ Mobile phones, smartphones
■ e-books
■ MP3 players
■ Games
■ Portable navigation devices
■ Any application that requires delayed reset
push-button(s) response for improved system
stability
Table 1. Device summary
t
Voltage inputs Smart Reset inputs
Part
number
V
STM6502
STM6503 ✓✓✓ ✓✓TDFN-8L
STM6504
STM6505 ✓✓ ✓ ✓ ✓ ✓ ✓TDFN-8L
1. Contact local ST sales office for availability.
February 2011 Doc ID 16101 Rev 6 1/29
(1)
(1)
V
CC
✓✓✓ ✓ ✓TDFN-8L
✓✓ ✓ ✓✓TDFN-8L
BAT
SR0 SR1
SRE
immediate,
independent
SRC pin
SRC
programming
Three-
Ext.
state
input
TSR
Reset or Power
Good outputs
RST
BLD
Package
www.st.com
1
Contents STM6502, STM6503, STM6504, STM6505
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Smart Reset devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.1 Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.2 Ground (V
1.2.3 Primary Smart Reset input (SR0
1.2.4 Secondary Smart Reset input (SR1
1.2.5 Edge-triggered Smart Reset input (SRE pin) – STM6504 only . . . . . . . 11
1.2.6 Adjustable delay of Smart Reset input (SRC pin) – STM6502
and STM6505 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.7 Programmable Smart Reset input delay (TSR pin) – STM6503
and STM6504 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.8 Reset output (RST
1.2.9 Battery monitoring input (V
1.2.10 Battery low detect output (BLD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
) – STM6505 only . . . . . . . . . . . . . . . . . 12
BAT
) – STM6505 only . . . . . . . . . . . . . . . . . 12
2 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 List of tables
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. t
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating and measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. V
Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . 21
Table 9. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Table 10. Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
programmed by an ideal external capacitor – STM6502 and STM6505 . . . . . . . . . . 11
SRC
voltage thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CC
Doc ID 16101 Rev 6 3/29
STM6502, STM6503, STM6504, STM6505 List of figures
List of figures
Figure 1. Logic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram - STM6502, STM6503, STM6504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Block diagram - STM6505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Single-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Dual-button Smart Reset typical hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. STM6502, STM6503 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. STM6504 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. STM6505 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Supply current (I
Figure 11. Smart Reset delay (t
Figure 12. Reset threshold (V
Figure 13. V
monitoring threshold (V
BAT
Figure 14. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline. . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Figure 17. Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 18. Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Package marking, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
) vs. temperature (STM6505) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
) vs. temperature, C
SRC
) vs. temperature, “S” threshold option, VCC falling (STM6505) . . . 14
RST
BATTH)
vs. temperature, falling (STM6505) . . . . . . . . . . . . . . 14
= 0.62 µF (STM6505) . . . . . . . . . . . . . . 13
SRC
Doc ID 16101 Rev 6 4/29
STM6502, STM6503, STM6504, STM6505 Description
1 Description
STM6502 has two combined Smart Reset inputs (SR0 and SR1) with delayed Smart Reset
setup time (t
STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0
and three user-selectable delayed Smart Reset setup time (t
s through a three-state TSR input pin: when connected to ground, t
open, t
SRC
STM6504 has two independent Smart Reset inputs. SR0
setup time (t
input pin: when connected to ground, t
connected to V
is edge-triggered with a special debounce time (t
edge after a valid reset period.
) programmed by an external capacitor on the SRC pin.
SRC
= 6 s; when connected to VCC, t
= 10 s (all the times are minimum).
SRC
provides the delayed Smart Reset
) function with three user-selectable t
SRC
CC
, t
= 10 s (all the times are minimum). SRE provides instant reset. SRE
SRC
= 2 s; when left open, t
SRC
DEBOUNCE
options through a three-state TSR
SRC
, SR1)
) options of 2 s, 6 s and 10
SRC
= 2 s; when left
SRC
= 6 s; when
SRC
= 240 ms min.) at the falling
STM6505 has two combined delayed Smart Reset inputs (SR0
adjustable reset delay setup time via an external capacitor connected to the SRC pin.
The RST
output depends also on the VCC monitoring threshold. STM6505 also provides
independent low battery detect (BLD
voltage V
detect output pin (BLD
BAT
. V
is monitored for low voltage and provides an indication on the battery low
BAT
). V
BAT
be used to set the actual battery voltage threshold. V
(16 mV max.). V
V
pin; VCC must be ≥ 1.575 V for proper operation of the V
CC
is voltage monitoring input only, the device is powered only from the
BAT
1.1 Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (t
delay are met, the device generates an output reset pulse with user-programmable timeout
period (t
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (t
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
REC
).
, SR1) and provides an
) output controlled by the secondary external input
threshold is 1.25 V, fixed, and an external resistor divider is to
threshold hysteresis is 8 mV typ.
BAT
comparator.
BAT
). Once the valid Smart Reset input levels and setup
SRC
) causes hard reset of
SRC
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (t
) options of 2 s, 6 s and 10 s (all min.) are
SRC
adjustable by an external capacitor on the SRC pin or selectable by three-state logic. The
delayed setup period ignores switch closures shorter than t
, thus preventing unwanted
SRC
resets.
Doc ID 16101 Rev 6 5/29
Description STM6502, STM6503, STM6504, STM6505
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage V
reset output remains asserted for the reset timeout period (t
drops below the specified threshold. The
CC
) after the monitored supply
REC
voltage goes above the specified threshold.
Figure 1. Logic diagrams
V
CC
SR0
SR1
SRC
SR0
SRE
TSR
STM6502
V
SS
V
CC
STM6504
V
SS
Figure 2. Pin connections
RST
RST
SR0
SR1
TSR
SR0
SR1
SRC
V
BAT
V
CC
STM6503
V
SS
V
CC
STM6505
V
SS
RST
RST
BLD
AM00378
8
1
RST
V
2
SS
SR1
NC NC
RST
V
SS
SRE
NC
STM
6502
3
4
1
2
STM
6504
3
4
V
CC
7
SR0
6
SRC
5
8
V
CC
7
SR0
6
TSR
5
NC
6/29 Doc ID 16101 Rev 6
1
RST
V
2
SS
SR1
NC NC
RST
V
SS
SR1
BLD
STM
6503
3
4
1
2
STM
6505
3
4
8
7
6
5
8
7
6
5
V
SR0
TSR
V
CC
SR0
SRC
V
BAT
CC
AM00379
STM6502, STM6503, STM6504, STM6505 Description
Table 2. Signal names
Symbol
RST
BLD
SR0
Input/
output
Description
Output Open-drain reset output, active-low.
Output Battery low detect output, active-low, open-drain. STM6505 only.
Input
Primary push-button Smart Reset input. Active-low, with or without internal
65 kΩ pull-up to V
(product options).
CC
Secondary push-button Smart Reset input - combines with the primary push-
SR1
Input
button reset to provide setup delay time before reset. Active-low, with or without
internal 65 kΩ pull-up to V
(product options).
CC
Secondary push-button Smart Reset input - provides instant Smart Reset. SRE
SRE Input
is edge-triggered with a special debounce time (t
the falling edge after a valid reset period. Active-high, no internal pull-up to V
STM6504 only.
SRC Input
Smart Reset input delay setup control: connect to an external capacitor to adjust
the delay setup time (t
). STM6502 and STM6505 only.
SRC
A three-state Smart Reset input delay setup control. When connected to
TSR Input
ground, t
t
= 10 s (all times are minimum). TSR is a DC-type input, intended to be
SRC
either permanently grounded, permanently connected to V
= 2 s; when left open, t
SRC
= 6 s; when connected to VCC,
SRC
left open. If left open, for improved system glitch immunity it is strongly
recommended to connect a 0.1 µF decoupling ceramic capacitor between the
TSR and V
pins. STM6503 and STM6504 only.
SS
Supply voltage input. Power supply for the device and an input for the monitored
V
V
BAT
V
Supply
CC
Supply Ground
SS
Input Battery voltage monitoring input. STM6505 only.
supply voltage. A 0.1 µF decoupling ceramic capacitor is recommended to be
connected between the V
and VSS pins.
CC
NC No connect (not bonded); should be connected to V
DEBOUNCE
.
SS
= 240 ms min.) at
or permanently
CC
CC
.
Doc ID 16101 Rev 6 7/29
Description STM6502, STM6503, STM6504, STM6505
Figure 3. Block diagram - STM6502, STM6503, STM6504
V
CC
SR1
(SRE
STM6504
(1)
only)
V
RST
Logic
COMPARE
t
REC
generator
RST
SR0
SRC (STM6502)
TSR (STM6503,
STM6504)
1. STM6504 only: SR0 and SRE are working independently. SRE is edge-triggered and has a special
debounce time (t
DEBOUNCE
= 240 ms min.) at the falling edge after a valid reset period.
Logic
Figure 4. Block diagram - STM6505
6
"!4
6
##
32
32
32#
6
##
6
"!44(
6
234
#/-
#/-
,OGIC
0!2%
0!2%
",$
T
GENE
2%#
RATOR
234
AM00352a
!-B
8/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Description
Figure 5. Single-button Smart Reset typical hookup
6
##
6
##
234
432
34-
32
6
32
33
Figure 6. Dual-button Smart Reset typical hookup
6
##
2%3%4
).4
.-)
053(
37)4#(
6
##
-#5
6
33
"544/.
!-B
6
##
34-
6
33
234
432
32
32
053("544/.
37)4#(
053(
37)4#(
2%3%4
).4
.-)
"544/.
6
##
-#5
6
33
!-6
Doc ID 16101 Rev 6 9/29
Description STM6502, STM6503, STM6504, STM6505
1.2 Pin descriptions
1.2.1 Power supply (VCC)
This pin is used to provide the power to the device and to monitor the power supply.
A 0.1 µF decoupling ceramic capacitor is recommended to be connected between the V
and V
SS
pins.
1.2.2 Ground (VSS)
This is the supply ground for the device.
1.2.3 Primary Smart Reset input (SR0)
The primary push-button Smart Reset input, active-low pin is connected to the first pushbutton switch.
1.2.4 Secondary Smart Reset input (SR1)
The secondary push-button Smart Reset input, active-low pin is connected to the second
push-button switch. Keeping both Smart Reset inputs SR0
t
activates the reset output pulse.
SRC
and SR1 active for longer than
CC
Figure 7. STM6502, STM6503 timing
t
REC
SR0
SR1
RST
t
SRC
Reset is asserted “low” right after the Smart Reset setup delay (t
returns to high after the t
REC
period.
) has been met and
SRC
AM00327
10/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Description
1.2.5 Edge-triggered Smart Reset input (SRE pin) – STM6504 only
The SRE pin is active-high, immediate and independent reset input that includes an edge
trigger with debounce delay t
DEBOUNCE
Note: The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster
than 1 V/µs typ.
Figure 8. STM6504 timing
on the falling edge.
SR0
Independent
SRE
No debounce
RST
t < t
=> t
REC
DEBOUNCE
timer reset
t < t
=> no output response
t
REC
(rising edges within
t
DEBOUNCE
SRC
t
DEBOUNCE
are ignored)
t
REC
t
SRC
t
REC
1.2.6 Adjustable delay of Smart Reset input (SRC pin) – STM6502 and
STM6505 only
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (C
desired value of the setup time (t
Calculated t
Table 3. t
Calculated C
value [µF]
and C
SRC
programmed by an ideal external capacitor – STM6502 and STM6505
SRC
SRC
examples are given in Ta bl e 3 . Refer also to Ta b le 6 .
SRC
Min. Typ. Max.
).
SRC
Setup delay t
), which is tied to ground to provide the
SRC
(1)(2)
[s]
SRC
Closest common
C
SRC
value [µF]
AM00328V2
0.2 2 2.5 3.0 0.22
0.3 3 3.75 4.5 0.33
0.6 6 7.5 9 0.56
1 10 12.5 15 1
1. At 25 °C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external t
(C
) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
SRC
used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment
should be ensured to prevent t
is 0.01 µF.
2. In case of repeated activations of the t
activations to fully discharge C
accuracy from being affected. A recommended minimum value of C
SRC
timer, an interval of 10 ms min. is needed between the
SRC
, so that the next t
SRC
is as specified.
SRC
programming capacitor
SRC
Doc ID 16101 Rev 6 11/29
SRC
Description STM6502, STM6503, STM6504, STM6505
1.2.7 Programmable Smart Reset input delay (TSR pin) – STM6503 and
STM6504 only
The TSR pin allows the user to program the setup time before the push-button action is
validated by the reset output. It is controlled by different voltage levels on the three-state
TSR input pin: when connected to ground, t
connected to V
CC
, t
= 10 s (all times are minimum). TSR is a DC-type input, intended to
SRC
be either permanently grounded, permanently connected to V
= 2 s; when left open, t
SRC
= 6 s; when
SRC
or permanently left open.
CC
If it is left open, for improved system glitch immunity it is strongly recommended to connect
a 0.1 µF decoupling ceramic capacitor between the TSR and V
SS
pins.
1.2.8 Reset output (RST)
RST is the active-low, open-drain reset output in the Smart Reset family.
1.2.9 Battery monitoring input (V
V
is an input for monitoring the battery voltage. V
BAT
) – STM6505 only
BAT
threshold is 1.25 V, fixed, and an
BAT
external resistor divider is to be used to set the actual battery voltage threshold.
1.2.10 Battery low detect output (BLD) – STM6505 only
The battery low detect output is controlled by the V
active-low, open-drain, with no pull-up.
Figure 9. STM6505 timing
t
SRC
SR0
SR1
RST
V
BAT
V
BATTH
BLD
voltage monitoring input and is
BAT
t
REC
12/29 Doc ID 16101 Rev 6
AM00329
STM6502, STM6503, STM6504, STM6505 Typical operating characteristics
2 Typical operating characteristics
Figure 10. Supply current (ICC) vs. temperature (STM6505)
3
2.5
2
[μA]
CC
I
1.5
1
0.5
-60 -40 -20 0 20 40 60 80 100 120 140
Figure 11. Smart Reset delay (t
9.2
8.7
8.2
[s]
SRC
t
7.7
7.2
6.7
0
Temperature [°C]
5.5 V 2 V 5 V 3 V
) vs. temperature, C
SRC
= 0.62 µF (STM6505)
SRC
AM04886v1
-60 -40 -20 0 20 40 60 80 100 120 140
6.2
Temperature [°C]
5.75 V 5.5 V 3.3 V
AM04887v1
Doc ID 16101 Rev 6 13/29
Typical operating characteristics STM6502, STM6503, STM6504, STM6505
Figure 12. Reset threshold (V
[V]
RST
V
-60 -40 -20 0 20 40 60 80 100 120 140
) vs. temperature, “S” threshold option, VCC falling (STM6505)
RST
2.99
2.97
2.95
2.93
2.91
2.89
2.87
2.85
Temperature [°C]
AM04888v1
Figure 13. V
[V]
BATTH
V
-60 -40 -20 0 20 40 60 80 100 120 140
monitoring threshold (V
BAT
1.275
1.27
1.265
1.26
1.255
1.25
1.245
1.24
1.235
1.23
1.225
BATTH)
vs. temperature, falling (STM6505)
Temperature [°C]
5.75 V 5.5 V 3.3 V 2 V 1.58 V
AM04889v1
14/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Maximum ratings
3 Maximum ratings
Stressing the device above the rating listed in Table 4: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
T
SLD
θ
JA
V
V
CC
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
2. For inputs or outputs with internal pull-up resistors and push-pull type outputs –0.3 to VCC+0.3 V only.
Storage temperature (VCC off) –55 to +150 °C
(1)
Lead solder temperature for 10 seconds 260 °C
Thermal resistance (junction to ambient) TDFN8 149.0 °C/W
Input or output voltage –0.3 to 5.5
IO
Supply voltage –0.3 to 7 V
(2)
V
Doc ID 16101 Rev 6 15/29
DC and AC parameters STM6502, STM6503, STM6504, STM6505
4 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5: Operating and measurement conditions. Designers should check that the operating
conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 5. Operating and measurement conditions
Paramete r Value Unit
supply voltage 1.0 to 5.5 V
V
CC
Ambient operating temperature (T
Input rise and fall times ≤
) –40 to +85 °C
A
5ns
Input pulse voltages 0.2 to 0.8 V
Input and output timing ref. voltages 0.3 to 0.7 V
Figure 14. AC testing input/output waveforms
0.8 V
0.2 V
CC
CC
0.7 V
0.3 V
CC
CC
CC
CC
V
V
AM00478
16/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 DC and AC parameters
Table 6. DC and AC characteristics
Symbol Parameter Test conditions
CC
Supply voltage range Reset output valid - active-low 1.0 5.5 V
= 5.0 V 1.2 µA
V
CC
V
= 3.0 V
CC
V
= 5.0 V, TSR left open 4 5.8 µA
CC
V
= 3.0 V, TSR left open
CC
V
= 5.0 V, TSR left open 4 5.8 µA
CC
V
= 3.0 V, TSR left open
CC
V
= 5.0 V 2.3 3.3 µA
CC
V
= 3.0 V
CC
Supply current (inputs
in their inactive state,
t
REC
and t
SRC
counter
is inactive)
STM6502
STM6503
STM6504
STM6505
V
I
CC
Output characteristics
V
≥ 4.5 V, sinking 3.2 mA 0.3 V
CC
V
t
REC
OL
Reset output voltage low
(reset asserted: RST
, BLD)
Reset timeout delay,
factory-programmed
V
≥ 3.3 V, sinking 2.5 mA 0.3 V
CC
V
≥ 1.0 V, sinking 0.1 mA 0.3 V
CC
Option A 140 210 280 ms
Option B 240 360 480 ms
(3)
(3)
(1)
(3)
(3)
Min. Typ.
1.1 µA
2.2 µA
(2)
Max. Unit
3µA
3µA
V
monitoring reset thresholds
CC
Fixed voltage trip point for
V
V
RST
monitoring (refer to
CC
Table 7)
V
HYST
V
BAT
V
BATTH
V
BATHYSTVBATTH
I
LI(VBAT)
Hysteresis of V
V
CC
monitoring
Fixed V
threshold
V
BAT
to reset delay
monitoring
BAT
hysteresis STM6505 only 8 16 mV
input leakage current STM6505 only –100 10 100 nA
RST
–40 to +85 °C
25 °C
RST
–2.5%
V
RST
–2.0%
V
V
RST
RST
V
RST
+2.5%
V
RST
+2.0%
V
L, M 0.5%
T, S, R, Z, Y, W, V 1%
falling from
V
CC
(V
+ 100 mV) to (V
RST
10 mV/µs
(4)
- 100 mV) at
RST
20 µs
STM6505 only 1.225 1.25 1.275 V
V
V
Doc ID 16101 Rev 6 17/29
DC and AC parameters STM6502, STM6503, STM6504, STM6505
Table 6. DC and AC characteristics (continued)
Symbol Parameter Test conditions
Smart Reset inputs
(1)
Min. Typ.
(2)
Max. Unit
V
IL
V
IH
I
LI(SR)
I
LI(TSR)
SR0, SR1, SRE input
voltage low
SR0, SR1, SRE input
voltage high
Input leakage current, SR
and SRE inputs
Input leakage current, TSR
input
Option without internal pull-up resistor –1 +1 µA
STM6503 and STM6504 only –5 +7 µA
VSS
–0.3
0.7
V
CC
0.3
V
CC
5.5 V
Internal pull-up resistor,
PUI
input (optional - refer to
R
65 kΩ
Table 12)
t
DEBOUNCE
SRE input falling edge
debounce time
STM6504 only 240 360 480 ms
Smart Reset delay
Capacitor-programmable
t
SRC
(5)
STM6502 and STM6505.
T
= 25 °C
A
C
Smart Reset setup time,
Refer to Ta bl e 3 .
TSR pin-programmable
(5)
t
SRC
Smart Reset setup time,
STM6503 and STM6504.
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 to 5.5 V (except wher e noted).
2. Typical value is at 25 °C and V
3. For devices with V
4. Guaranteed by design.
5. Input glitch immunity is equal to t
only.
6. If left open, for improved system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and V
RST
< 3.0 V.
= 3.3 V unless otherwise noted.
CC
SRC
SS
TSR = V
TSR = floating
TSR = V
(when both SR inputs are low, otherwise infinite). STM6502, STM6503, STM6505
pins.
SS
(6)
CC
10 x
SRC
(µF)
12.5 x
C
(µF)
SRC
15 x
C
SRC
(µF)
22.53s
67.59s
10 12.5 15 s
V
s
18/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 DC and AC parameters
.
Table 7. VCC voltage thresholds
VCC monitoring threshold
V
RST
Typ.
±2.5% (–40 °C to +85 °C) ±2.0% (25 °C)
Unit
Min. Max. Min. Max.
L (falling) 4.625 4.509 4.741 4.533 4.718 V
M (falling) 4.375 4.266 4.484 4.288 4.463 V
T (falling) 3.075 2.998 3.152 3.014 3.137 V
S (falling) 2.925 2.852 2.998 2.867 2.984 V
R (falling) 2.625 2.559 2.691 2.573 2.678 V
Z (falling) 2.313 2.255 2.371 2.267 2.359 V
Y (falling) 2.188 2.133 2.243 2.144 2.232 V
W (falling) 1.665 1.623 1.707 1.632 1.698 V
V (falling) 1.575 1.536 1.614 1.544 1.607 V
Doc ID 16101 Rev 6 19/29
Package mechanical data STM6502, STM6503, STM6504, STM6505
5 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
20/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Package mechanical data
Figure 15. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package outline
PIN 1 INDEX AREA
0.10 C
0.10
C
A
0.08 C
PIN 1 INDEX AREA
Pin#1 I D
D
2x
0.10 C
2x
TOP VIEW
SIDE VIEW
e
1
A
B
E
C
A1
SEAT ING
PLANE
b
4
0.10 C A B
L
8
BOTTOM VIEW
5
8070540_A
Table 8. TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm pitch package mechanical data
Dimension (mm) Dimension (inches)
Symbol
Min. Nom. Max. Min. Nom. Max.
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.15 0.20 0.25 0.006 0.008 0.010
D
BSC
E
BSC
e 0.50 0.020
L 0.45 0.55 0.65 0.018 0.022 0.026
1.9 2.00 2.1 0.075 0.079 0.083
1.9 2.00 2.1 0.075 0.079 0.083
Doc ID 16101 Rev 6 21/29
Package mechanical data STM6502, STM6503, STM6504, STM6505
Figure 16. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E1E
L
b
Table 9. Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Parameter Description
Min. Nom. Max.
L Contact length 1.05
b Contact width 0.25
E Max. land pattern Y-direction
E1 Contact gap spacing
D Max. land pattern X-direction
P Contact pitch
—
—
—
—
—
—
2.85
0.65
1.75
0.5
AM00441
1.15
0.30
—
—
—
—
22/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Package mechanical data
Figure 17. Carrier tape
P
0
D
T
Top cover
tape
K
0
Center lines
of cavity
Table 10. Carrier tape dimensions
Package W D E P
1.50
+0.10/
–0.00
1.75
±0.10
TDFN8
8.00
+0.30
–0.10
0
4.00
±0.10
P
2
User direction of feed
P
2.00
±0.10
FA0B
2
3.50
±0.05
±0.05
2.30
E
A
0
B
0
P
1
K
0
2.30
±0.05
1.00
±0.05
F
W
AM03073v2
P
0
4.00
±0.10
1
TUnit
0.250
±0.05
Bulk
qty.
mm 3000
Doc ID 16101 Rev 6 23/29
Package mechanical data STM6502, STM6503, STM6504, STM6505
Figure 18. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
A
Full radius
C
N
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
Table 11. Reel dimensions
Tape sizes A max. B min. C D min. N min. G T max.
8 mm 180 (7 inches) 1.50 13.0 +/– 0.20 20.20 60 8.4 +2/–0 14.40
AM00443
24/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Package mechanical data
Figure 19. Tape trailer/leader
End
To p
cover
tape
No components No componentsComponents
TRAILER
160 mm min.
Figure 20. Pin 1 orientation
Sealed with cover tape
User direction of feed
10 0 mm min.
LEADE
400 mm min.
Start
R
AM00444
Note: 1 Drawings are not to scale.
2 All dimensions are in mm, unless otherwise noted.
User direction of feed
AM00442
Doc ID 16101 Rev 6 25/29
Part numbering STM6502, STM6503, STM6504, STM6505
6 Part numbering
Table 12. Ordering information scheme
Example: STM6505 W C A B DG 6 F
Device type
STM6502
(1)
STM6503
STM6504
(1)
STM6505
Reset (V
(V
RST
monitoring) threshold voltage
CC
), typ., falling
L = 4.625 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
W = 1.665 V
V = 1.575 V
Smart Reset setup delay (t
pull-up on all Smart Reset inputs (SRx
); presence of internal input
SRC
, SRE)
A = user-programmable (external capacitor); no input pull-up
C = user-programmable (external capacitor); 65 kΩ input pull-up
E = 2 or 6 or 10 s min., user-programmable (three-state); no input pull-up
F = 2 or 6 or 10 s min., user-programmable (three-state); 65 kΩ input pull-up
Output type
A = open-drain, no pull-up, active-low
Reset timeout period (t
REC
)
A = 140 ms min.
B = 240 ms min.
Package
DG = TDFN8 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
F = ECOPACK
®
package, tape and reel
1. Contact local ST sales office for availability.
For device options currently available refer to Tabl e 13 . For other options, voltage threshold values etc. or
for more information on any aspect of this device, please contact the ST sales office nearest you.
26/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505 Package marking
7 Package marking
Table 13. Package marking
Smart
t
Part number
SRC
delay
control
Reset
inputs
(1)
V
RST
STM6503REAADG6F TSR AL R AL, OD A — 3RG
STM6503SEAADG6F TSR AL S AL, OD A — 3SG
STM6503VEAADG6F TSR AL V AL, OD A — 3VG
STM6504SEABDG6F
(2)
TSR AL S AL, OD B — 4SG
RST
output
(1)
t
REC
option
BLD
output
(1)
Topmark
STM6505SCABDG6F C
STM6505RCABDG6F C
STM6505WCABDG6F C
1. AL = active-low, AH = active-high, PU = with internal pull-up resistor, OD = open-drain.
2. Contact local ST sales office for availability.
SRC
SRC
SRC
AL, PU S AL, OD B AL, OD 5SK
AL, PU R AL, OD B AL, OD 5RK
AL, PU W AL, OD B AL, OD 5WK
Figure 21. Package marking, top view
A
BC
E
D
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
Doc ID 16101 Rev 6 27/29
AM00479
Revision history STM6502, STM6503, STM6504, STM6505
8 Revision history
Table 14. Document revision history
Date Revision Changes
31-Aug-2009 1 Initial release.
Updated Applications, Section 1, Section , Figure 3 to Figure 6
updated and moved to Section , updated Ta b l e 1 , Ta b le 2 , Ta bl e 3 ,
06-Nov-2009 2
15-Jan-2010 3
01-Mar-2010 4
Ta b le 4 , Ta bl e 6 , Ta b l e 1 2 , Section 1.2.3, Section 1.2.7,
Section 1.2.9, Section 5, added package footprint, tape and reel
information, and Section 7.
Updated Features, Section 1, Section 1.2.6, Tab le 1 , Ta b le 2 ,
Figure 5, Figure 6, Ta bl e 3 , Table 6 , Ta b le 1 2 , Table 13, removed
Table 4.
Updated title of datasheet, Features, Applications, Tab le 1, 2, 6, 12,
footnote 5 of Ta b l e 6 ; updated Figure 3, 4; added Section 2: Typical
operating characteristics; minor textual and formatting changes.
21-Jun-2010 5
09-Feb-2011 6
Updated Features, Section 1, Figure 8, footnote 1 and 2
updated Tab le 4 , added footnote 2 to Ta b le 4 , Tabl e 6, added
footnote 6 to Tabl e 6, updated Ta bl e 6 to Ta b l e 9 , and added footnote
2 of Tab le 1 3 .
Reformatted Tab le 1 , updated Ta b l e 6 , added STM6503REAADG6F
and STM6503SEAADG6F device to Table 13, corrected typo in
Ta b le 1 3 .
of Ta b le 3 ,
28/29 Doc ID 16101 Rev 6
STM6502, STM6503, STM6504, STM6505
y
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Doc ID 16101 Rev 6 29/29
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