ST STM32F101C8, STM32F101R8, STM32F101V8, STM32F101T8, STM32F101RB User Manual

...

Download

Medium-density access line, ARM-based 32-bit MCU with 64 or

LQFP48

7 x 7 mm

LQFP100

14 x 14 mm

LQFP64

10 x 10 mm

VFQFPN36

6 × 6 mm

VFQFPN48

7 × 7 mm

128 KB Flash, 6 timers, ADC and 7 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access

– Single-cycle multiplication and hardware

division

■ Memories

– 64 to 128 Kbytes of Flash memory – 10 to 16 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os – POR, PDR and programmable voltage

detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes –V

■ Debug mode

– Serial wire debug (SWD) and JTAG

■ DMA

– 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs,

■ 1 × 12-bit, 1 µs A/D converter (up to 16

channels) – Conversion range: 0 to 3.6 V – Temperature sensor

■ Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

supply for RTC and backup registers

BAT

interfaces

Cs and USARTs

external interrupt vectors and almost all

5 V-tolerant

CPU

STM32F101x8

STM32F101xB

■ Six timers

– Three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 2 watchdog timers (Independent and

Window)

– SysTick timer: 24-bit downcounter

■ Up to 7 communication interfaces

– Up to 2 x I – Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 SPIs (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

Table 1. Device summary

Reference Part number

STM32F101x8

STM32F101xB

C interfaces (SMBus/PMBus)

packages

STM32F101C8, STM32F101R8 STM32F101V8, STM32F101T8

STM32F101RB, STM32F101VB, STM32F101CB STM32F101TB

April 2011 Doc ID 13586 Rev 14 1/87

www.st.com

Contents STM32F101x8, STM32F101xB

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15

2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.19 I

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19

2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Contents

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 33

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 33

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52

5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2.2 Evaluating the maximum junction temperature for an application . . . . . 78

Doc ID 13586 Rev 14 3/87

Contents STM32F101x8, STM32F101xB

7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Device features and peripheral counts (STM32F101xx medium-density

access line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Medium-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Maximum current consumption in Sleep mode, code running from Flash

or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 38

Table 16. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 42

Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 22. LSE oscillator characteristics (f

Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 39. I Table 40. SCL frequency (f

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

= 36 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

PCLK1

Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 42. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 43. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

ADC

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

LSE

Doc ID 13586 Rev 14 5/87

List of tables STM32F101x8, STM32F101xB

Table 44. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 45. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 46. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 72

Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 73

Table 49. LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data. . . . . . . . 74

Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 75

Table 51. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 76

Table 52. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 53. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 54. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB List of figures

List of figures

Figure 1. STM32F101xx medium-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM32F101xx medium-density access line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. STM32F101xx medium-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 5. STM32F101xx medium-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. STM32F101xx medium-density access line VFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . 23

Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . 23

Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 37

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 37

Figure 15. Typical current consumption on V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

BAT

Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V

= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V

= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 18. Typical current consumption in Standby mode versus temperature at V

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 20. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 23. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 24. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 25. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 26. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 27. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. I

C bus AC waveforms and measurement circuit

Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 31. SPI timing diagram - slave mode and CPHA = 1 Figure 32. SPI timing diagram - master mode

Figure 33. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 35. Power supply and reference decoupling (V Figure 36. Power supply and reference decoupling (V Figure 37. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline Figure 38. Recommended footprint (dimensions in mm) Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline Figure 40. Recommended footprint (dimensions in mm)

Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 74

Figure 42. Recommended footprint

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

with RTC on versus temperature at different

BAT

= 3.3 V and

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

REF+

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

not connected to V connected to V

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DDA

). . . . . . . . . . . . . . 69

DDA

). . . . . . . . . . . . . . . . . 70

Doc ID 13586 Rev 14 7/87

List of figures STM32F101x8, STM32F101xB

Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 75

Figure 44. Recommended footprint

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 46. Recommended footprint Figure 47. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32F101x8 and STM32F101xB medium-density access line microcontrollers. For

more details on the whole STMicroelectronics STM32F101xx family, please refer to

Section 2.2: Full compatibility throughout the family.

The medium-density STM32F101xx datasheet should be read in conjunction with the low-,

medium- and high-density STM32F10xxx reference manual.

For information on programming, erasing and protection of the internal Flash memory

please refer to the STM32F10xxx Flash programming manual.

The reference and Flash programming manuals are both available from the

STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical

Reference Manual, available from the www.arm.com website at the following address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 13586 Rev 14 9/87

Description STM32F101x8, STM32F101xB

2 Description

The STM32F101xB and STM32F101x8 medium-density access line family incorporates the

high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,

high-speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 16

Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB

buses. All devices offer standard communication interfaces (two I

three USARTs), one 12-bit ADC and three general-purpose 16-bit timers.

The STM32F101xx medium-density access line family operates in the –40 to +85 °C

temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving

mode allows the design of low-power applications.

The STM32F101xx medium-density access line family includes devices in four different

packages ranging from 36 pins to 100 pins. Depending on the device chosen, different sets

of peripherals are included, the description below gives an overview of the complete range

of peripherals proposed in this family.

These features make the STM32F101xx medium-density access line microcontroller family

suitable for a wide range of applications such as application control and user interface,

medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial

applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and

HVACs.

Cs, two SPIs, and up to

10/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Description

2.1 Device overview

Figure 1 shows the general block diagram of the device family.

Table 2. Device features and peripheral counts (STM32F101xx medium-density

access line)

Peripheral

Flash - Kbytes 64 128 64 128 64 128 64 128

SRAM - Kbytes 10 16 10 16 10 16 10 16

General -purpose 33 3 3

Timers

SPI 12 2 2

C 12 2 2

USART 23 3 3

Communication

12-bit synchronized ADC

number of channels

STM32F101Tx STM32F101Cx STM32F101Rx STM32F101Vx

10 channels

16 channels

GPIOs 26 37 51 80

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Packages VFQFPN36

Ambient temperature: –40 to +85 °C (see Ta b le 8 )

Junction temperature: –40 to +105 °C (see Ta b le 8 )

LQFP48,

VFQFPN48

LQFP64 LQFP100

Doc ID 13586 Rev 14 11/87

Description STM32F101x8, STM32F101xB

Temp sen sor

PA[15: 0]

EXTI

W W D G

NVIC

12bit A DC1

SWD

16AF

JTDI

JTCK/ SWCLK

JTMS/SWDIO

JNTRST

JTDO

NRST

= 2 to 3.6V

80AF

PB[15: 0]

PC[15:0 ]

AHB2

MOSI,MISO,SCK,NSS

SRAM

2x(8x16bit )

WAKEUP

GPIOA

GPIOB

GPIOC

max

: 36 MHz

SCL,SDA

I2C2

REF+

GP DMA

TIM2

TIM3

XTAL OSC

4-16 MHz

XTAL 32 k Hz

OSC_IN OSC_OUT

OSC32_OUT

OSC32_IN

PLL &

APB1 : F

max

=24 / 36 MHz

PCLK1

HCLK

CLOCK MANAG T

PCLK 2

as AF

VOLT. REG.

3.3V TO 1.8V

POWER

Backu p in terface

as AF

16 KB

RTC

RC 8 MHz

Cortex M3 CPU

USART1

USART2

SPI2

7 chan nels

Back up

reg

SCL,SDA ,SMBAL

I2C1

as AF

RX,TX, CTS, RTS,

USART3

REF-

PD[15: 0]

GPIOD

AHB: F

max

=36 MHz

4 Chann els

FCLK

RC 42 kHz

Stand by

IWDG

@VDD

@VBAT

POR / PDR

SUPPLY

@VDDA

VDDA

VSSA

@VDDA

BAT

CK, SmartCard as AF

RX,TX, CTS, RTS, Smart Card as AF

RX,TX, CTS, RTS,

APB2 : F

max

= 36 MHz

NVIC

SPI1

MOSI,MISO,

SCK,NSS as AF

int erface

@VDDA

SUPERVISION

PVD

Rst

Int

@VDD

AHB2

APB2

APB1

AWU

TAMPER-RTC

PE[15:0]

GPIOE

Flash 128 KB

BusM atrix

64 bit

Interfac e

Ibus

Dbus

pbus

obl

Flash

Trac e

Cont roll er

Syst em

TIM4

4 Channe ls

ai14385B

TRACECLK TRACED[0:3] as AS

SW/JTAG

TPIU

Trace/trig

CK, SmartCard as AF

Figure 1. STM32F101xx medium-density access line block diagram

12/87 Doc ID 13586 Rev 14

1. AF = alternate function on I/O port pin.

= –40 °C to +85 °C (junction temperature up to 105 °C).

2. T

STM32F101x8, STM32F101xB Description

Figure 2. Clock tree

FLITFCLK to Flash programming interface

36 MHz max

AHB Prescaler /1, 2..512

Prescaler

/1, 2, 4, 8, 16

TIM2,3, 4 If (APB1 prescaler =1) x1 else x2

Prescaler

/1, 2, 4, 8, 16

HCLK to AHB bus, core,

Clock

Enable (3 bits)

APB1

APB2

Legend:

HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal

memory and DMA

to Cortex System timer

FCLK Cortex free running clock

36 MHz max

Peripheral Clock

Enable (13 bits)

36 MHz max

Peripheral Clock

Enable (11 bits)

ADC Prescaler /2, 4, 6, 8

PCLK1 to APB1

peripherals

to TIM2, 3 and 4

TIMXCLK

eripheral Clock

P Enable (3 bits)

PCLK2

to APB2 peripherals

ADCCLK

to ADC

ai15104

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO

8 MHz

HSI RC

PLLSRC

4-16 MHz

HSE OSC

LSE OSC

32.768 kHz

LSI RC 40 kHz

Main Clock Output

HSI

PLLMUL

..., x16

x2, x3, x4

PLL

PLLXTPRE

MCO

/128

LSE

RTCSEL[1:0]

LSI

PLLCLK

HSE

SYSCLK

HSI

HSE

SYSCLK

36 MHz max

PLLCLK

CSS

RTCCLK

to RTC

to Independent Watchdog (IWDG)

IWDGCLK

HSI

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 13586 Rev 14 13/87

Description STM32F101x8, STM32F101xB

2.2 Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices.

Low- and high-density devices are an extension of the STM32F101x8/B devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Lowdensity devices feature lower Flash memory and RAM capacities and a timer less. Highdensity devices have higher Flash memory and RAM capacities, and additional peripherals like FSMC and DAC, while remaining fully compatible with the other members of the STM32F101xx family. The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.

Moreover, the STM32F101xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices

Pinout

16 KB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

144

100

2 × USARTs 2 × 16-bit timers

1 × SPI, 1 × I2C 1 × ADC

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

32 KB

Flash

(1)

64 KB

Flash

3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC

128 KB

Flash

256 KB

Flash

32 KB

RAM

384 KB

Flash

48 KB

RAM

512 KB

Flash

48 KB

RAM

5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I

Cs, 1 × ADC,

2 × DACs, FSMC (100 and 144 pins)

14/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Description

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices.

The STM32F101xx medium-density access line family having an embedded ARM core, is therefore compatible with all ARM tools and software.

2.3.2 Embedded Flash memory

64 or 128 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

2.3.4 Embedded SRAM

Up to 16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F101xx medium-density access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt latency.

Doc ID 13586 Rev 14 15/87

Description STM32F101x8, STM32F101xB

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

● V

For more details on how to connect power pins, refer to Figure 11: Power supply scheme.

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

Provided externally through V

, V

SSA

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

DDA

and PLL (minimum voltage to be applied to V V

and V

DDA

BAT

SSA

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

2.3.10 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when V external reset circuit.

pins.

must be connected to V

is below a specified threshold, V

is 2.4 V when the ADC is used).

DDA

and VSS, respectively.

is not present.

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the V

DD/VDDA

generated when V

16/87 Doc ID 13586 Rev 14

power supply and compares it to the V

DD/VDDA

drops below the V

PVD

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

DDA

is higher

STM32F101x8, STM32F101xB Description

than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 10: Embedded reset and power control block characteristics for the values of V

POR/PDR

and V

PVD

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop mode

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output.

2.3.12 Low-power modes

The STM32F101xx medium-density access line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.

Doc ID 13586 Rev 14 17/87

Description STM32F101x8, STM32F101xB

Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general purpose timers

TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on V

supply when present or through the V

registers used to store 20 bytes of user application data when V

The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

pin. The backup registers are ten 16-bit

BAT

power is not present.

2.3.15 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.

2.3.16 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

2.3.17 SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.18 General-purpose timers (TIMx)

There are three synchronizable general-purpose timers embedded in the STM32F101xx medium-density access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input

18/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Description

capture, output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

2.3.19 I²C bus

Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes.

They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

Up to two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

Both SPIs can be served by the DMA controller.

2.3.22 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.

2.3.23 ADC (analog to digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC can be served by the DMA controller.

Doc ID 13586 Rev 14 19/87

Description STM32F101x8, STM32F101xB

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

2.3.24 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.

2.3.25 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

20/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Pinouts and pin description

100999897969594939291908988878685848382818079787776

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

PE2 PE3 PE4 PE5 PE6

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

VSS_5

VDD_5

OSC_IN

OSC_OUT

NRST

PC0 PC1 PC2 PC3

VSSA

VREF-

VREF+

VDDA

PA 0- W K UP

PA 1 PA 2

VDD_2 VSS_2 NC PA 1 3 PA 1 2 PA 1 1 PA 1 0 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

VSS_1

VDD_1

VDD_3

VSS_3

PE1

PE0

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC12

PC11

PC10

PA15

PA14

26272829303132333435363738394041424344454647484950

ai14386b

LQFP100

PC13-TAMPER-RTC

3 Pinouts and pin description

Figure 3. STM32F101xx medium-density access line LQFP100 pinout

Doc ID 13586 Rev 14 21/87

Pinouts and pin description STM32F101x8, STM32F101xB

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0 PC1 PC2

PC3 VSSA VDDA

PA 0- W K UP

PA 1 PA 2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

VDD_2 VSS_2 PA 1 3 PA 1 2 PA 1 1 PA 1 0 PA 9 PA 8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

LQFP64

ai14387b

PC13-TAMPER-RTC

44 43 42 41 40 39 38 37

35 34

33 32 31 30 29 28 27 26 25

13 14 15 16 17 18

19 20 21 22

1 2 3 4 5 6 7 8 9 10 11

48 47 46 45

LQFP48

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

VDD_2 VSS_2 PA1 3 PA1 2 PA1 1 PA1 0 PA9 PA8 PB15 PB14 PB13 PB12

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST VSSA VDDA

PA 0- W K UP

PA 1 PA 2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA 1 5

PA 14

ai14378d

PC13-TAMPER-RTC

Figure 4. STM32F101xx medium-density access line LQFP64 pinout

Figure 5. STM32F101xx medium-density access line LQFP48 pinout

22/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Pinouts and pin description

ai18300

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST

VSSA

VDDA

PA0-WKUP

PA 1 PA 2

VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA 9 PA 8 PB15 PB14 PB13 PB12

VFQFPN48

47 46

45 444342 41

40 39 38 37

14 15

16 171819 20

21 22 23 24

SS_3

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

36 35 34 33 32 31 30 29 28

DD_3

DD_2

OSC_IN/PD0

SS_2

OSC_OUT/PD1

PA13

NRST

QFN36

PA12

SSA

23 PA11

DDA

PA10

PA0-WKUP

PA 9

PA 1

PA 8

PA 2 9

DD_1

10 11 12 13 14 15 16 17 18

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

SS_1

ai14654

Figure 6. STM32F101xx medium-density access line VFQPFN48 pinout

Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout

Doc ID 13586 Rev 14 23/87

Pinouts and pin description STM32F101x8, STM32F101xB

Pins

(2)

(1)

Table 4. Medium-density STM32F101xx pin definitions

Pin name

Type

LQFP64

LQFP48/

VFQFPN48

LQFP100

VFQFPN36

- - 1 - PE2 I/O

- - 2 - PE3 I/O

- - 3 - PE4 I/O

- - 4 - PE5 I/O

- - 5 - PE6 I/O

116- V

227-

338-

449-

--10- V

--11- V

BAT

PC13-TAMPER-

RTC

(5)

PC14-

OSC32_IN

PC15-

OSC32_OUT

SS_5

DD_5

(5)

I/O PC13

I/O PC14

I/O PC15

(5)

I / O level

5 5 12 2 OSC_IN I OSC_IN

6 6 13 3 OSC_OUT O OSC_OUT

7 7 14 4 NRST I/O NRST

- 8 15 - PC0 I/O PC0 ADC_IN10

- 9 16 - PC1 I/O PC1 ADC_IN11

- 10 17 - PC2 I/O PC2 ADC_IN12

- 11 18 - PC3 I/O PC3 ADC_IN13

812195 V

--20- V

--21- V

913226 V

SSA

REF-

REF+

DDA

10 14 23 7 PA0-WKUP I/O PA0

11 15 24 8 PA1 I/O PA1

12 16 25 9 PA2 I/O PA2

13 17 26 10 PA3 I/O PA3

-1827- V

SS_4

Main

function

(after reset)

(3)

Default Remap

PE2 TRACECLK

PE3 TRACED0

PE4 TRACED1

PE5 TRACED2

PE6 TRACED3

BAT

(6)

SS_5

DD_5

SSA

REF-

REF+

DDA

TAMPER-RTC

OSC32_IN

OSC32_OUT

WKUP/USART2_CTS

ADC_IN0/

TIM2_CH1_ETR

USART2_RTS

ADC_IN1/TIM2_CH2

USART2_TX

ADC_IN2/TIM2_CH3

USART2_RX

ADC_IN3/TIM2_CH4

SS_4

Alternate functions

(8)

(3)(4)

24/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Pinouts and pin description

Table 4. Medium-density STM32F101xx pin definitions (continued)

Pins

Pin name

LQFP64

LQFP48/

VFQFPN48

-1928- V

LQFP100

VFQFPN36

DD_4

14 20 29 11 PA4 I/O PA4

(2)

(1)

Typ e

Main

function

(3)

(after reset)

I / O level

DD_4

SPI1_NSS

15 21 30 12 PA5 I/O PA5 SPI1_SCK

16 22 31 13 PA6 I/O PA6

17 23 32 14 PA7 I/O PA7

SPI1_MISO

SPI1_MOSI

Alternate functions

Default Remap

(8)

/ADC_IN4

USART2_CK

TIM3_CH1

TIM3_CH2

(8)

/ADC_IN5

(8)

/ADC_IN6

(8)

/ADC_IN7

(8)

- 24 33 PC4 I/O PC4 ADC_IN14

- 25 34 PC5 I/O PC5 ADC_IN15

18 26 35 15 PB0 I/O PB0 ADC_IN8/TIM3_CH3

19 27 36 16 PB1 I/O PB1 ADC_IN9/TIM3_CH4

(8)

20 28 37 17 PB2 I/O FT PB2/BOOT1

- - 38 - PE7 I/O FT PE7

- - 39 - PE8 I/O FT PE8

- - 40 - PE9 I/O FT PE9

--41- PE10 I/OFT PE10

--42- PE11 I/OFT PE11

--43- PE12 I/OFT PE12

--44- PE13 I/OFT PE13

--45- PE14 I/OFT PE14

--46- PE15 I/OFT PE15

21 29 47 - PB10 I/O FT PB10

22 30 48 - PB11 I/O FT PB11

23 31 49 18 V

24 32 50 19 V

SS_1

DD_1

25 33 51 - PB12 I/O FT PB12

26 34 52 - PB13 I/O FT PB13

SS_1

DD_1

SPI2_NSS / I2C2_SMBA /

27 35 53 - PB14 I/O FT PB14

I2C2_SCL/

USART3_TX

I2C2_SDA/

USART3_RX

USART3_CK

SPI2_SCK/

USART3_CTS

SPI2_MISO/

USART3_RTS

(8)

28 36 54 - PB15 I/O FT PB15 SPI2_MOSI

(3)(4)

TIM2_CH3

TIM2_CH4

Doc ID 13586 Rev 14 25/87

Pinouts and pin description STM32F101x8, STM32F101xB

Table 4. Medium-density STM32F101xx pin definitions (continued)

Pins

LQFP64

LQFP48/

VFQFPN48

LQFP100

Pin name

VFQFPN36

(1)

(2)

Typ e

Main

function

(3)

(after reset)

I / O level

Alternate functions

Default Remap

- - 55 - PD8 I/O FT PD8 USART3_TX

- - 56 - PD9 I/O FT PD9 USART3_RX

- - 57 - PD10 I/O FT PD10 USART3_CK

- - 58 - PD11 I/O FT PD11 USART3_CTS

- - 59 - PD12 I/O FT PD12

- - 60 - PD13 I/O FT PD13 TIM4_CH2

- - 61 - PD14 I/O FT PD14 TIM4_CH3

- - 62 - PD15 I/O FT PD15 TIM4_CH4

- 37 63 - PC6 I/O FT PC6 TIM3_CH1

38 64 - PC7 I/O FT PC7 TIM3_CH2

39 65 - PC8 I/O FT PC8 TIM3_CH3

- 40 66 - PC9 I/O FT PC9 TIM3_CH4

29 41 67 20 PA8 I/O FT PA8 USART1_CK/MCO

30 42 68 21 PA9 I/O FT PA9 USART1_TX

31 43 69 22 PA10 I/O FT PA10 USART1_RX

(8)

32 44 70 23 PA11 I/O FT PA11 USART1_CTS

33 45 71 24 PA12 I/O FT PA12 USART1_RTS

34 46 72 25 PA13 I/O FT JTMS-SWDIO PA13

- - 73 - Not connected

35 47 74 26 V

36 48 75 27 V

SS_2

DD_2

SS_2

DD_2

37 49 76 28 PA14 I/O FT JTCK/SWCLK PA14

38 50 77 29 PA15 I/O FT JTDI

- 51 78 PC10 I/O FT PC10 USART3_TX

- 52 79 PC11 I/O FT PC11 USART3_RX

- 53 80 PC12 I/O FT PC12 USART3_CK

55812 PD0 I/OFTOSC_IN

6 6 82 3 PD1 I/O FT OSC_OUT

(7)

54 83 - PD2 I/O FT PD2 TIM3_ETR

- - 84 - PD3 I/O FT PD3 USART2_CTS

- - 85 - PD4 I/O FT PD4 USART2_RTS

(3)(4)

TIM4_CH1 /

USART3_RTS

TIM2_CH1_ETR/ PA15/ SPI1_NSS

26/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Pinouts and pin description

Table 4. Medium-density STM32F101xx pin definitions (continued)

Pins

LQFP64

LQFP48/

VFQFPN48

LQFP100

Pin name

VFQFPN36

(1)

(2)

Typ e

Main

function

(3)

(after reset)

I / O level

Alternate functions

Default Remap

- - 86 - PD5 I/O FT PD5 USART2_TX

- - 87 - PD6 I/O FT PD6 USART2_RX

- - 88 - PD7 I/O FT PD7 USART2_CK

39 55 89 30 PB3 I/O FT JTDO

40 56 90 31 PB4 I/O FT JNTRST

41 57 91 32 PB5 I/O PB5 I2C1_SMBAl

42 58 92 33 PB6 I/O FT PB6

43 59 93 34 PB7 I/O FT PB7

I2C1_SCL

TIM4_CH1

I2C1_SDA

TIM4_CH2

(8)

44 60 94 35 BOOT0 I BOOT0

45 61 95 - PB8 I/O FT PB8 TIM4_CH3

46 62 96 - PB9 I/O FT PB9 TIM4_CH4

(8)

- - 97 - PE0 I/O FT PE0 TIM4_ETR

- - 98 - PE1 I/O FT PE1

47 63 99 36 V

48 64 100 1 V

SS_3

DD_3

1. I = input, O = output, S = supply, HiZ= high impedance.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

7. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.

8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.

SS_3

DD_3

(3)(4)

TIM2_CH2 / PB3

TRACESWO

SPI1_SCK

PB4 / TIM3_CH1

SPI1_MISO

TIM3_CH2 / SPI1_MOSI

USART1_TX

USART1_RX

I2C1_SCL

I2C1_SDA

Doc ID 13586 Rev 14 27/87

Memory mapping STM32F101x8, STM32F101xB

4 Memory mapping

The memory map is shown in Figure 8.

Figure 8. Memory map

APB memory space

0xFFFF FFFF 0xE010 0000

0x6000 0000

0x4002 3400

0xFFFF FFFF

0xE010 0000

0xE000 0000

Cortex-M3 internal

peripherals

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800

0x1FFF F000

reserved

Option Bytes

System memory

0x4000 0000

Peripherals

reserved

0x2000 0000

0x0000 0000

SRAM

Reserved

0x0801 FFFF

0x0800 0000

0x0000 0000

Flash memory

Aliased to Flash or system memory depending on BOOT pins

0x4002 3000

0x4002 2400

0x4002 2000

0x4002 1400

0x4002 1000

0x4002 0400

0x4002 0000

0x4001 3C00

0x4001 3800

0x4001 3400

0x4001 3000

0x4001 2C00

0x4001 2800

0x4001 2400

0x4001 1C00

0x4001 1800

0x4001 1400

0x4001 1000

0x4001 0C00

0x4001 0800

0x4001 0400

0x4001 0000

0x4000 7400

0x4000 7000

0x4000 6C00

0x4000 6800

0x4000 6400

0x4000 6000

0x4000 5C00

0x4000 5800

0x4000 5400

0x4000 4C00

0x4000 4800

0x4000 4400

0x4000 3C00

0x4000 3800

0x4000 3400

0x4000 3000

0x4000 2C00

0x4000 2800

0x4000 0C00

0x4000 0800

0x4000 0400

0x4000 0000

reserved

CRC

reserved

Flash interface

reserved

RCC

reserved

DMA

reserved

USART1

reserved

SPI1

reserved

ADC1

reserved

Port E

Port D

Port C

Port B

Port A

EXTI

AFIO

reserved

PWR

BKP

reserved

I2C2

I2C1

reserved

USART3

USART2

reserved

SPI2

reserved

IWDG

WWDG

RTC

reserved

TIM4

TIM3

TIM2

ai14379d

35K

28/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2 Typical values

= 25 °C and TA = TAmax (given by

Unless otherwise specified, typical data are based on TA = 25 °C, V 2V≤ V

≤ 3.6 V voltage range). They are given only as design guidelines and are not

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

(mean±2Σ).

= 3.3 V (for the

Doc ID 13586 Rev 14 29/87

Electrical characteristics STM32F101x8, STM32F101xB

ai14125d

1/2/3/4/5

Analo g:

RCs, PLL,

...

Power switch

BAT

GP I/O s

OUT

Kernel logic

(CPU, Digital

& Memories)

Backup circuitry

(OSC32K,RTC,

Backup registers)

Wake-up logic

5 × 100 nF + 1 × 4.7 µF

1.8-3.6V

Regulator

1/2/3/4/5

DDA

REF+

REF-

SSA

ADC

Level shifter

Logic

10 nF

+ 1 µF

REF

10 nF

+ 1 µF

Figure 9. Pin loading conditions Figure 10. Pin input voltage

STM32F10xxx pin

C = 50 pF

5.1.6 Power supply scheme

Figure 11. Power supply scheme

ai14123b

STM32F10xxx pin

ai14124b

Caution: In Figure 11, the 4.7 µF capacitor must be connected to V

30/87 Doc ID 13586 Rev 14

DD3

STM32F101x8, STM32F101xB Electrical characteristics

ai14126

BAT

DDA

IDD_V

BAT

5.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,

Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 5. Voltage characteristics

Symbol Ratings Min Max Unit

VDD − V

|ΔV

DDx

− VSS|

SSX

ESD(HBM)

1. All main power (VDD, V supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum allowed injected current values.

External main supply voltage (including

and VDD)

DDA

Input voltage on five volt tolerant pin V

(2)

(1)

Input voltage on any other pin V

| Variations between different V

Variations between all the different ground pins

Electrostatic discharge voltage (human body model)

) and ground (VSS, V

DDA

SSA

–0.3 4.0

− 0.3 V

− 0.3 4.0

+ 4.0

power pins 50

see Section 5.3.11: Absolute

maximum ratings (electrical

sensitivity)

) pins must always be connected to the external power

Doc ID 13586 Rev 14 31/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 6. Current characteristics

Symbol Ratings Max. Unit

(1)

(5)

is the absolute sum of the

INJ(PIN)

150

-5/+0

± 5

± 25

INJ(PIN)

must

VDD

VSS

Total current into VDD/V

Total current out of V

power lines (source)

DDA

ground lines (sink)

Output current sunk by any I/O and control pin 25

INJ(PIN)

ΣI

INJ(PIN)

1. All main power (VDD, V supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC

characteristics.

3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage values.

4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. I never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage values.

5. When several inputs are submitted to a current injection, the maximum ΣI positive and negative injected currents (instantaneous values).

Output current source by any I/Os and control pin − 25

Injected current on five volt tolerant pins

(2)

Injected current on any other pin

(3)

(4)

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

) pins must always be connected to the external power

SSA

Table 7. Thermal characteristics

Symbol Ratings Value Unit

STG

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 8. General operating conditions

Symbol Parameter Conditions Min Max Unit

HCLK

PCLK1

PCLK2

DDA

BAT

Internal AHB clock frequency 0 36

Internal APB1 clock frequency 0 36

Internal APB2 clock frequency 0 36

Standard operating voltage 2 3.6 V

Analog operating voltage (ADC not used)

(1)

Analog operating voltage (ADC used)

Backup operating voltage 1.8 3.6 V

Must be the same potential

(2)

as V

MHzf

23.6

2.4 3.6

32/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

Table 8. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

LQFP100 434

Power dissipation at T

(3)

85 °C

LQFP64 444

LQFP48 363

VFQFPN36 1000

Maximum power dissipation –40 85 °C

TA Ambient temperature

Low power dissipation

J Junction temperature range –40 105 °C

1. When the ADC is used, refer to Table 42: ADC characteristics.

2. It is recommended to power V between V

3. If T

4. In low power dissipation state, T

is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal

characteristics on page 77).

Table 6.2: Thermal characteristics on page 77).

and V

can be tolerated during power-up and operation.

DDA

and V

can be extended to this range as long as TJ does not exceed TJmax (see

from the same source. A maximum difference of 300 mV

DDA

5.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Table 9. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0

VDD

fall time rate 20

(4)

–40 105 °C

∞

µs/V

∞

5.3.3 Embedded reset and power control block characteristics

The parameters given in Tab l e 1 0 are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in Tab l e 8 .

Doc ID 13586 Rev 14 33/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 10. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V

PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V

PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V

PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V

PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V

PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V

PVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V

PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V

PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V

PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V

PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V

PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V

PLS[2:0]=111 (rising edge) 2.76 2.88 3 V

PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V

(2)

PVDhyst

POR/PDR

PDRhyst

RSTTEMPO

1. The product behavior is guaranteed by design down to the minimum V

2. Guaranteed by design, not tested in production.

PVD hysteresis 100 mV

(1)

Power on/power down reset threshold

(2)

PDR hysteresis 40 mV

(2)

Reset temporization 1.5 2.5 4.5 ms

Falling edge

Rising edge 1.84 1.92 2.0 V

POR/PDR

1.8

value.

1.88 1.96 V

34/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

5.3.4 Embedded reference voltage

The parameters given in Tab l e 1 1 are derived from tests performed under the ambient temperature and V

Table 11. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

supply voltage conditions summarized in Tab l e 8 .

REFINT

S_vrefint

RERINT

Coeff

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V

ADC sampling time when reading

(1)

the internal reference voltage

Internal reference voltage spread

(2)

over the temperature range

(2)

Temperature coefficient 100

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

5.1

17.1

= 3 V ±10 mV 10 mV

(2)

µs

ppm/

°C

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

or VSS (no load)

wait state from 24 to 36 MHz)

● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

PCLK1

= f

HCLK/2

, f

PCLK2

= f

HCLK

The parameters given in Tab l e 1 2 are derived from tests performed under the ambient temperature and V

supply voltage conditions summarized in Tab l e 8 .

Doc ID 13586 Rev 14 35/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash

(1)

Max

Symbol Parameter Conditions f

36 MHz 28.6

External clock

(2)

, all

peripherals enabled

24 MHz 19.9

16 MHz 14.7

HCLK

= 85 °C

Unit

Supply current in Run mode

External clock

(4)

, all

peripherals Disabled

8 MHz 8.6

36 MHz 19.8

24 MHz 13.9

16 MHz 10.7

8 MHz 6.8

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

Table 13. Maximum current consumption in Run mode, code with data processing

HCLK

> 8 MHz.

running from RAM

(1)

Max

Symbol Parameter Conditions f

External clock

(2)

, all

peripherals enabled

Supply current in Run mode

External clock

(2)

all

peripherals disabled

HCLK

= 85 °C

36 MHz 24 mA

24 MHz 17.5

16 MHz 12.5

8 MHz 7.5

36 MHz 16

24 MHz 11.5

16 MHz 8.5

8 MHz 5.5

Unit

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

36/87 Doc ID 13586 Rev 14

HCLK

max, f

> 8 MHz.

HCLK

max.

STM32F101x8, STM32F101xB Electrical characteristics

-40 0 25 70 85

Temperature (°C)

Consumption (mA)

36MHz 16MHz 8MHz

-40 0 25 70 85

Temperature (°C)

Consumption (mA)

36MHz 16MHz 8MHz

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

Doc ID 13586 Rev 14 37/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 14. Maximum current consumption in Sleep mode, code running from Flash

or RAM

(1)

Max

Symbol Parameter Conditions f

36 MHz 15.5

External clock

(2)

all

peripherals enabled

24 MHz 11.5

16 MHz 8.5

HCLK

= 85 °C

Unit

Supply current in Sleep mode

External clock

(2)

, all

peripherals disabled

8 MHz 5.5

36 MHz 5

24 MHz 4.5

16 MHz 4

8 MHz 3

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

Table 15. Typical and maximum current consumptions in Stop and Standby modes

HCLK

Symbol Parameter Conditions

max and f

> 8 MHz.

DD/VBAT

= 2.0 V

max with peripherals enabled.

HCLK

(1)

Typ

= 2.4 V

/ V

BAT

DD/VBAT

= 3.3 V

Regulator in Run mode,

Supply current in Stop mode

Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Regulator in Low-Power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)

Low-speed internal RC oscillator and independent watchdog ON

- 23.5 24 200

- 13.5 14 180

-2.63.4-

Max

85 °C

Unit

(2)

µA

Supply current in Standby mode

Low-speed internal RC oscillator ON, independent watchdog OFF

Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF

DD_VBAT

Backup domain supply current

1. Typical values are measured at TA = 25 °C.

2. Based on characterization, not rested in production.

Low-speed oscillator and RTC ON 0.9 1.1 1.4 1.9

38/87 Doc ID 13586 Rev 14

-2.43.2-

-1.72 4

STM32F101x8, STM32F101xB Electrical characteristics

0.5

1.5

2.5

–40 °C 25 °C 70 °C 85 °C 105 °C

Temperature (°C)

Consumption ( µA )

2 V

2.4 V

3 V

3.6 V

ai17351

100

120

140

-45 25 70 90

Temperature (°C)

Consumption (µA)

3.3 V

3.6 V

Figure 15. Typical current consumption on V

values

BAT

with RTC on versus temperature at different

BAT

Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V

= 3.3 V and 3.6 V

Doc ID 13586 Rev 14 39/87

Electrical characteristics STM32F101x8, STM32F101xB

100

–45 °C 25 °C 85 °C

Temperature (°C)

Consumption (µA)

3.3 V

3.6 V

0.5

1.5

2.5

-45 25 70 90

Temperature (°C)

Consumption (µA)

3.3 V

3.6 V

Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V

= 3.3 V and 3.6 V

Figure 18. Typical current consumption in Standby mode versus temperature at V

= 3.3 V and

3.6 V

40/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 36 MHz)

● Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

PCLK2

PCLK1

= f

HCLK/4

The parameters given in Tab l e 1 6 are derived from tests performed under the ambient temperature and V

Table 16. Typical current consumption in Run mode, code with data processing

supply voltage conditions summarized in Tab l e 8 .

running from Flash

Symbol Parameter Conditions f

HCLK

All peripherals

36 MHz 19 14.8

or VSS (no load)

, f

PCLK2

(1)

Typ

enabled

(2)

= f

HCLK/2

All peripherals

, f

ADCCLK

(1)

Typ

disabled

Unit

24 MHz 12.9 10.1

16 MHz 9.3 7.4

8 MHz 5.5 4.6

External

(3)

clock

4 MHz 3.3 2.8

2 MHz 2.2 1.9

1 MHz 1.6 1.45

500 kHz 1.3 1.25

Supply

current in Run mode

125 kHz 1.08 1.06

36 MHz 18.3 14.1

24 MHz 12.2 9.5

Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency

16 MHz 8.5 6.8

8 MHz 4.9 4

4 MHz 2.7 2.2

2 MHz 1.6 1.4

1 MHz 1.02 0.9

500 kHz 0.73 0.67

125 kHz 0.5 0.48

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

= 3.3 V.

> 8 MHz.

Doc ID 13586 Rev 14 41/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 17. Typical current consumption in Sleep mode, code running from Flash or

RAM

Symbol Parameter Conditions f

36 MHz 7.6 3.1

24 MHz 5.3 2.3

16 MHz 3.8 1.8

8 MHz 2.1 1.2

External clock

(3)

4 MHz 1.6 1.1

2 MHz 1.3 1

1 MHz 1.11 0.98

500 kHz 1.04 0.96

Supply

current in Sleep mode

125 kHz 0.98 0.95

36 MHz 7 2.5

24 MHz 4.8 1.8

Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency

16 MHz 3.2 1.2

8 MHz 1.6 0.6

4 MHz 1 0.5

2 MHz 0.72 0.47

1 MHz 0.56 0.44

HCLK

(1)

Typ

All peripherals

enabled

(2)

All peripherals

(1)

Typ

disabled

Unit

500 kHz 0.49 0.42

125 kHz 0.43 0.41

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

HCLK

= 3.3 V.

> 8 MHz.

42/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Ta bl e 1 8. The MCU is placed under the following conditions:

● all I/O pins are in input mode with a static value at V

● all peripherals are disabled unless otherwise mentioned

● the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

● ambient operating temperature and V

supply voltage conditions summarized in

Ta bl e 5 .

Table 18. Peripheral current consumption

Peripheral Typical consumption at 25 °C

TIM2 0.6

TIM3 0.6

TIM4 0.6

APB1

SPI2 0.08

USART2 0.21

or VSS (no load)

(1)

Unit

USART3 0.21

I2C1 0.18

I2C2 0.18

GPIO A 0.21

GPIO B 0.21

GPIO C 0.21

GPIO D 0.21

APB2

GPIO E 0.21

(2)

ADC1

SPI1 0.24

USART1 0.35

1. f

2. Specific conditions for ADC: f

= 36 MHz, f

HCLK

in the ADC_CR2 register is set to 1.

APB1

= f

HCLK

/2, f

HCLK

= f

APB2

= 28 MHz, f

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Tab l e 1 9 result from tests performed using an high-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Ta bl e 8 .

1.4

, default prescaler value for each peripheral.

HCLK

= f

APB1

HCLK

/2, f

APB2

= f

HCLK

, f

ADCCLK

= f

/2, ADON bit

APB2

Doc ID 13586 Rev 14 43/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 19. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

HSE_ext

w(HSE)

r(HSE)

f(HSE)

in(HSE)

DuCy

HSEH

HSEL

User external clock source frequency

(1)

OSC_IN input pin high level voltage 0.7V

OSC_IN input pin low level voltage V

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle 45 55 %

(HSE)

OSC_IN Input leakage current VSS≤ VIN≤ V

(1)

1825MHz

5pF

0.3V

±1 µA

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Tab l e 2 0 result from tests performed using an low-speed external clock source, and under the ambient temperature and supply voltage conditions summarized in Ta bl e 8 .

Table 20. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

LSE_ext

LSEH

User external clock source frequency

(1)

OSC32_IN input pin high level voltage

0.7V

32.768 1000 kHz

(LSE)

OSC32_IN input pin low level voltage

OSC32_IN high or low time

(1)

450

0.3V

OSC32_IN rise or fall time

OSC32_IN input capacitance

(1)

5pF

Duty cycle 30 70 %

OSC32_IN Input leakage current VSS≤ VIN≤ V

±1 µA

LSEL

w(LSE)

r(LSE)

f(LSE)

in(LSE)

DuCy

1. Guaranteed by design, not tested in production.

44/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

ai14127b

OS C _I N

External

STM32F10xxx

clock source

HSEH

f(HSE)

W(HSE)

90%

10%

HSE

r(HSE)

W(HSE)

HSE_ext

HSEL

Figure 19. High-speed external clock source AC timing diagram

Figure 20. Low-speed external clock source AC timing diagram

LSEH

90%

LSEL

10%

r(LSE)

External clock source

LSE_ext

LSE

f(LSE)

OSC32_IN

W(LSE)

STM32F10xxx

ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 21 . In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Doc ID 13586 Rev 14 45/87

Electrical characteristics STM32F101x8, STM32F101xB

ai14128b

OSC_OU T

OSC_IN

HSE

STM32F10xxx

8 MHz resonator

Resonator with integrated capacitors

Bias

controlled

gain

EXT

(1)

Table 21. HSE 4-16 MHz oscillator characteristics

(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

OSC_IN

Oscillator frequency 4 8 16 MHz

Feedback resistor 200 kΩ

Recommended load capacitance

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

versus equivalent serial resistance of the crystal (R

HSE driving current

Oscillator transconductance Startup 25 mA/V

(4)

Startup time VDD is stabilized 2 ms

RS = 30 Ω 30 pF

(3)

)

= 3.3 V, VIN = V

with 30 pF load

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

1mA

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 21). C

and C

are usually the

same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

can be used as a rough estimate of the combined pin and board capacitance) when sizing C

and CL2. Refer to the application note AN2867 “Oscillator design guide for ST

microcontrollers” available from the ST website www.st.com.

46/87 Doc ID 13586 Rev 14

Figure 21. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Ta bl e 22 . In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

STM32F101x8, STM32F101xB Electrical characteristics

resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 22. LSE oscillator characteristics (f

= 32.768 kHz)

LSE

Symbol Parameter Conditions Min Typ Max Unit

(1) (2)

Feedback resistor 5 MΩ

Recommended load capacitance

versus equivalent serial resistance of the crystal (R

LSE driving current

)

RS = 30 KΩ 15 pF

= 3.3 V

VIN = V

1.4 µA

Oscillator transconductance 5 µA/V

TA = 50 °C 1.5

= 25 °C 2.5

= 10 °C 4

= 0 °C 6

(3)

SU(LSE)

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Startup time

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

stabilized

= -10 °C 10

= -20 °C 17

= -30 °C 32

= -40 °C 60

Note: For CL1 and C

it is recommended to use high-quality ceramic capacitors in the 5 pF to

15 pF range selected to match the requirements of the crystal or resonator. C usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C Load capacitance C C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C

between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of C

to use a resonator with a load capacitance C capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of C then C

= CL2 = 8 pF.

Doc ID 13586 Rev 14 47/87

and CL2.

and C

and CL2 (15 pF) it is strongly recommended

≤

7 pF. Never use a resonator with a load

= 6 pF, and C

stray

L2,

where

= 2 pF,

are

Electrical characteristics STM32F101x8, STM32F101xB

ai14129b

OSC32_OU T

OSC32_IN

LSE

STM32F10xxx

32.768 KHz resonator

Resonator with integrated capacitors

Bias

controlled

gain

Figure 22. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

The parameters given in Tab l e 2 3 are derived from tests performed under the ambient temperature and V

High-speed internal (HSI) RC oscillator

supply voltage conditions summarized in Tab l e 8 .

Table 23. HSI oscillator characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

HSI

DuCy

ACC

su(HSI)

DD(HSI)

1. V

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com.

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

Frequency 8 MHz

Duty cycle 45 55 %

(HSI)

User-trimmed with the RCC_CR register

Accuracy of the HSI

HSI

oscillator

Factorycalibrated

HSI oscillator

(4)

startup time

HSI oscillator power

(4)

consumption

= 3.3 V, TA = –40 to 105 °C unless otherwise specified.

(2)

TA = –40 to 105 °C –2 2.5 %

= –10 to 85 °C –1.5 2.2 %

(4)

= 0 to 70 °C –1.3 2 %

= 25 °C –1.1 1.8 %

12µs

80 100 µA

(3)

48/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 24. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(2)

LSI

su(LSI)

DD(LSI)

1. V

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Frequency 30 40 60 kHz

(3)

LSI oscillator startup time 85 µs

(3)

LSI oscillator power consumption 0.65 1.2 µA

= 3 V, TA = –40 to 85 °C unless otherwise specified.

(1)

Wakeup time from low-power mode

The wakeup times given in Ta bl e 25 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V voltage conditions summarized in Tabl e 8 .

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit

WUSLEEP

WUSTOP

WUSTDBY

1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.

(1)

5.3.8 PLL characteristics

The parameters given in Tab l e 2 6 are derived from tests performed under the ambient temperature and V

Table 26. PLL characteristics

Symbol Parameter

PLL_IN

PLL_OUT

(1)

Wakeup from Sleep mode 1.8 µs

Wakeup from Stop mode (regulator in run mode) 3.6

Wakeup from Stop mode (regulator in low-power mode) 5.4

(1)

Wakeup from Standby mode 50 µs

supply voltage conditions summarized in Tab l e 8 .

Val ue

PLL input clock

(2)

(1)

Min

Typ Max

18.025MHz

(1)

PLL input clock duty cycle 40 60 %

PLL multiplier output clock 16 36 MHz

supply

µs

Unit

Doc ID 13586 Rev 14 49/87

Electrical characteristics STM32F101x8, STM32F101xB

Table 26. PLL characteristics

Val ue

Symbol Parameter

Min

(1)

Typ Max

(1)

Unit

LOCK

PLL lock time 200 µs

Jitter Cycle-to-cycle jitter 300 ps

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 85 °C unless otherwise specified.

Table 27. Flash memory characteristics

Symbol Parameter Conditions Min

prog

ERASE

prog

1. Guaranteed by design, not tested in production.

16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs

Page (1 KB) erase time TA = –40 to +85 °C 20 40 ms

Mass erase time TA = –40 to +85 °C 20 40 ms

Supply current

Programming voltage 2 3.6 V

Read mode f

= 36 MHz with 1 wait

HCLK

state, V

= 3.3 V

Write / Erase modes f

= 36 MHz, VDD = 3.3 V

HCLK

Power-down mode / Halt,

= 3.0 to 3.6 V

(1)

Typ Max

20 mA

50 µA

(1)

Unit

5mA

Table 28. Flash memory endurance and data retention

Symbol Parameter Conditions

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Endurance TA = –40 °C to 85 °C

END

RET

Data retention

TA = 85 °C, 1 kcycle

Susceptibility tests are performed on a sample basis during device characterization.

50/87 Doc ID 13586 Rev 14

= 55 °C, 10 kcycle

(2)

Min

Val ue

(1)

Typ Max

Unit

kcycles

Ye a r s

STM32F101x8, STM32F101xB Electrical characteristics

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab l e 2 9 . They are based on the EMS levels and classes defined in application note AN1709.

Table 29. EMS characteristics

Symbol Parameter Conditions Level/Class

= 3.3 V, TA = +25 °C,

FESD

EFTB

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on VDD and V

pins

to induce a functional disturbance

= 36 MHz

HCLK

conforms to IEC 61000-4-2

VDD = 3.3 V, TA = +25 °C, f

= 36 MHz

HCLK

conforms to IEC 61000-4-4

and

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Doc ID 13586 Rev 14 51/87

Electrical characteristics STM32F101x8, STM32F101xB

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Symbol Parameter Conditions

Monitored

frequency band

0.1 MHz to 30 MHz 7

= 3.3 V, TA = 25 °C,

EMI

Peak level

LQFP100 package compliant with IEC 61967-2

130 MHz to 1GHz 13

SAE EMI Level 3.5 -

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 31. ESD absolute maximum ratings

Symbol Ratings Conditions Class

Max vs. [f

8/36 MHz

HSE/fHCLK

Maximum

value

(1)

]

Unit

dBµV30 MHz to 130 MHz 8

Unit

ESD(HBM)

ESD(CDM)

1. Based on characterization results, not tested in production.

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

52/87 Doc ID 13586 Rev 14

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 32. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class T

TA = +25 °C conforming to JESD22-A114

TA = +25 °C conforming to JESD22-C101

2 2000

II 500

= +85 °C conforming to JESD78A II level A

STM32F101x8, STM32F101xB Electrical characteristics

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or above V operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation).

The test results are given in Tab l e 3 3

Table 33. I/O current injection susceptibility

Symbol Description

(for standard, 3 V-capable I/O pins) should be avoided during normal product

Functional susceptibility

Negative injection

Positive

injection

Unit

INJ

Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins -5 +0

-0 +0

Injected current on any other pin -5 +5

Doc ID 13586 Rev 14 53/87

Electrical characteristics STM32F101x8, STM32F101xB

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Ta bl e 3 4 are derived from tests performed under the conditions summarized in Tab l e 8 . All I/Os are CMOS and TTL compliant.

Table 34. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Standard IO input low level voltage

IO FT

(1)

voltage

Standard IO input high level voltage

IO FT

(1)

voltage

input low level

input high level

–0.3 0.28*(V

–0.3 0.32*(V

0.41*(V

> 2 V

≤ 2 V 5.2

0.42*(V

-2 V)+1.3 V VDD+0.3 V

-2 V)+1 V

-2 V)+0.8 V V

-2V)+0.75 V V

5.5

Standard IO Schmitt trigger voltage

hys

hysteresis

IO FT Schmitt trigger voltage hysteresis

Input leakage current

lkg

(2)

(4)

≤ VIN≤ V

Standard I/Os

= 5 V

I/O FT

1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

Weak pull-up equivalent

(5)

resistor

Weak pull-down equivalent resistor

(5)

I/O pin capacitance 5 pF

= V

disabled.

PMOS/NMOS contribution

to the series resistance is minimum (~10% order).

200 mV

(3)

5% V

±1

30 40 50 kΩ

µA

54/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

ai17277b

VDD (V)

1.3

0.8

2 3.6

Input range

not guaranteed

1.59

2.7

=0.41(V

-2)+1.3

0.7

CMOS standard requirement V

=0.65V

3.3

VIH/VIL (V)

CMOS standard requirement V

=0.35V

= 0.28(V

–2)+0.8

1.25

1.96

1.71

1.59

1.08

ILmax

IHmin

AI





)NPUTRANGE

NOTGUARANTEED

6)(6),6













44,REQUIREMENTS 6)(6

)(

6



6



44,REQUIREMENTS 6),6

6$$6

),MAX

)(MIN

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and in Figure 25 and Figure 26 for 5 V tolerant I/Os.

Figure 23. Standard I/O input characteristics - CMOS port

Figure 24. Standard I/O input characteristics - TTL port

Doc ID 13586 Rev 14 55/87

Electrical characteristics STM32F101x8, STM32F101xB

6$$



 

#-/3STANDARDREQUIREMENTS6

)(

6



#-/3STANDARDREQUIRMENT6

6















 

 

 

6)(6),6

6$$6

)NPUTRANGE

NOTGUARANTEED

AIB

)(

6



6







 

NOTGUARANTEED

)NPUTRANGE







44,REQUIREMENT6)(6

)(

6



6



44,REQUIREMENTS6),6

6)(6),6

6$$6

),MAX

)(MIN

AI

Figure 25. 5 V tolerant I/O input characteristics - CMOS port

Figure 26. 5 V tolerant I/O input characteristics - TTL port

56/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed V

OL/VOH

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V I

(see Ta bl e 6 ).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V I

(see Ta bl e 6 ).

VSS

cannot exceed the absolute maximum rating

DD,

cannot exceed the absolute maximum rating

plus the maximum Run

DD,

plus the maximum Run

Output voltage levels

Unless otherwise specified, the parameters given in Ta bl e 3 5 are derived from tests performed under the ambient temperature and V in Ta bl e 8 . All I/Os are CMOS and TTL compliant.

Table 35. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

supply voltage conditions summarized

Output Low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output High level voltage for an I/O pin

(3)

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

4. Based on characterization data, not tested in production.

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

and the sum of I

Table 6 and the sum of I

(I/O ports and control pins) must not exceed I

CMOS port

2.7 V < VDD < 3.6 V

TTL port

2.7 V < V

= +20 mA

2.7 V < VDD < 3.6 V

= +6 mA

2 V < VDD < 2.7 V

VSS

= +8 mA,

(2)

= +8 mA

< 3.6 V

VDD

(2)

(4)

–0.4

2.4

–1.3

VDD–0.4

0.4

1.3

0.4

Doc ID 13586 Rev 14 57/87

Electrical characteristics STM32F101x8, STM32F101xB

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 27 and

Ta bl e 3 6, respectively.

Unless otherwise specified, the parameters given in Ta bl e 3 6 are derived from tests performed under the ambient temperature and V in Ta bl e 8 .

Table 36. I/O AC characteristics

MODEx

[1:0] bit

value

Symbol Parameter Conditions Max Unit

(1)

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

max(IO)out

f(IO)out

r(IO)out

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum frequency

Output high to low level fall time

Output low to high level rise time

Maximum Frequency

Output high to low level fall time

Output low to high level rise time

Pulse width of external

-t

EXTIpw

signals detected by the EXTI controller

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 27.

3. Guaranteed by design, not tested in production.

(1)

(2)

supply voltage conditions summarized

CL = 50 pF, V

= 50 pF, V

CL= 50 pF, V

= 50 pF, V

CL= 30 pF, V

= 50 pF, V

CL = 30 pF, V

= 50 pF, V

CL = 50 pF, VDD = 2 V to 2.7 V 12

= 30 pF, V

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

(3)

125

= 2 V to 3.6 V

= 2 V to 3.6 V 10 MHz

= 2 V to 3.6 V

= 2.7 V to 3.6 V 50 MHz

= 2.7 V to 3.6 V 30 MHz

= 2 V to 2.7 V 20 MHz

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2.7 V to 3.6 V 5

= 2.7 V to 3.6 V 8

= 2 V to 2.7 V 12

125

(3)

10 ns

58/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

ai14131

10%

90%

50%

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)

10 %

50%

90%

when loaded by 50pF

r(IO)out

ai14132d

STM32F10x

NRST

(2)

Filter

Internal reset

0.1 µF

External reset circuit

(1)

Figure 27. I/O AC characteristics definition

5.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

Unless otherwise specified, the parameters given in Ta bl e 3 7 are derived from tests performed under the ambient temperature and V in Ta bl e 8 .

Table 37. NRST pin characteristics

(see Ta bl e 3 4).

supply voltage conditions summarized

Symbol Parameter Conditions Min Typ Max Unit

IL(NRST)

IH(NRST)

NF(NRST)

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

(1)

NRST Input low level voltage –0.5 0.8

(1)

NRST Input high level voltage 2 VDD+0.5

hys(NRST)

F(NRST)

the series resistance must be minimum

NRST Schmitt trigger voltage hysteresis

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse 100 ns

(1)

NRST Input not filtered pulse 300 ns

(~10% order).

(2)

200 mV

= V

30 40 50 kΩ

Figure 28. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 37. Otherwise the reset will not be taken into account by the device.

Doc ID 13586 Rev 14 59/87

max level specified in

IL(NRST)

Electrical characteristics STM32F101x8, STM32F101xB

5.3.15 TIM timer characteristics

The parameters given in Tab l e 3 8 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 38. TIMx

Symbol Parameter Conditions Min Max Unit

(1)

characteristics

res(TIM)

EXT

Res

Timer resolution time

Timer external clock frequency on CH1 to CH4

Timer resolution 16 bit

TIM

16-bit counter clock period

COUNTER

when internal clock is selected

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.

Maximum possible count

5.3.16 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 3 9 are derived from tests performed under the ambient temperature, f conditions summarized in Ta bl e 8 .

The STM32F101xx medium-density access line I standard I SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V

The I

injection characteristics

(SDA and SCL)

C communication protocol with the following restrictions: t

C characteristics are described in Ta b le 3 9 . Refer also to

for more details on the input/output alternate function characteristics

TIMxCLK

= 36 MHz

27.8 ns

TIMxCLK

018MHz

1 65536

TIMxCLK

= 36 MHz

0.0278 1820 µs

65536 × 65536

TIMxCLK

PCLK1

= 36 MHz

119.2 s

frequency and VDD supply voltage

C interface meets the requirements of the

he I/O pins SDA and

is disabled, but is still present.

Section 5.3.12: I/O current

TIMxCLK

MHz

TIMxCLK

60/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

Table 39. I2C characteristics

Symbol Parameter

Standard mode I

2C(1)

Fast mode I2C

Min Max Min Max

(1)(2)

Unit

w(SCLL)

w(SCLH)

su(SDA)

h(SDA)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

h(STA)

su(STA)

su(STO)

w(STO:STA)

Guaranteed by design, not tested in production.

2. f

PCLK1

4 MHz to achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

3. period of SCL signal.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

4. undefined region of the falling edge of SCL.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0

(3)

SDA and SCL rise time 1000 20+0.1C

(4)

SDA and SCL fall time 300 300

Start condition hold time 4.0 0.6

Repeated Start condition setup time

4.7 0.6

Stop condition setup time 4.0 0.6 µs

Stop to Start condition time (bus free)

Capacitive load for each bus line 400 400 pF

must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than

4.7 1.3 µs

900

300

µs

(3)

µs

Doc ID 13586 Rev 14 61/87

Electrical characteristics STM32F101x8, STM32F101xB

ai14133d

Start

SDA

100 Ω

4.7kΩ

I²C bus

4.7kΩ

100 Ω

STM32F10x

SDA

SCL

f(SDA)

r(SDA)

SCL

h(STA)

w(SCLH)

w(SCLL)

su(SDA)

r(SCL)

f(SCL)

h(SDA)

Start repeated

Start

su(STA)

su(STO)

Stop

su(STO:STA)

Figure 29. I2C bus AC waveforms and measurement circuit

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

Table 40. SCL frequency (f

(kHz)

SCL

= 36 MHz, VDD = 3.3 V)

PCLK1

400 0x801E

(1)(2)

I2C_CCR value

(1)

= 4.7 kΩ

300 0x8028

200 0x803C

100 0x00B4

50 0x0168

20 0x0384

= External pull-up resistance, f

1. R

2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application.

62/87 Doc ID 13586 Rev 14

SCL

= I2C speed,

STM32F101x8, STM32F101xB Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 1 are derived from tests performed under the ambient temperature, f conditions summarized in Ta bl e 8 .

Refer to Section 5.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 41. SPI characteristics

Symbol Parameter Conditions Min Max Unit

frequency and VDD supply voltage

PCLKx

SCK

1/t

c(SCK)

r(SCK)

f(SCK)

su(NSS)

h(NSS)

w(SCKH)

w(SCKL)

su(MI)

su(SI)

h(MI)

h(SI)

a(SO)

dis(SO)

v(SO)

v(MO)

h(SO)

h(MO)

SPI clock frequency

Master mode 0 18

Slave mode 0 18

SPI clock rise and fall time

(1)

NSS setup time Slave mode 4 t

(1)

NSS hold time Slave mode 73

(1)

SCK high and low time

(1)

Data input setup time

(1)

Master mode

Data input setup time

(1)

Capacitive load: C = 30 pF 8

Master mode, f

= 36 MHz,

PCLK

presc = 4

SPI1 1

SPI2 5

Slave mode

Data input hold time

(1)

Master mode

Data input hold time

(1)

SPI1 1

SPI2 5

Slave mode

Slave mode, f

(1)(2)

Data output access time

presc = 4

Slave mode, f

(1)(3)

Data output disable time Slave mode 10

(1)

Data output valid time Slave mode (after enable edge) 25

(1)

Data output valid time

(1)

Data output hold time

(1)

Master mode (after enable edge)

Slave mode (after enable edge) 25

Master mode (after enable

= 36 MHz,

PCLK

= 24 MHz 0 4 t

PCLK

edge)

MHz

PCLK

50 60

055

PCLK

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Doc ID 13586 Rev 14 63/87

Electrical characteristics STM32F101x8, STM32F101xB

ai14134c

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

SU(NSS)

c(SCK)

h(NSS)

a(SO)

w(SCKH)

w(SCKL)

v(SO)

h(SO)

r(SCK)

f(SCK)

dis(SO)

su(SI)

h(SI)

NSS input

Figure 30. SPI timing diagram - slave mode and CPHA = 0

Figure 31. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

(1)

64/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP UT

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

h(MI)

High

SCK Input

CPHA=1

CPOL=0

CPOL=1

su(MI)

v(MO)

h(MO)

Figure 32. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3V

and 0.7V

Doc ID 13586 Rev 14 65/87

Electrical characteristics STM32F101x8, STM32F101xB

5.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 2 are derived from tests performed under the ambient temperature, f conditions summarized in Ta bl e 8 .

Note: It is recommended to perform a calibration after each power-up.

Table 42. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

frequency and V

PCLK2

supply voltage

DDA

TRIG

CAL

STAB

CONV

DDA

REF+

VREF

ADC

(2)

AIN

ADC

(2)

lat

latr

(2)

Power supply 2.4 3.6 V

Positive reference voltage 2.4 V

Current on the V pin

REF

input

160

(1)

220

ADC clock frequency 0.6 14 MHz

Sampling rate 0.05 1 MHz

= 14 MHz 823 kHz

(2)

External trigger frequency

Conversion voltage range

(2)

External input impedance

(2)

Sampling switch resistance 1 kΩ

Internal sample and hold

(2)

(3)

ADC

See Equation 1 and

Ta bl e 4 3 for details

0 (V

SSA

or V

tied to ground)

REF-

REF+

capacitor

= 14 MHz 5.9 µs

(2)

Calibration time

ADC

83 1/f

= 14 MHz 0.214 µs

Injection trigger conversion latency

Regular trigger conversion

(2)

latency

ADC

= 14 MHz 0.143 µs

ADC

0.107 17.1 µs

Sampling time f

(2)

Power-up time 0 0 1 µs

Total conversion time

(2)

(including sampling time)

= 14 MHz

ADC

= 14 MHz 1 18 µs

ADC

1.5 239.5 1/f

14 to 252 (t

for sampling +12.5 for

successive approximation)

DDA

(1)

17 1/f

µA

ADC

50 kΩ

8pF

ADC

(4)

1/f

ADC

(4)

1/f

ADC

1/f

ADC

1. Based on characterization results, not tested in production.

2. Guaranteed by design, not tested in production.

3. V

can be internally connected to V

REF+

Refer to Section 3: Pinouts and pin description for further details.

4. For external triggers, a delay of 1/f

and V

DDA

must be added to the latency specified in Table 42.

PCLK2

can be internally connected to V

REF-

66/87 Doc ID 13586 Rev 14

, depending on the package.

SSA

STM32F101x8, STM32F101xB Electrical characteristics

AIN

ADCCADC

N2+

()ln××

------------------------------------------------------------- - R

ADC

–<

Equation 1: R

max formula:

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 43. R

Ts (cycles) tS (µs) R

max for f

AIN

= 14 MHz

ADC

(1)

max (kΩ)

AIN

1.5 0.11 0.4

7.5 0.54 5.9

13.5 0.96 11.4

28.5 2.04 25.2

41.5 2.96 37.2

55.5 3.96 50

71.5 5.11 NA

239.5 17.1 NA

1. Guaranteed by design, not tested in production.

Table 44. ADC accuracy - limited test conditions

Symbol Parameter Test conditions Typ Max

(1) (2)

(3)

Unit

ET Total unadjusted error

EO Offset error ±1 ±1.5

EG Gain error ±0.5 ±1.5

ED Differential linearity error ±0.7 ±1

EL Integral linearity error ±0.8 ±1.5

= 28 MHz,

PCLK2

= 14 MHz, R

ADC

= 3 V to 3.6 V

DDA

= 25 °C

< 10 kΩ,

AIN

Measurements made after ADC calibration

±1.3 ±2

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I affect the ADC accuracy.

INJ(PIN)

and ΣI

in Section 5.3.12 does not

INJ(PIN)

3. Based on characterization, not tested in production.

Doc ID 13586 Rev 14 67/87

Electrical characteristics STM32F101x8, STM32F101xB

1LSB

IDEAL

(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

=Offset Error: deviation between the first actual

transition and the first ideal one.

=Gain Error: deviation between the last ideal

transition and the last actual one.

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.

=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.

4095

4094

4093

1234567

4093 4094 4095 4096

(1)

(2)

(3)

DDA

SSA

ai14395b

REF+

4096

(or depending on package)]

DDA

4096

[1LSB

IDEAL =

Table 45. ADC accuracy

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error ±1.5 ±2.5

EG Gain error ±1.5 ±3

ED Differential linearity error ±1 ±2

(1) (2) (3)

= 28 MHz,

PCLK2

= 14 MHz, R

ADC

= 2.4 V to 3.6 V

DDA

< 10 kΩ,

AIN

Measurements made after ADC calibration

(4)

±2 ±5

EL Integral linearity error ±1.5 ±3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I affect the ADC accuracy.

, frequency, V

INJ(PIN)

and temperature ranges.

REF

and ΣI

in Section 5.3.12 does not

INJ(PIN)

4. Based on characterization, not tested in production.

Figure 33. ADC accuracy characteristics

Unit

LSB

68/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Electrical characteristics

ai14139d

STM32F10xxx

AINx

IL±1 µA

0.6 V

AIN

(1)

parasitic

AIN

0.6 V

ADC

(1)

ADC

(1)

12-bit

converter

Sample and hold ADC converter

Figure 34. Typical connection diagram using the ADC

1. Refer to Table 42 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C this, f

should be reduced.

ADC

AIN

, R

parasitic

ADC

and C

ADC

value will downgrade conversion accuracy. To remedy

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 35 or Figure 36, depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 35. Power supply and reference decoupling (V

1 µF // 10 nF

is connected to V

REF+

or not. The 10 nF capacitors should be

DDA

not connected to V

REF+

STM32F10xxx

REF+

DDA

)

1 µF // 10 nF

SSA/VREF-

ai14380b

1. V

REF+

and V

inputs are available only on 100-pin packages.

REF-

Doc ID 13586 Rev 14 69/87

Electrical characteristics STM32F101x8, STM32F101xB

Figure 36. Power supply and reference decoupling (V

1 µF // 10 nF

1. V

REF+

and V

inputs are available only on 100-pin packages.

REF-

5.3.18 Temperature sensor characteristics

REF+

STM32F10xxx

REF+/VDDA

REF–/VSSA

connected to V

ai14381b

DDA

)

Table 46. TS characteristics

Symbol Parameter Min Typ Max Unit

(1)

Avg_Slope

(1)

(2)

START

S_temp

(3)(2)

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

(1)

Average slope 4.0 4.3 4.6 mV/°C

linearity with temperature

SENSE

±1 ±2

Voltage at 25°C 1.34 1.43 1.52 V

Startup time 4 10 µs

ADC sampling time when reading the temperature

17.1 µs

°C

70/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Package characteristics

6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Doc ID 13586 Rev 14 71/87

Package characteristics STM32F101x8, STM32F101xB

Seating

Plane

ddd C

Pin no. 1 ID

R = 0.20

Bottom View

V0_ME

0.50

7.30

0.75

5.80

6.20

5.60

ai15799

0.55

0.30

0.20

Figure 37. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package

outline

(1)

Figure 38. Recommended footprint

(dimensions in mm)

(1)(2)

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.020 0.050 0.0008 0.0020

A2 0.650 1.000 0.0256 0.0394

A3 0.250 0.0098

b 0.180 0.230 0.300 0.0071 0.0091 0.0118

D 6.850 7.000 7.150 0.2697 0.2756 0.2815

D2 2.250 4.700 5.250 0.0886 0.1850 0.2067

E 6.850 7.000 7.150 0.2697 0.2756 0.2815

E2 2.250 4.700 5.250 0.0886 0.1850 0.2067

e 0.450 0.500 0.550 0.0177 0.0197 0.0217

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

ddd 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

72/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Package characteristics

Seating plane

ddd C

AA2

Pin # 1 ID R = 0.20

ZR_ME

0.30

6.30

0.50

1.00

4.30

4.80

4.10

ai14870b

0.75

Figure 39. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package

outline

(1)

Figure 40. Recommended footprint

(dimensions in mm)

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data

millimeters inches

Symbol

Min Typ Max Min Typ Max

(1)(2)

(1)

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.020 0.050 0.0008 0.0020

A2 0.650 1.000 0.0256 0.0394

A3 0.250 0.0098

b 0.180 0.230 0.300 0.0071 0.0091 0.0118

D 5.875 6.000 6.125 0.2313 0.2362 0.2411

D2 1.750 3.700 4.250 0.0689 0.1457 0.1673

E 5.875 6.000 6.125 0.2313 0.2362 0.2411

E2 1.750 3.700 4.250 0.0689 0.1457 0.1673

e 0.450 0.500 0.550 0.0177 0.0197 0.0217

L 0.350 0.550 0.750 0.0138 0.0217 0.0295

ddd 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 13586 Rev 14 73/87

Package characteristics STM32F101x8, STM32F101xB

100 26

125

E3 E1 E

Pin 1 identification

SEATING PLANE

GAGE PLANE

Cccc

0.25 mm

0.10 inch

1L_ME

75 51

5076

0.5

0.3

16.7 14.3

100 26

12.3

1.2

16.7

ai14906

Figure 41. LQFP100, 14 x 14 mm, 100-pin low-profile

quad flat package outline

(1)

Figure 42. Recommended footprint

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 49. LQPF100 – 14 x14 mm, 100-pin low-profile quad flat package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

(1)(2)

D1 13.80 14.00 14.2 0.5433 0.5512 0.5591

D3 12.00 0.4724

ccc 0.08 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

74/87 Doc ID 13586 Rev 14

A 1.60 0.063

A1 0.05 0.15 0.002 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 0.2 0.0035 0.0079

D 15.80 16.00 16.2 0.622 0.6299 0.6378

E 15.80 16.00 16.2 0.622 0.6299 0.6378

E1 13.80 14.00 14.2 0.5433 0.5512 0.5591

E3 12.00 0.4724

e 0.50 0.0197

L 0.45 0.60 0.75 0.0177 0.0236 0.0295

L1 1.00 0.0394

k 0° 3.5° 7° 0.0° 3.5° 7.0°

STM32F101x8, STM32F101xB Package characteristics

ai14398b

3249

64 17

116

1.2

0.3

10.3

12.7

10.3

0.5

7.8

12.7

ai14909

Figure 43. LQFP64 – 10 x 10 mm, 64 pin low-profile

quad flat package outline

(1)

Figure 44. Recommended

footprint

(1)(2)

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

D1 10.00 0.3937

E1 10.00 0.3937

L1 1.00 0.0394

1. Values in inches are converted from mm and rounded to 4 decimal digits.

A 1.60 0.0630

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 0.20 0.0035 0.0079

D 12.00 0.4724

E 12.00 0.4724

e 0.50 0.0197

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.0177 0.0236 0.0295

Number of pins

N64

Doc ID 13586 Rev 14 75/87

Package characteristics STM32F101x8, STM32F101xB

ccc

A2A

Seating plane

0.25 mm

Gage plane

Pin 1 identification

5B_ME

9.70

5.80

7.30

0.20

7.30

1.20

5.80

9.70

0.30

1.20

0.50

ai14911b

1348

Figure 45. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

package outline

(1)

Figure 46. Recommended

footprint

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 51. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

(1)(2)

A 1.600 0.0630

A1 0.050 0.150 0.0020 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 0.200 0.0035 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 5.500 0.2165

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 5.500 0.2165

e 0.500 0.0197

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 1.000 0.0394

k 0°3.5°7° 0°3.5°7°

ccc 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

76/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Package characteristics

6.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 8: General operating conditions on page 32.

The maximum chip-junction temperature, T

max, in degrees Celsius, may be calculated

using the following equation:

max = TA max + (PD max x ΘJA)

Where:

● T

● Θ

● P

max is the maximum ambient temperature in °C,

is the package junction-to-ambient thermal resistance, in °C/W,

max is the sum of P

max is the product of I

INT

max and P

INT

and VDD, expressed in Watts. This is the maximum chip

max (PD max = P

I/O

INT

max + P

I/O

max),

internal power.

max represents the maximum power dissipation on output pins where:

I/O

max = Σ (VOL × IOL) + Σ((V

I/O

taking into account the actual V

– VOH) × IOH),

/ IOL and VOH / I

of the I/Os at low and high level in the

application.

Table 52. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

LQFP 100 - 14 x 14 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

VFQFPN 48 - 6 x 6 mm / 0.5 mm pitch

°C/W

Thermal resistance junction-ambient

VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch

6.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

Doc ID 13586 Rev 14 77/87

Package characteristics STM32F101x8, STM32F101xB

100

200

300

400

500

600

700

65 75 85 95 105 115

TA (°C)

(mW)

Suffix 6

6.2.2 Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 53: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F101xx junction temperature range.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T I

= 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

level with I mode at low level with I

INTmax =

IOmax =

This gives: P

Dmax =

Thus: P

Dmax

= 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output

= 20 mA, VOL= 1.3 V

50 mA × 3.5 V= 175 mW

20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

= 175 mW and P

INTmax

175 + 272 = 447 mW

= 447 mW

Using the values obtained in Tab le 5 2 T

– For LQFP64, 45 °C/W

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

Jmax

This is within the junction temperature range of the STM32F101xx (–40 < T

= 82 °C (measured according to JESD51-2),

Amax

= 272 mW

IOmax

is calculated as follows:

Jmax

< 105 °C).

Figure 47. LQFP64 P

78/87 Doc ID 13586 Rev 14

max vs. T

STM32F101x8, STM32F101xB Ordering information scheme

7 Ordering information scheme

Table 53. Ordering information scheme

Example: STM32 F 101 C 8 T 6 xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

101 = access line

Pin count

T = 36 pins C = 48 pins R = 64 pins V = 100 pins

Flash memory size

(1)

8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory

Package

T = LQFP U = VFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Options

xxx = programmed parts TR = tape and real

1. Although STM32F101x6 devices are not described in this datasheet, orderable part numbers that do not show the A internal code after temperature range code 6 should be referred to this datasheet for the electrical characteristics. The low-density datasheet only covers STM32F101x6 devices that feature the A code.

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

Doc ID 13586 Rev 14 79/87

Revision history STM32F101x8, STM32F101xB

8 Revision history

Table 54. Document revision history

Date Revision Changes

06-Jun-2007 1 First draft.

values modified in Table 11: Maximum current consumption in Run

and Sleep modes (TA = 85 °C).

range modified in Power supply schemes.

BAT

20-Jul-07 2

min value, t

REF+

characteristics. Table 38: TIMx characteristics modified. Note 6 modified and Note 8, Note 5 and Note 7 added below Ta bl e 4:

Medium-density STM32F101xx pin definitions. Figure 20: Low-speed external clock source AC timing diagram,

Figure 11: Power supply scheme, Figure 28: Recommended NRST pin protection and Figure 29: I2C bus AC waveforms and measurement circuit(1) modified.

Sample size modified and machine model removed in Electrostatic

discharge (ESD).

Number of parts modified and standard reference updated in Static

latch-up. 25 °C and 85 °C conditions removed and class name modified

in Table 32: Electrical sensitivities. t

SU(LSE)

changed to t

characteristics.

In Table 28: Flash memory endurance and data retention, typical endurance added, data retention for T retention for TA = 85 °C added. Note removed below Tab l e 8: G e n e r al

operating conditions.

changed to V

voltage. I

max values added to Table 11: Maximum current

consumption in Run and Sleep modes (TA = 85 °C).

max value added to Table 23: HSI oscillator characteristics.

DD(HSI)

and RPD min and max values added to Table 34: I/O static

characteristics. R characteristics (two notes removed).

Datasheet title corrected. USB characteristics section removed.

Features on page 1 list optimized. Small text changes.

, t

STAB

REFINT

and f

lat

in Table 21: HSE 4-16 MHz oscillator

SU(LSE)

in Table 11: Embedded internal reference

min and max values added to Table 37: NRST pin

added to Table 42: ADC

TRIG

= 25 °C removed and data

80/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Revision history

Table 54. Document revision history (continued)

Date Revision Changes

ESD(CDM)

value added to Table 31: ESD absolute maximum ratings.

Note added below Table 10: Embedded reset and power control block

characteristics. and below Table 21: HSE 4-16 MHz oscillator characteristics.

Note added below Table 35: Output voltage characteristics and V

parameter description modified.

Table 42: ADC characteristics and Table 44: ADC accuracy - limited test conditions modified.

Figure 33: ADC accuracy characteristics modified.

Packages are ECOPACK® compliant. Tables modified in Section 5.3.5: Supply current characteristics. ADC and ANTI_TAMPER signal names modified (see Table 4: Medium-

density STM32F101xx pin definitions). Table 4: Medium-density STM32F101xx pin definitions modified. Note 4 removed and values

updated in Table 21: Typical current consumption in Standby mode.

modified in Table 34: I/O static characteristics.

hys

Updated: Table 29: EMS characteristics and Ta b le 30 : EM I

characteristics.

modified in Table 9: Operating conditions at power-up / power-

VDD

down.

Typical values modified, note 2 modified and note 3 removed in Ta b le 2 5 :

Low-power mode wakeup timings.

18-Oct-2007 3

Maximum current consumption Ta b le 1 2 , Ta bl e 1 3 and Ta b le 1 4 updated. Values added and notes added in Tab l e 1 5 : Typ ic al a n d ma xi mu m

current consumptions in Stop and Standby modes. On-chip peripheral current consumption on page 43 added.

Package mechanical data inch values are calculated from mm and rounded to 4 decimal digits (see Section 6: Package characteristics).

added to Table 27: Flash memory characteristics.

prog

T T

added to Table 46: TS characteristics.

S_temp

added to Table 11: Embedded internal reference voltage.

S_vrefint

Handling of unused pins specified in General input/output characteristics

on page 54. All I/Os are CMOS and TTL compliant. Table 4: Medium-density STM32F101xx pin definitions: table clarified

and Note 7 modified. Internal LSI RC frequency changed from 32 to 40 kHz (see Ta bl e 2 4: LS I

oscillator characteristics). Values added to Table 25: Low-power mode wakeup timings. N

modified in Table 28: Flash memory endurance

END

and data retention.

Option byte addresses corrected in Figure 8: Memory map. ACC t

modified in Table 23: HSI oscillator characteristics.

HSI

removed from Table 26: PLL characteristics.

JITTER

Appendix A: Important notes on page 71 added.

Added: Figure 13, Figure 14, Figure 16 and Figure 18.

Doc ID 13586 Rev 14 81/87

Revision history STM32F101x8, STM32F101xB

Table 54. Document revision history (continued)

Date Revision Changes

Document status promoted from preliminary data to datasheet. Small text changes.

STM32F101CB part number corrected in Table 1: Device summary. Number of communication peripherals corrected for STM32F101Tx in

Table 2: Device features and peripheral counts (STM32F101xx mediumdensity access line) and Number of GPIOs corrected for LQFP package.

Power supply schemes on page 16 modified.

Main function and default alternate function modified for PC14 and PC15 in Table 4: Medium-density STM32F101xx pin definitions, Note 6 added, Remap column added.

Figure 11: Power supply scheme modified. V

and Note 1 modified in Table 5: Voltage characteristics. Note 1 modified in Table 6: Current characteristics.

Note 2 added in Table 10: Embedded reset and power control block characteristics.

48 and 72 MHz frequencies removed from Ta bl e 1 2, Ta b l e 1 3 and

Ta bl e 1 4 . MCU ‘s operating conditions modified in Typical current consumption on page 41.

DD_VBAT

typical value at 2.4 V modified and I

added in Table 15: Typical and maximum current consumptions in Stop

and Standby modes. Note added in Table 16 on page 41 and Ta b l e 1 7 on page 42. Table 18: Peripheral current consumption modified.

22-Nov-2007 4

Figure 17: Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.

Note removed below Figure 30: SPI timing diagram - slave mode and

CPHA = 0. Note added below Figure 31: SPI timing diagram - slave mode and CPHA = 1(1).

Figure 34: Typical connection diagram using the ADC modified.

SU(HSE)

and t

conditions modified in Ta b le 2 1 and Ta bl e 2 2 ,

SU(LSE)

respectively. Maximum values removed from Table 25: Low-power mode

wakeup timings. t

conditions modified in Table 28: Flash memory

RET

endurance and data retention. Conditions modified in Table 29: EMS characteristics.

Impedance size specified in A.4: Voltage glitch on ADC input 0 on

page 71. Small text changes in Table 35: Output voltage characteristics. Section 5.3.11: Absolute maximum ratings (electrical sensitivity)

updated. Details on unused pins removed from General input/output

characteristics on page 54. Table 41: SPI characteristics updated. Notes added and I

Table 42: ADC characteristics. Note added in Ta bl e 4 3 and Tab le 4 6. Note 3 and Note 2 added below Table 44: ADC accuracy - limited test conditions. Avg_Slope and V

value for VFQFPN36 package added in Table 52: Package thermal

modified in Table 46: TS characteristics.

characteristics. I2C interface characteristics on page 60 modified.

Order codes replaced by Section 7: Ordering information scheme.

− VSS ratings modified

DD_VBAT

maximum value

lkg

removed in

82/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB Revision history

Table 54. Document revision history (continued)

Date Revision Changes

Figure 2: Clock tree on page 13 added.

CRC added (see CRC (cyclic redundancy check) calculation unit on

page 9 and Figure 8: Memory map on page 28 for address).

Maximum T

, TA and TJ added, t

in Table 27: Flash memory characteristics on page 50.

modified in Table 15: Typical and maximum current consumptions in

Stop and Standby modes on page 38.

ACC

HSI

note 2 removed.

modified in Table 28: Flash memory endurance and data retention.

RET

14-Mar-2008 5

NF(NRST)

page 59. Table 41: SPI characteristics on page 63 modified.

VREF

Table 44: ADC accuracy - limited test conditions added. Table 45: ADC accuracy modified.

LQFP100 package specifications updated (see Section 6: Package

characteristics on page 71).

Recommended LQFP100, LQFP64, LQFP48 and VFQFPN36 footprints added (see Figure 42, Figure 44, Figure 46 and Figure 40).

Section 6.2: Thermal characteristics on page 77 modified. Appendix A: Important notes removed.

Small text changes. In Table 28: Flash memory endurance and data retention: –N

END

21-Mar-2008 6

– cycling conditions specified for t –t

RET

Figure 2: Clock tree corrected. Figure 8: Memory map clarified.

, Avg_Slope and TL modified in Table 46: TS characteristics.

CRC feature removed.

Section 1: Introduction modified, Section 2.2: Full compatibility throughout the family added. CRC feature added.

DD_VBAT

mode on page 42.

Values added to Table 40: SCL frequency (fPCLK1= 36 MHz, VDD = 3.3

22-May-2008 7

V) on page 62. Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 64

modified. Equation 1 corrected.

Section 6.2.2: Evaluating the maximum junction temperature for an application on page 78 added.

Axx option added to Table 53: Ordering information scheme on page 79.

value given in Table 7: Thermal characteristics on page 32.

values modified and t

prog

description clarified

prog

modified in Table 23: HSI oscillator characteristics on page 48,

unit corrected in Table 37: NRST pin characteristics on

added in Table 42: ADC characteristics on page 66.

tested over the whole temperature range

RET

min modified at TA = 55 °C

removed from Table 21: Typical current consumption in Standby

Doc ID 13586 Rev 14 83/87

Revision history STM32F101x8, STM32F101xB

Table 54. Document revision history (continued)

Date Revision Changes

Small text changes.

added to

DDA

21-Jul-2008 8

Power supply supervisor on page 16 modified and V Table 8: General operating conditions on page 32.

Capacitance modified in Figure 11: Power supply scheme on page 30. Table notes revised in Section 5: Electrical characteristics. Maximum value of t

RSTTEMPO

modified in Table 10: Embedded reset and

power control block characteristics on page 34.

Values added to Table 15: Typical and maximum current consumptions

in Stop and Standby modes and Table 21: Typical current consumption in Standby mode removed.

characteristics on page 44. f

modified in Table 19: High-speed external user clock

HSE_ext

modified in Table 26: PLL

PLL_IN

characteristics on page 49.

corrected in Table 29: EMS characteristics.

HCLK

Minimum SDA and SCL fall time value for Fast mode removed from

Table 39: I2C characteristics on page 61, note 1 modified.

modified in Table 41: SPI characteristics on page 63 and

h(NSS)

Figure 30: SPI timing diagram - slave mode and CPHA = 0 on page 64.

modified in Table 42: ADC characteristics on page 66 and

ADC

Figure 34: Typical connection diagram using the ADC modified.

corrected in Table 44: ADC accuracy - limited test conditions and

PCLK2

Table 45: ADC accuracy.

Typical T

value removed from Table 46: TS characteristics on

S_temp

page 70.

LQFP48 package specifications updated (see Ta b le 5 1 , Tab l e 4 5 and

Ta bl e 4 6 ).

Axx option removed from Table 53: Ordering information scheme on

page 79.

24-Jul-2008 9

First page modified: “Up to 2 x I²C interfaces” instead of “1 x I²C interface”

STM32F101xx devices with 32 Kbyte Flash memory capacity removed, document updated accordingly.

Section 2.2: Full compatibility throughout the family on page 14 updated.

Notes modified in Table 4: Medium-density STM32F101xx pin definitions

on page 24. Note 2 modified below Table 5: Voltage characteristics on page 31,

| min and |ΔV

|ΔV

DDx

23-Sep-2008 10

Note 2 added to Table 8: General operating conditions on page 32.

Measurement conditions specified in Section 5.3.5: Supply current

characteristics on page 35.

in standby mode at 85 °C modified in Tab l e 15 : Ty p ic a l a nd ma xi mu m

current consumptions in Stop and Standby modes on page 38. General input/output characteristics on page 54 modified.

Note added below Table 53: Ordering information scheme.

Section 7.1: Future family enhancements removed. Small text changes.

84/87 Doc ID 13586 Rev 14

| min removed.

DDx

STM32F101x8, STM32F101xB Revision history

Table 54. Document revision history (continued)

Date Revision Changes

I/O information clarified on page 1. Figure 8: Memory map modified. In Table 4: Medium-density STM32F101xx pin definitions: PB4, PB13,

PB14, PB15, PB3/TRACESWO moved from Default column to Remap column.

Note modified in Table 12: Maximum current consumption in Run mode,

21-Apr-2009 11

22-Sep-2009 12

code with data processing running from Flash and Table 14: Maximum current consumption in Sleep mode, code running from Flash or RAM.

Figure 16, Figure 17 and Figure 18 show typical curves. Table 19: High-speed external user clock characteristics and Ta bl e 2 0: Low-speed external user clock characteristics modified.

ACC

max values modified in Table 23: HSI oscillator characteristics.

HSI

Small text changes.

Note 5 updated and Note 4 added in Table 4: Medium-density STM32F101xx pin definitions.

voltage. Typical I

RERINT

and T

added to Table 11: Embedded internal reference

Coeff

DD_VBAT

value added in Table 15: Typical and maximum

current consumptions in Stop and Standby modes. Figure 15: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added.

min modified in Table 19: High-speed external user clock

HSE_ext

characteristics.

and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator

characteristics and Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables. Table 23: HSI oscillator characteristics modified. Conditions removed

from Table 25: Low-power mode wakeup timings.

Figure 28: Recommended NRST pin protection modified. Note 1 modified below Figure 21: Typical application with an 8 MHz

crystal. Figure 28: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 50.

Jitter added to Table 26: PLL characteristics. C modified in Table 42: ADC characteristics. R

AIN

and R

ADC

max values modified in

parameters

AIN

Table 43: RAIN max for fADC = 14 MHz.

Small text changes.

Doc ID 13586 Rev 14 85/87

Revision history STM32F101x8, STM32F101xB

Table 54. Document revision history (continued)

Date Revision Changes

Added STM32F101TB devices. Added VFQFPN48 package.

20-May-2010 13

19-Apr-2011 14

Updated note 2 below Table 39: I2C characteristics Updated Figure 29: I2C bus AC waveforms and measurement circuit(1) Updated Figure 28: Recommended NRST pin protection Updated Section 5.3.12: I/O current injection characteristics

Updated footnotes below Table 5: Voltage characteristics on page 31 and Table 6: Current characteristics on page 32

Updated tw min in Table 19: High-speed external user clock

characteristics on page 44

Updated startup time in Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz) on page 47

Added Section 5.3.12: I/O current injection characteristics Updated Section 5.3.13: I/O port characteristics

86/87 Doc ID 13586 Rev 14

STM32F101x8, STM32F101xB

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

Doc ID 13586 Rev 14 87/87

ST STM32F101C8, STM32F101R8, STM32F101V8, STM32F101T8, STM32F101RB User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Introduction

2 Description

2.1 Device overview

Figure 1. STM32F101xx medium-density access line block diagram

Figure 2. Clock tree

2.2 Full compatibility throughout the family

Table 3. STM32F101xx family

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

2.3.2 Embedded Flash memory

2.3.3 CRC (cyclic redundancy check) calculation unit

2.3.4 Embedded SRAM

2.3.5 Nested vectored interrupt controller (NVIC)

2.3.6 External interrupt/event controller (EXTI)

2.3.7 Clocks and startup

2.3.8 Boot modes

2.3.9 Power supply schemes

2.3.10 Power supply supervisor

2.3.11 Voltage regulator

2.3.12 Low-power modes

2.3.13 DMA

2.3.14 RTC (real-time clock) and backup registers

2.3.15 Independent watchdog

2.3.16 Window watchdog

2.3.17 SysTick timer

2.3.18 General-purpose timers (TIMx)

2.3.19 I²C bus

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)

2.3.21 Serial peripheral interface (SPI)

2.3.22 GPIOs (general-purpose inputs/outputs)

2.3.23 ADC (analog to digital converter)

2.3.24 Temperature sensor

2.3.25 Serial wire JTAG debug port (SWJ-DP)

3 Pinouts and pin description

Figure 3. STM32F101xx medium-density access line LQFP100 pinout

Figure 4. STM32F101xx medium-density access line LQFP64 pinout

Figure 5. STM32F101xx medium-density access line LQFP48 pinout

Figure 6. STM32F101xx medium-density access line VFQPFN48 pinout

Figure 7. STM32F101xx medium-density access line VFQPFN36 pinout

4 Memory mapping

Figure 8. Memory map

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

Figure 9. Pin loading conditions Figure 10. Pin input voltage

5.1.6 Power supply scheme

Figure 11. Power supply scheme

5.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

5.2 Absolute maximum ratings

Table 5. Voltage characteristics

Table 6. Current characteristics

Table 7. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

5.3.2 Operating conditions at power-up / power-down

Table 9. Operating conditions at power-up / power-down

5.3.3 Embedded reset and power control block characteristics

Table 10. Embedded reset and power control block characteristics

5.3.4 Embedded reference voltage

Table 11. Embedded internal reference voltage

5.3.5 Supply current characteristics

Table 15. Typical and maximum current consumptions in Stop and Standby modes

Table 18. Peripheral current consumption

5.3.6 External clock source characteristics

Table 19. High-speed external user clock characteristics

Table 20. Low-speed external user clock characteristics

Figure 19. High-speed external clock source AC timing diagram

Figure 20. Low-speed external clock source AC timing diagram

Table 21. HSE 4-16 MHz oscillator characteristics

Figure 21. Typical application with an 8 MHz crystal