ST STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 User Manual

Low-density access line, ARM-based 32-bit MCU with

LQFP48

7 x 7 mm

LQFP64

10 x 10 mm

VFQFPN36

6 × 6 mm

VFQFPN48

7 × 7 mm

16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3

– 36 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access

– Single-cycle multiplication and hardware

division

■ Memories

– 16 to 32 Kbytes of Flash memory
– 4 to 6 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage

detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes
–V

■ Debug mode

– Serial wire debug (SWD) and JTAG

■ DMA

– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,

■ 1 × 12-bit, 1 µs A/D converter (up to 16

channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor

■ Up to 51 fast I/O ports

– 26/37/51 I/Os, all mappable on 16 external

supply for RTC and backup registers

BAT

interfaces

2

I

Cs and USARTs

interrupt vectors and almost all 5 V-tolerant

CPU

STM32F101x4
STM32F101x6

■ Up to 5 timers

– Up to two16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 2 watchdog timers (Independent and

Window)

– SysTick timer: 24-bit downcounter

■ Up to 4 communication interfaces

– 1 x I
– Up to 2 USARTs (ISO 7816 interface, LIN,

– 1 × SPI (18 Mbit/s)

■ CRC calculation unit, 96-bit unique ID

■ ECOPACK

Table 1. Device summary

STM32F101x4

STM32F101x6

2

C interface (SMBus/PMBus)

IrDA capability, modem control)

®

packages

Reference Part number

STM32F101C4,
STM32F101R4,
STM32F101T4

STM32F101C6,
STM32F101R6,
STM32F101T6

April 2011 Doc ID 15058 Rev 5 1/79

www.st.com

1

Contents STM32F101x4, STM32F101x6

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15

2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15

2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 15

2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18

2.3.15 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.16 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.17 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.18 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.19 I

²

C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . 19

2.3.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.23 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Contents

4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 31

5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 31

5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 50

5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.2.2 Evaluating the maximum junction temperature for an application . . . . . 75

Doc ID 15058 Rev 5 3/79

Contents STM32F101x4, STM32F101x6

7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Low-density STM32F101xx device features and peripheral counts . . . . . . . . . . . . . . . . . . 11

Table 3. STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Low-density STM32F101xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 5. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 7. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. Maximum current consumption in Run mode, code with data processing

running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Maximum current consumption in Sleep mode, code running from Flash

or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 15. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 36

Table 16. Typical current consumption in Run mode, code with data processing

running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 17. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 40

Table 18. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 19. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 20. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 22. LSE oscillator characteristics (f

Table 23. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 24. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 26. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 27. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 28. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 30. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 31. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 32. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 33. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 39. I
Table 40. SCL frequency (f

Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2

C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

= MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PCLK1

Table 42. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 43. R

max for f

AIN

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

ADC

Table 44. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

LSE

Doc ID 15058 Rev 5 5/79

List of tables STM32F101x4, STM32F101x6

Table 45. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 46. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 70

Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 71

Table 49. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 72

Table 50. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 73

Table 51. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 52. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 List of figures

List of figures

Figure 1. STM32F101xx Low-density access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3. STM32F101xx Low-density access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. STM32F101xx Low-density access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5. STM32F101xx Low-density access line VFQPFN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6. STM32F101xx Low-density access line VFQPFN36 pinout . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 7. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 35

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 35

Figure 14. Typical current consumption on V

V

values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

BAT

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V

= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DD

Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V

= 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DD

Figure 17. Typical current consumption in Standby mode versus temperature at V

3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 27. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 28. I

2

C bus AC waveforms and measurement circuit

Figure 29. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 30. SPI timing diagram - slave mode and CPHA = 1
Figure 31. SPI timing diagram - master mode

Figure 32. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 33. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 34. Power supply and reference decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 35. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline
Figure 36. Recommended footprint (dimensions in mm)
Figure 37. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline
Figure 38. Recommended footprint (dimensions in mm)

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 72

Figure 40. Recommended footprint

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 41. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

with RTC on versus temperature at different

BAT

= 3.3 V and

DD

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

(1)

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Doc ID 15058 Rev 5 7/79

List of figures STM32F101x4, STM32F101x6

Figure 42. Recommended footprint
Figure 43. LQFP64 P

max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

D

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

8/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Introduction

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of
the STM32F101x4 and STM32F101x6 low-density access line microcontrollers. For more
details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2:

Full compatibility throughout the family.

The Low-density STM32F101xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.

For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.

Doc ID 15058 Rev 5 9/79

Description STM32F101x4, STM32F101x6

2 Description

The STM32F101x4 and STM32F101x6 Low-density access line family incorporates the
high-performance ARM Cortex™-M3 32-bit RISC core operating at a 36 MHz frequency,
high-speed embedded memories (Flash memory of 16 to 32 Kbytes and SRAM of 4 to 6
Kbytes), and an extensive range of enhanced peripherals and I/Os connected to two APB
buses. All devices offer standard communication interfaces (one I
USARTs), one 12-bit ADC and up to two general-purpose 16-bit timers.

The STM32F101xx Low-density access line family operates in the –40 to +85 °C
temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
mode allows the design of low-power applications.

The STM32F101xx Low-density access line family includes devices in three different
packages ranging from 36 pins to 64 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.

These features make the STM32F101xx Low-density access line microcontroller family
suitable for a wide range of applications such as application control and user interface,
medical and handheld equipment, PC peripherals, gaming and GPS platforms, industrial
applications, PLCs, inverters, printers, scanners, alarm systems, Video intercoms, and
HVACs.

2

C, one SPI, and two

10/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Description

2.1 Device overview

Figure 1 shows the general block diagram of the device family.

Table 2. Low-density STM32F101xx device features and peripheral counts

Peripheral

Flash - Kbytes 16 32 16 32 16 32

SRAM - Kbytes 464646

General-purpose 222222

Timers

SPI 111111

2

I

C 111111

USART 222222

Communication

12-bit synchronized ADC

number of channels

STM32F101Tx STM32F101Cx STM32F101Rx

1

10 channels

1

10 channels

1

16 channels

GPIOs 26 37 51

CPU frequency 36 MHz

Operating voltage 2.0 to 3.6 V

Operating temperatures

Packages VFQFPN36

Ambient temperature: –40 to +85 °C (see Ta b l e 8 )
Junction temperature: –40 to +105 °C (see Ta bl e 8 )

LQFP48,

VFQFPN48

LQFP64

Doc ID 15058 Rev 5 11/79

Description STM32F101x4, STM32F101x6

Temp sensor

PA[15: 0]

EXTI

W W D G

NVIC

12bit ADC

SWD

16AF

JTDI

JTCK/ SWCLK

JTMS/SWDIO

NJTRST

JTDO

NRST

V

DD

= 2 to 3.6 V

80AF

PB[15: 0]

PC[15:0 ]

AHB2

SRAM

WAKEUP

GPIOA

GPIOB

GPIOC

F

max

: 3 6 MHz

V

SS

GP DMA

TIM2

TIM3

XTAL OSC

4-16 MHz

XTAL 32 kHz

OSC_IN
OSC_OUT

OSC32_OUT

OSC32_IN

PLL &

APB1 : F

max

=24 / 36 MHz

PCLK1

HCLK

CLOCK
MANAG T

PCLK 2

VOLT. REG.

3.3V TO 1.8V

POWER

Backu p i nterf ace

as AF

6 KB

RTC

RC 8 MHz

Cortex M3 CPU

USART1

USART2

7 channels

Back up

reg

SCL,SDA ,SMBA

I2C

as AF

PD[3:0]

GPIOD

AHB: F

max

=36 MHz

4 Chann els

4 Chann els

FCLK

RC 42 kHz

Stand by

IWDG

@VDD

@VBAT

POR / PDR

SUPPLY

@VDDA

VDDA

VSSA

@VDDA

V

BAT

RX,TX, CTS, RTS,
Smartcard as AF

RX,TX, CTS, RTS,

APB2 : F

max

= 36 MHz

NVIC

SPI

MOSI,MISO,

SCK,NSS as AF

IF

int erface

@VDDA

SUPERVISION

PVD

Rst

Int

@VDD

AHB2

APB2

APB1

AWU

TAMPER-RTC

Flash 32 KB

BusM atrix

64 bit

Interface

Ibus

Dbus

pbus

obl

Flash

Trace

controller

System

ai15173c

TRACECLK
TRACED[0:3]

as AS

SW/JTAG

TPIU

Trace/trig

CK, SmartCard as AF

Figure 1. STM32F101xx Low-density access line block diagram

1. AF = alternate function on I/O port pin.

= –40 °C to +85 °C (junction temperature up to 105 °C).

2. T

A

12/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Description

HSE OSC

4-16 MHz

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

HSI RC

8 MHz

LSI RC
40 kHz

to Independent Watchdog (IWDG)

PLL

x2, x3, x4

PLLMUL

Legend:

MCO

Clock Output

Main

PLLXTPRE

/2

..., x16

AHB
Prescaler
/1, 2..512

/2

PLLCLK

HSI

HSE

APB1

Prescaler

/1, 2, 4, 8, 16

ADC
Prescaler
/2, 4, 6, 8

ADCCLK

PCLK1

HCLK

PLLCLK

to AHB bus, core,
memory and DMA

to TIM2, TIM3

to ADC

LSE

LSI

HSI

/128

/2

HSI

HSE

peripherals

to APB1

Peripheral Clock

Enable (13 bits)

Enable (3 bits)

P

eripheral Clock

APB2

Prescaler

/1, 2, 4, 8, 16

PCLK2

peripherals

to APB2

Peripheral Clock

Enable (11 bits)

36 MHz max

36 MHz max

to RTC

PLLSRC

SW

MCO

CSS

to Cortex System timer

/8

Clock

Enable (3 bits)

SYSCLK

RTCCLK

RTCSEL[1:0]

TIMXCLK

IWDGCLK

SYSCLK

FCLK Cortex
free running clock

TIM2, TIM3
If (APB1 prescaler =1) x1
else x2

HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal

ai15174

36 MHz max

36 MHz
max

Figure 2. Clock tree

1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
36 MHz.

2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz.

Doc ID 15058 Rev 5 13/79

Description STM32F101x4, STM32F101x6

2.2 Full compatibility throughout the family

The STM32F101xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are
referred to as low-density devices, the STM32F101x8 and STM32F101xB are referred to as
medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are
referred to as high-density devices.

Low- and high-density devices are an extension of the STM32F101x8/B devices, they are
specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low­density devices feature lower Flash memory and RAM capacities and a timer less. High­density devices have higher Flash memory and RAM capacities, and additional peripherals
like FSMC and DAC, while remaining fully compatible with the other members of the
STM32F101xx family.
The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE
are a drop-in replacement for the STM32F101x8/B medium-density devices, allowing the
user to try different memory densities and providing a greater degree of freedom during the
development cycle.

Moreover, the STM32F101xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.

Table 3. STM32F101xx family

Memory size

Low-density devices Medium-density devices High-density devices

Pinout

16 KB

Flash

4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM

144

100

64

2 × USARTs
2 × 16-bit timers

48

1 × SPI, 1 × I2C
1 × ADC

36

1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices.

32 KB

Flash

(1)

64 KB

Flash

3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs,
1 × ADC

128 KB

Flash

256 KB

Flash

32 KB

RAM

384 KB

Flash

48 KB

RAM

512 KB

Flash

48 KB

RAM

5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I

2

Cs, 1 × ADC,

2 × DACs, FSMC (100 and 144 pins)

14/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Description

2.3 Overview

2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.

The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.

The STM32F101xx Low-density access line family having an embedded ARM core, is
therefore compatible with all ARM tools and software.

2.3.2 Embedded Flash memory

16 or 32 Kbytes of embedded Flash is available for storing programs and data.

2.3.3 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link­time and stored at a given memory location.

2.3.4 Embedded SRAM

Up to 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.

2.3.5 Nested vectored interrupt controller (NVIC)

The STM32F101xx Low-density access line embeds a nested vectored interrupt controller
able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt
latency.

Doc ID 15058 Rev 5 15/79

Description STM32F101x4, STM32F101x6

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from User Flash

● Boot from System Memory

● Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

● V

● V

● V

For more details on how to connect power pins, refer to Figure 10: Power supply scheme.

= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.

DD

Provided externally through V

, V

SSA

= 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs

DDA

and PLL (minimum voltage to be applied to V
V

and V

DDA

BAT

SSA

= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

2.3.10 Power supply supervisor

The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.

pins.

DD

must be connected to V

is below a specified threshold, V

DD

DD

DD

is 2.4 V when the ADC is used).

DDA

and VSS, respectively.

is not present.

POR/PDR

, without the need for an

The device features an embedded programmable voltage detector (PVD) that monitors the
V

DD/VDDA

generated when V

16/79 Doc ID 15058 Rev 5

power supply and compares it to the V

DD/VDDA

drops below the V

PVD

threshold. An interrupt can be

PVD

threshold and/or when VDD/V

DDA

is higher

STM32F101x4, STM32F101x6 Description

than the V

threshold. The interrupt service routine can then generate a warning

PVD

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 10: Embedded reset and power control block characteristics for the values of
V

POR/PDR

and V

PVD

.

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop mode

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.

2.3.12 Low-power modes

The STM32F101xx Low-density access line supports three low-power modes to achieve the
best compromise between low power consumption, short startup time and available wakeup
sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.

Doc ID 15058 Rev 5 17/79

Description STM32F101x4, STM32F101x6

Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

2

C, USART, general purpose timers

TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on
V

supply when present or through the V

DD

registers used to store 20 bytes of user application data when V

The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.

pin. The backup registers are ten 16-bit

BAT

power is not present.

DD

2.3.15 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.

2.3.16 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

2.3.17 SysTick timer

This timer is dedicated for OS, but could also be used as a standard down counter. It
features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.18 General-purpose timers (TIMx)

There areup to two synchronizable general-purpose timers embedded in the STM32F101xx
Low-density access line devices. These timers are based on a 16-bit auto-reload up/down
counter, a 16-bit prescaler and feature 4 independent channels each for input capture,

18/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Description

output compare, PWM or one pulse mode output. This gives up to 12 input captures / output
compares / PWMs on the largest packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs. They all have independent DMA request
generation.

These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.

2.3.19 I²C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.

2.3.20 Universal synchronous/asynchronous receiver transmitter (USART)

The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.

The USART interfaces can be served by the DMA controller.

2.3.21 Serial peripheral interface (SPI)

The SPI interface is able to communicate up to 18 Mbit/s in slave and master modes in full­duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.

The SPI interface can be served by the DMA controller.

2.3.22 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current­capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.

2.3.23 ADC (analog to digital converter)

The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.

The ADC can be served by the DMA controller.

Doc ID 15058 Rev 5 19/79

Description STM32F101x4, STM32F101x6

An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.

2.3.24 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V

< 3.6 V. The temperature sensor is internally

DDA

connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.

2.3.25 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

20/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Pinouts and pin description

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0 OSC_IN

PD1 OSC_OUT

NRST

PC0
PC1
PC2
PC3

VSSA

VDDA

PA 0- W K UP

PA 1
PA 2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PD2

PC12

PC11

PC10

PA 1 5

PA 14

VDD_2
VSS_2
PA 1 3
PA 1 2
PA 1 1
PA 1 0
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12

PA 3

VSS_4

VDD_4

PA 4

PA 5

PA 6

PA 7

PC4

PC5

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

LQFP64

ai14387b

PC13-TAMPER-RTC

44 43 42 41 40 39 38 37

36

35
34

33
32
31
30
29
28
27
26
25

24

23

12

13 14 15 16 17 18

19 20 21 22

1
2
3
4
5
6
7
8
9
10
11

48 47 46 45

LQFP48

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

VDD_2
VSS_2
PA1 3
PA1 2
PA1 1
PA1 0
PA9
PA8
PB15
PB14
PB13
PB12

VBAT

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST
VSSA
VDDA

PA 0- W K UP

PA 1
PA 2

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA 1 5

PA 14

ai14378d

PC13-TAMPER-RTC

3 Pinouts and pin description

Figure 3. STM32F101xx Low-density access line LQFP64 pinout

Figure 4. STM32F101xx Low-density access line LQFP48 pinout

Doc ID 15058 Rev 5 21/79

Pinouts and pin description STM32F101x4, STM32F101x6

ai18300

VDD_3

VSS_3

PB9

PB8

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

PB10

PB11

VSS_1

VDD_1

VBAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1-OSC_OUT

NRST
VSSA
VDDA

PA0-WKUP

PA 1
PA 2

VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA 9
PA 8
PB15
PB14
PB13
PB12

48

VFQFPN48

47 46

45 444342 41

40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

13

14 15

16 171819 20

21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

V

SS_3

BOOT0

PB7

PB6

PB5

PB4

PB3

PA15

PA14

36 35 34 33 32 31 30 29 28

V

DD_3

1

27

V

DD_2

OSC_IN/PD0

2

26

V

SS_2

OSC_OUT/PD1

3

25

PA13

NRST

4

QFN36

24

PA12

V

SSA

5

23 PA11

V

DDA

6

22

PA10

PA0-WKUP

7

21

PA 9

PA 1

8

20

PA 8

PA 2 9

19

V

DD_1

10 11 12 13 14 15 16 17 18

PA 3

PA 4

PA 5

PA 6

PA 7

PB0

PB1

PB2

V

SS_1

ai14654

Figure 5. STM32F101xx Low-density access line VFQPFN48 pinout

Figure 6. STM32F101xx Low-density access line VFQPFN36 pinout

22/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions

Pins

Pin name

(1)

Type

LQFP64

LQFP48/

VFQFPN48

11- V

2 2 - PC13-TAMPER-RTC

3 3 - PC14-OSC32_IN

4 4 - PC15-OSC32_OUT

VFQFPN36

BAT

SV

(5)

I/O PC13

(5)

I/O PC14

(5)

I/O PC15

5 5 2 OSC_IN I OSC_IN

6 6 3 OSC_OUT O OSC_OUT

7 7 4 NRST I/O NRST

- 8 - PC0 I/O PC0 ADC_IN10

- 9 - PC1 I/O PC1 ADC_IN11

- 10 - PC2 I/O PC2 ADC_IN12

- 11 - PC3 I/O PC3 ADC_IN13

8125 V

9136 V

SSA

DDA

SV

SV

10 14 7 PA0-WKUP I/O PA0

11 15 8 PA1 I/O PA1

12 16 9 PA2 I/O PA2

13 17 10 PA3 I/O PA3

-18- V

-19- V

SS_4

DD_4

SV

SV

14 20 11 PA4 I/O PA4

15 21 12 PA5 I/O PA5 SPI_SCK

16 22 13 PA6 I/O PA6

17 23 14 PA7 I/O PA7

- 24 PC4 I/O PC4 ADC_IN14

- 25 PC5 I/O PC5 ADC_IN15

18 26 15 PB0 I/O PB0 ADC_IN8/TIM3_CH3

19 27 16 PB1 I/O PB1 ADC_IN9/TIM3_CH4

(2)

I / O level

Main

function

(3)

(after reset)

BAT

(6)

(6)

(6)

SSA

DDA

SS_4

DD_4

Alternate functions

Default Remap

TAMPER-RTC

OSC32_IN

OSC32_OUT

WKUP/USART2_CTS/

ADC_IN0/

TIM2_CH1_ETR

(7)

USART2_RTS/

ADC_IN1/TIM2_CH2

USART2_TX/

ADC_IN2/TIM2_CH3

USART2_RX/

ADC_IN3/TIM2_CH4

(7)

SPI_NSS

/ADC_IN4

USART2_CK

(7)

/ADC_IN5

SPI_MISO

SPI_MOSI

(7)

/ADC_IN6/

TIM3_CH1

(7)

/ADC_IN7/

TIM3_CH2

(7)

(7)

(7)

(7)

(7)

(7)

(7)

(3)(4)

Doc ID 15058 Rev 5 23/79

Pinouts and pin description STM32F101x4, STM32F101x6

Table 4. Low-density STM32F101xx pin definitions (continued)

Pins

LQFP64

LQFP48/

VFQFPN48

Pin name

VFQFPN36

(1)

(2)

Typ e

Main

function

(3)

(after reset)

I / O level

Alternate functions

Default Remap

20 28 17 PB2 I/O FT PB2/BOOT1

21 29 - PB10 I/O FT PB10 TIM2_CH3

22 30 - PB11 I/O FT PB11 TIM2_CH4

23 31 18 V

24 32 19 V

SS_1

DD_1

SV

SV

SS_1

DD_1

25 33 - PB12 I/O FT PB12

26 34 - PB13 I/O FT PB13

27 35 - PB14 I/O FT PB14

28 36 - PB15 I/O FT PB15

- 37 - PC6 I/O FT PC6 TIM3_CH1

38 - PC7 I/O FT PC7 TIM3_CH2

39 - PC8 I/O FT PC8 TIM3_CH3

- 40 - PC9 I/O FT PC9 TIM3_CH4

29 41 20 PA8 I/O FT PA8 USART1_CK/MCO

30 42 21 PA9 I/O FT PA9 USART1_TX

31 43 22 PA10 I/O FT PA10 USART1_RX

(7)

(7)

32 44 23 PA11 I/O FT PA11 USART1_CTS

33 45 24 PA12 I/O FT PA12 USART1_RTS

34 46 25 PA13 I/O FT JTMS-SWDIO PA13

35 47 26 V

36 48 27 V

SS_2

DD_2

SV

SV

SS_2

DD_2

37 49 28 PA14 I/O FT JTCK/SWCLK PA14

38 50 29 PA15 I/O FT JTDI

-51 PC10 I/OFT PC10

-52 PC11 I/OFT PC11

-53 PC12 I/OFT PC12

552 PD0 I/OFTOSC_IN

6 6 3 PD1 I/O FT OSC_OUT

54 - PD2 I/O FT PD2 TIM3_ETR

(8)

(8)

39 55 30 PB3 I/O FT JTDO

(3)(4)

TIM2_CH1_ETR/

PA15 / SPI_NSS

TIM2_CH2 / PB3

TRACESWO

SPI_SCK

24/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Pinouts and pin description

Table 4. Low-density STM32F101xx pin definitions (continued)

Pins

LQFP64

LQFP48/

VFQFPN48

Pin name

VFQFPN36

(1)

(2)

Typ e

Main

function

(3)

(after reset)

I / O level

Alternate functions

Default Remap

40 56 31 PB4 I/O FT NJTRST

41 57 32 PB5 I/O PB5 I2C_SMBA

42 58 33 PB6 I/O FT PB6 I2C_SCL

43 59 34 PB7 I/O FT PB7 I2C_SDA

(7)

(7)

44 60 35 BOOT0 I BOOT0

45 61 - PB8 I/O FT PB8 I2C_SCL

46 62 - PB9 I/O FT PB9 I2C_SDA

47 63 36 V

48 64 1 V

SS_3

DD_3

1. I = input, O = output, S = supply.

2. FT= 5 V tolerant.

3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 11.

4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.

7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.

8. The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.

SV

SV

SS_3

DD_3

(3)(4)

TIM3_CH1 / PB4

SPI_MISO

TIM3_CH2 /

SPI_MOSI

USART1_TX

USART1_RX

Doc ID 15058 Rev 5 25/79

Memory mapping STM32F101x4, STM32F101x6

APB memory space

DMA

RTC

WWDG

IWDG

USART2

ADC

USART1

SPI

EXTI

RCC

0

1

2

3

4

5

6

7

Peripherals

SRAM

reserved

reserved

Option Bytes

Reserved

0x4000 0000

0x4000 0400

0x4000 0800

0x4000 2800

0x4000 2C00

0x4000 3000

0x4000 3400

0x4000 4400

0x4000 4800

0x4000 5400

0x4000 5800

0x4000 6000

0x4000 6400

0x4000 6800

0x4000 6C00

0x4000 7000

0x4000 7400

0x4001 0000

0x4001 0400

0x4001 0800

0x4001 0C00

0x4001 1000

0x4001 1400

0x4001 1800

0x4001 2400

0x4001 2800

0x4001 2C00

0x4001 3000

0x4001 3400

0x4001 3800

0x4001 3C00

0x4002 0000

0x4002 0400

0x4002 1000

0x4002 1400

0x4002 2000

0x4002 2400

0x4002 3000

0x4002 3400

0x6000 0000

0xE010 0000

0xFFFF FFFF

reserved

reserved

reserved

CRC

reserved

reserved

Flash interface

reserved

reserved

reserved

reserved

reserved

reserved

reserved

Port D

Port C

Port B

Port A

AFIO

PWR

BKP

reserved

reserved

reserved

reserved

I2C

reserved

reserved

reserved

TIM3

TIM2

0xFFFF FFFF

0xE010 0000

0xE000 0000

0xC000 0000

0xA000 0000

0x8000 0000

0x6000 0000

0x4000 0000

0x2000 0000

0x0000 0000

0x1FFF FFFF

0x1FFF F80F

0x1FFF F800

0x1FFF F000

0x0801 FFFF

0x0800 0000

System memory

Flash memory

Cortex-M3 internal

peripherals

ai15175b

0x0000 0000

Aliased to Flash or
system memory
depending on
BOOT pins

4 Memory mapping

The memory map is shown in Figure 7.

Figure 7. Memory map

26/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

5 Electrical characteristics

5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

5.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).

5.1.2 Typical values

= 25 °C and TA = TAmax (given by

A

Unless otherwise specified, typical data are based on TA = 25 °C, V
2V≤ V

≤ 3.6 V voltage range). They are given only as design guidelines and are not

DD

tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated

5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 8.

5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 9.

(mean±2Σ).

= 3.3 V (for the

DD

Doc ID 15058 Rev 5 27/79

Electrical characteristics STM32F101x4, STM32F101x6

ai15496

V

DD

1/2/3/4/5

Analo g:

RCs, PLL,

...

Power switch

V

BAT

GP I/O s

OUT

IN

Kernel logic

(CPU,
Digital

& Memories)

Backup circuitry

(OSC32K,RTC,

Backup registers)

Wakeup logic

5 × 100 nF
+ 1 × 4.7 µF

1.8-3.6V

Regulator

V

SS

1/2/3/4/5

V

DDA

V

SSA

ADC

Level shifter

IO

Logic

V

DD

10 nF

+ 1 µF

V

DD

V

REF+

V

REF-

Figure 8. Pin loading conditions Figure 9. Pin input voltage

STM32F10xxx pin

C = 50 pF

5.1.6 Power supply scheme

Figure 10. Power supply scheme

ai14123b

STM32F10xxx pin

V

IN

ai14124b

Caution: In Figure 10, the 4.7 µF capacitor must be connected to V

28/79 Doc ID 15058 Rev 5

DD3

.

STM32F101x4, STM32F101x6 Electrical characteristics

ai14126

V

BAT

V

DD

V

DDA

IDD_V

BAT

I

DD

5.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,

Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent

damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

Table 5. Voltage characteristics

Symbol Ratings Min Max Unit

VDD − V

(2)

V

IN

|ΔV

DDx

|V

− VSS|

SSX

V

ESD(HBM)

1. All main power (VDD, V
supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum
allowed injected current values.

External main supply voltage (including

SS

V

and VDD)

DDA

(1)

Input voltage on five volt tolerant pin V

Input voltage on any other pin V

| Variations between different V

power pins 50

DD

Variations between all the different ground
pins

Electrostatic discharge voltage (human body
model)

) and ground (VSS, V

DDA

) pins must always be connected to the external power

SSA

–0.3 4.0

− 0.3 V

SS

− 0.3 4.0

SS

DD

+ 4.0

50

see Section 5.3.11: Absolute

maximum ratings (electrical

sensitivity)

V

mV

Doc ID 15058 Rev 5 29/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 6. Current characteristics

Symbol Ratings Max. Unit

(1)

(1)

(5)

is the absolute sum of the

INJ(PIN)

150

150

-5/+0

± 5

± 25

INJ(PIN)

INJ(PIN)

mA

must

must

I

VDD

I

VSS

Total current into VDD/V

Total current out of V

SS

power lines (source)

DDA

ground lines (sink)

Output current sunk by any I/O and control pin 25

I

IO

I

INJ(PIN)

ΣI

INJ(PIN)

1. All main power (VDD, V
supply, in the permitted range.

2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC

characteristics.

3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.

4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. I
never be exceeded. Refer to Table 5: Voltage characteristics for the maximum allowed input voltage
values.

5. When several inputs are submitted to a current injection, the maximum ΣI
positive and negative injected currents (instantaneous values).

Output current source by any I/Os and control pin − 25

Injected current on five volt tolerant pins

(2)

Injected current on any other pin

(4)

(3)

Total injected current (sum of all I/O and control pins)

) and ground (VSS, V

DDA

) pins must always be connected to the external power

SSA

Table 7. Thermal characteristics

Symbol Ratings Value Unit

T

STG

T

J

Storage temperature range –65 to +150 °C

Maximum junction temperature 150 °C

5.3 Operating conditions

5.3.1 General operating conditions

Table 8. General operating conditions

Symbol Parameter Conditions Min Max Unit

f

HCLK

PCLK1

f

PCLK2

V

DD

V

DDA

V

BAT

Internal AHB clock frequency 0 36

Internal APB1 clock frequency 0 36

Internal APB2 clock frequency 0 36

Standard operating voltage 2 3.6 V

Analog operating voltage
(ADC not used)

(1)

Analog operating voltage
(ADC used)

Backup operating voltage 1.8 3.6 V

Must be the same potential

(2)

as V

DD

MHzf

23.6

V

2.4 3.6

30/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

Table 8. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

LQFP64 444

P

D

Power dissipation at T

(3)

85 °C

=

A

mWLQFP48 363

VFQFPN36 1000

Maximum power dissipation –40 85 °C

T

A Ambient temperature

Low power dissipation

J Junction temperature range –40 105 °C

T

1. When the ADC is used, refer to Table 42: ADC characteristics.

2. It is recommended to power V
between V

is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal

3. If T

A

characteristics on page 74).

4. In low power dissipation state, T

Table 6.2: Thermal characteristics on page 74).

DD

and V

can be tolerated during power-up and operation.

DDA

and V

DD

can be extended to this range as long as TJ does not exceed TJmax (see

A

from the same source. A maximum difference of 300 mV

DDA

(4)

–40 105 °C

5.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Table 9. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate 0

t

VDD

fall time rate 20

V

DD

5.3.3 Embedded reset and power control block characteristics

The parameters given in Tab l e 1 0 are derived from tests performed under the ambient
temperature and V

supply voltage conditions summarized in Tab l e 8 .

DD

∞

µs/V

∞

Doc ID 15058 Rev 5 31/79

Electrical characteristics STM32F101x4, STM32F101x6

.

Table 10. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V

PLS[2:0]=000 (falling edge) 2 2.08 2.16 V

PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V

PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V

PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V

PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V

PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V

V

PVD

Programmable voltage
detector level selection

PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V

PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V

PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V

PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V

PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V

PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V

PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V

PLS[2:0]=111 (rising edge) 2.76 2.88 3 V

PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V

(2)

V

PVDhyst

V

POR/PDR

V

PDRhyst

t

RSTTEMPO

1. The product behavior is guaranteed by design down to the minimum V

2. Guaranteed by design, not tested in production.

PVD hysteresis 100 mV

(1)

Power on/power down
reset threshold

(2)

PDR hysteresis 40 mV

(2)

Reset temporization 1.5 2.5 4.5 ms

Falling edge

Rising edge 1.84 1.92 2.0 V

POR/PDR

1.8

value.

1.88 1.96 V

32/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

5.3.4 Embedded reference voltage

The parameters given in Tab l e 1 1 are derived from tests performed under the ambient
temperature and V

Table 11. Embedded internal reference voltage

Symbol Parameter Conditions Min Typ Max Unit

supply voltage conditions summarized in Tab l e 8 .

DD

V

REFINT

T

S_vrefint

V

RERINT

T

Coeff

1. Shortest sampling time can be determined in the application by multiple iterations.

2. Guaranteed by design, not tested in production.

Internal reference voltage –40 °C < TA < +85 °C 1.16 1.20 1.24 V

ADC sampling time when reading

(1)

the internal reference voltage

Internal reference voltage spread

(2)

over the temperature range

(2)

Temperature coefficient 100

5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption

measurement scheme.

All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption

5.1

17.1

= 3 V ±10 mV 10 mV

V

DD

(2)

µs

ppm/

°C

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

or VSS (no load)

DD

wait state from 24 to 36 MHz)

● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

PCLK1

= f

HCLK/2

, f

PCLK2

= f

HCLK

The parameters given in Tab l e 1 2 are derived from tests performed under the ambient
temperature and V

supply voltage conditions summarized in Tab l e 8 .

DD

Doc ID 15058 Rev 5 33/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 12. Maximum current consumption in Run mode, code with data processing

running from Flash

(1)

Max

Symbol Parameter Conditions f

36 MHz 26

External clock

(2)

, all

peripherals enabled

24 MHz 18

16 MHz 13

HCLK

= 85 °C

T

A

Unit

I

DD

Supply current
in Run mode

(2)

External clock

, all

peripherals Disabled

8 MHz 7

mA

36 MHz 19

24 MHz 13

16 MHz 10

8 MHz 6

1. Based on characterization, not tested in production.

2. External clock is 8 MHz and PLL is on when f

Table 13. Maximum current consumption in Run mode, code with data processing

HCLK

> 8 MHz.

running from RAM

(1)

Max

Symbol Parameter Conditions f

External clock

(2)

, all

peripherals enabled

I

DD

Supply current in
Run mode

External clock

(2)

all

peripherals disabled

HCLK

= 85 °C

T

A

36 MHz 20

24 MHz 14

16 MHz 10

8 MHz 6

36 MHz 15

24 MHz 10

16 MHz 7

8 MHz 5

Unit

mA

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

34/79 Doc ID 15058 Rev 5

HCLK

max, f

DD

> 8 MHz.

HCLK

max.

STM32F101x4, STM32F101x6 Electrical characteristics

0

5

10

15

20

25

– 45°C 25 °C 70 °C 85 °C

Temperature (°C)

Consumption (mA)

36 MHz

16 MHz

8 MHz

0

2

4

6

8

10

12

14

16

– 45°C 25 °C 70 °C 85 °C

Temperature (°C)

Consumption (mA)

36 MHz

16 MHz

8 MHz

Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals enabled

Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) -

code with data processing running from RAM, peripherals disabled

Doc ID 15058 Rev 5 35/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 14. Maximum current consumption in Sleep mode, code running from Flash

or RAM

(1)

Max

Symbol Parameter Conditions f

36 MHz 14

External clock

(2)

all

peripherals enabled

24 MHz 10

16 MHz 7

HCLK

= 85 °C

T

A

Unit

I

DD

Supply current in
Sleep mode

(2)

External clock

, all

peripherals disabled

8 MHz 4

36 MHz 5

24 MHz 4.5

16 MHz 4

8 MHz 3

1. Based on characterization, tested in production at V

2. External clock is 8 MHz and PLL is on when f

Table 15. Typical and maximum current consumptions in Stop and Standby modes

HCLK

Symbol Parameter Conditions

max and f

DD

> 8 MHz.

V

HCLK

DD/VBAT

= 2.0 V

max with peripherals enabled.

(1)

Typ

V

DD

= 2.4 V

/ V

BAT

V

DD/VBAT

= 3.3 V

Regulator in Run mode,

I

DD

Supply current
in Stop mode

Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)

Regulator in Low Power mode,
Low-speed and high-speed internal RC
oscillators and high-speed oscillator OFF
(no independent watchdog)

Low-speed internal RC oscillator and
independent watchdog ON

- 21.3 21.7 160

- 11.3 11.7 145

-2.63.4-

Max

T

A

85 °C

=

mA

Unit

(2)

µA

Supply current
in Standby
mode

Low-speed internal RC oscillator ON,
independent watchdog OFF

Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF

I

DD_VBAT

Backup domain
supply current

1. Typical values are measured at TA = 25 °C.

2. Based on characterization, not rested in production.

Low-speed oscillator and RTC ON 0.9 1.1 1.4 1.9

36/79 Doc ID 15058 Rev 5

-2.43.2-

- 1.7 2 3.2

STM32F101x4, STM32F101x6 Electrical characteristics

0

0.5

1

1.5

2

2.5

–40 °C 25 °C 70 °C 85 °C 105 °C

Temperature (°C)

Consumption ( µA )

2 V

2.4 V

3 V

3.6 V

ai17351

0

5

10

15

20

25

30

35

40

45

–45 °C 25 °C 85 °C

Temperature (°C)

Consumption (µA)

3.3 V

3.6 V

Figure 14. Typical current consumption on V

V

values

BAT

with RTC on versus temperature at different

BAT

Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus

temperature at V

= 3.3 V and 3.6 V

DD

Doc ID 15058 Rev 5 37/79

Electrical characteristics STM32F101x4, STM32F101x6

0

5

10

15

20

25

30

–45 °C 25 °C 85 °C

Temperature (°C)

Consumption (µA)

3.3 V

3.6 V

0

0.5

1

1.5

2

2.5

3

3.5

–45 °C 25 °C 85 °C

Temperature (°C)

Consumpt ion (µA)

3.3 V

3.6 V

Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus

temperature at V

= 3.3 V and 3.6 V

DD

Figure 17. Typical current consumption in Standby mode versus temperature at V

= 3.3 V and

DD

3.6 V

38/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

Typical current consumption

The MCU is placed under the following conditions:

● All I/O pins are in input mode with a static value at V

● All peripherals are disabled except if it is explicitly mentioned

● The Flash access time is adjusted to f

frequency (0 wait state from 0 to 24 MHz, 1

HCLK

wait state from 24 to 36 MHz)

● Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)

● When the peripherals are enabled f

f

/4

PCLK2

PCLK1

= f

HCLK/4

The parameters given in Tab l e 1 6 are derived from tests performed under the ambient
temperature and V

Table 16. Typical current consumption in Run mode, code with data processing

supply voltage conditions summarized in Tab l e 8 .

DD

running from Flash

Symbol Parameter Conditions f

HCLK

All peripherals

36 MHz 17.2 13.8

or VSS (no load)

DD

, f

PCLK2

(1)

Typ

enabled

(2)

= f

HCLK/2

All peripherals

, f

ADCCLK

(1)

Typ

disabled

=

Unit

24 MHz 11.2 8.9

16 MHz 8.1 6.6

8 MHz 5 4.2

External

(3)

clock

4 MHz 3 2.6

2 MHz 2 1.8

1 MHz 1.5 1.4

500 kHz 1.2 1.2

I

DD

Supply
current in
Run mode

125 kHz 1.05 1

mA

36 MHz 16.5 13.1

24 MHz 10.5 8.2

Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency

16 MHz 7.4 5.9

8 MHz 4.3 3.6

4 MHz 2.4 2

2 MHz 1.5 1.3

1 MHz 1 0.9

500 kHz 0.7 0.65

125 kHz 0.5 0.45

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

DD

HCLK

= 3.3 V.

> 8 MHz.

Doc ID 15058 Rev 5 39/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 17. Typical current consumption in Sleep mode, code running from Flash or

RAM

Symbol Parameter Conditions f

36 MHz 6.7 3.1

24 MHz 4.8 2.3

16 MHz 3.4 1.8

8 MHz 2 1.2

External clock

(3)

4 MHz 1.5 1.1

2 MHz 1.25 1

1 MHz 1.1 0.98

500 kHz 1.05 0.96

I

DD

Supply
current in
Sleep mode

125 kHz 1 0.95

36 MHz 6.1 2.5

24 MHz 4.2 1.7

Running on High
Speed Internal RC
(HSI), AHB
prescaler used to
reduce the
frequency

16 MHz 2.8 1.2

8 MHz 1.4 0.55

4 MHz 0.9 0.5

2 MHz 0.7 0.45

1 MHz 0.55 0.42

HCLK

(1)

Typ

All peripherals

enabled

(2)

All peripherals

(1)

Typ

disabled

Unit

mA

500 kHz 0.48 0.4

125 kHz 0.4 0.38

1. Typical values are measures at TA = 25 °C, V

2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).

3. External clock is 8 MHz and PLL is on when f

DD

HCLK

= 3.3 V.

> 8 MHz.

40/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Ta bl e 1 8. The MCU is placed
under the following conditions:

● all I/O pins are in input mode with a static value at V

● all peripherals are disabled unless otherwise mentioned

● the given value is calculated by measuring the current consumption

– with all peripherals clocked off

– with only one peripheral clocked on

● ambient operating temperature and V

supply voltage conditions summarized in

DD

Ta bl e 5 .

Table 18. Peripheral current consumption

Peripheral Typical consumption at 25 °C Unit

TIM2 0.6

APB1

TIM3 0.6

USART2 0.21

I2C 0.18

GPIO A 0.21

or VSS (no load)

DD

GPIO B 0.21

GPIO C 0.21

APB2

GPIO D 0.21

(1)

ADC

SPI 0.24

USART1 0.35

1. Specific conditions for ADC: f
in the ADC_CR2 register is set to 1.

= 28 MHz, f

HCLK

5.3.6 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Tab l e 1 9 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Ta bl e 8 .

APB1

= f

HCLK

/2, f

APB2

= f

1.4

HCLK

, f

ADCCLK

= f

/2, ADON bit

APB2

mA

Doc ID 15058 Rev 5 41/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 19. High-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HSE_ext

V

HSEH

V

t

w(HSE)

t

w(HSE)

t

r(HSE)

t

f(HSE)

C

in(HSE)

DuCy

HSEL

I

User external clock source
frequency

(1)

OSC_IN input pin high level voltage 0.7V

OSC_IN input pin low level voltage V

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle 45 55 %

(HSE)

OSC_IN Input leakage current VSS≤ VIN≤ V

L

(1)

(1)

(1)

DD

1825MHz

DD

SS

5

5pF

V

DD

0.3V

DD

20

±1 µA

ns

1. Guaranteed by design, not tested in production.

Low-speed external user clock generated from an external source

The characteristics given in Tab l e 2 0 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Ta bl e 8 .

Table 20. Low-speed external user clock characteristics

Symbol Parameter Conditions Min Typ Max Unit

V

f

LSE_ext

V

LSEH

User external clock source
frequency

(1)

OSC32_IN input pin high level
voltage

0.7V

32.768 1000 kHz

DD

V

DD

V

V

LSEL

t

w(LSE)

t

w(LSE)

t

r(LSE)

t

f(LSE)

C

in(LSE)

DuCy

1. Guaranteed by design, not tested in production.

OSC32_IN input pin low level
voltage

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

Duty cycle 30 70 %

(LSE)

OSC32_IN Input leakage current VSS≤ VIN≤ V

I

L

(1)

(1)

(1)

DD

V

450

SS

5pF

0.3V

DD

50

±1 µA

ns

42/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

ai14127b

OS C _I N

External

STM32F10xxx

clock source

V

HSEH

t

f(HSE)

t

W(HSE)

I

L

90%

10%

T

HSE

t

t

r(HSE)

t

W(HSE)

f

HSE_ext

V

HSEL

Figure 18. High-speed external clock source AC timing diagram

Figure 19. Low-speed external clock source AC timing diagram

V

LSEH

90%

V

LSEL

10%

t

r(LSE)

External
clock source

f

LSE_ext

T

LSE

t

f(LSE)

OSC32_IN

t

W(LSE)

I

L

t

W(LSE)

t

STM32F10xxx

ai14140c

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 21 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Doc ID 15058 Rev 5 43/79

Electrical characteristics STM32F101x4, STM32F101x6

ai14128b

OSC_OU T

OSC_IN

f

HSE

C

L1

R

F

STM32F10xxx

8 MHz
resonator

Resonator with
integrated capacitors

Bias

controlled

gain

R

EXT

(1)

C

L2

Table 21. HSE 4-16 MHz oscillator characteristics

(1)(2)

Symbol Parameter Conditions Min Typ Max Unit

f

OSC_IN

R

Oscillator frequency 4 8 16 MHz

Feedback resistor 200 kΩ

F

Recommended load capacitance

C

i

g

t

SU(HSE)

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

2. Based on characterization, not tested in production.

3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.

4. t

SU(HSE)

oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer

versus equivalent serial
resistance of the crystal (R

HSE driving current

2

Oscillator transconductance Startup 25 mA/V

m

(4)

Startup time VDD is stabilized 2 ms

S

RS = 30 Ω 30 pF

(3)

)

= 3.3 V, VIN = V

V

DD

SS

with 30 pF load

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz

1mA

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 20). C

and C

L1

are usually the

L2

same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C

and CL2. PCB and MCU pin capacitance must be included (10 pF

L1

can be used as a rough estimate of the combined pin and board capacitance) when sizing
C

and CL2. Refer to the application note AN2867 “Oscillator design guide for ST

L1

microcontrollers” available from the ST website www.st.com.

44/79 Doc ID 15058 Rev 5

Figure 20. Typical application with an 8 MHz crystal

1. R

value depends on the crystal characteristics.

EXT

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta bl e 22 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal

STM32F101x4, STM32F101x6 Electrical characteristics

resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).

Table 22. LSE oscillator characteristics (f

= 32.768 kHz)

LSE

Symbol Parameter Conditions Min Typ Max Unit

(1) (2)

R

F

Feedback resistor 5 MΩ

Recommended load capacitance

C

I

2

g

m

versus equivalent serial
resistance of the crystal (R

LSE driving current

)

S

RS = 30 KΩ 15 pF

V

= 3.3 V

DD

VIN = V

SS

1.4 µA

Oscillator transconductance 5 µA/V

TA = 50 °C 1.5

T

= 25 °C 2.5

A

= 10 °C 4

T

A

T

= 0 °C 6

is

(3)

t

SU(LSE)

1. Based on characterization, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.

3. t

SU(LSE)

reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer

Startup time

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is

V

DD

stabilized

A

= -10 °C 10

T

A

T

= -20 °C 17

A

= -30 °C 32

T

A

= -40 °C 60

T

A

s

Note: For CL1 and C

it is recommended to use high-quality ceramic capacitors in the 5 pF to

L2

15 pF range selected to match the requirements of the crystal or resonator. C
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C
Load capacitance C
C

is the pin capacitance and board or trace PCB-related capacitance. Typically, it is

stray

has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + C

L

L1

between 2 pF and 7 pF.

Caution: To avoid exceeding the maximum value of C

to use a resonator with a load capacitance C
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
then C

= CL2 = 8 pF.

L1

Doc ID 15058 Rev 5 45/79

and CL2.

and C

L1

and CL2 (15 pF) it is strongly recommended

L1

≤

7 pF. Never use a resonator with a load

L

= 6 pF, and C

L

stray

stray

L2,

where

= 2 pF,

are

Electrical characteristics STM32F101x4, STM32F101x6

ai14129b

OSC32_OU T

OSC32_IN

f

LSE

C

L1

R

F

STM32F10xxx

32.768 KHz
resonator

Resonator with
integrated capacitors

Bias

controlled

gain

C

L2

Figure 21. Typical application with a 32.768 kHz crystal

5.3.7 Internal clock source characteristics

The parameters given in Tab l e 2 3 are derived from tests performed under the ambient
temperature and V

High-speed internal (HSI) RC oscillator

supply voltage conditions summarized in Tab l e 8 .

DD

Table 23. HSI oscillator characteristics

(1)

Symbol Parameter Conditions Min Typ Max Unit

f

HSI

DuCy

ACC

t

su(HSI)

I

DD(HSI)

1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from
the ST website www.st.com.

3. Guaranteed by design, not tested in production.

4. Based on characterization, not tested in production.

Frequency 8 MHz

Duty cycle 45 55 %

(HSI)

Accuracy of the HSI

HSI

oscillator

HSI oscillator

(4)

startup time

HSI oscillator power

(4)

consumption

User-trimmed with the RCC_CR
register

Factory­calibrated

(2)

TA = –40 to 105 °C –2 2.5 %

= –10 to 85 °C –1.5 2.2 %

T

A

(4)

T

= 0 to 70 °C –1.3 2 %

A

= 25 °C –1.1 1.8 %

T

A

12µs

80 100 µA

(3)

1

%

46/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 24. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

(2)

f

LSI

t

su(LSI)

I

DD(LSI)

1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified.

2. Based on characterization, not tested in production.

3. Guaranteed by design, not tested in production.

Frequency 30 40 60 kHz

(3)

LSI oscillator startup time 85 µs

(3)

LSI oscillator power consumption 0.65 1.2 µA

(1)

Wakeup time from low-power mode

The wakeup times given in Ta bl e 2 5 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:

● Stop or Standby mode: the clock source is the RC oscillator

● Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under the ambient temperature and V
voltage conditions summarized in Tabl e 8.

Table 25. Low-power mode wakeup timings

Symbol Parameter Typ Unit

t

WUSLEEP

t

WUSTOP

t

WUSTDBY

1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.

(1)

5.3.8 PLL characteristics

The parameters given in Tab l e 2 6 are derived from tests performed under the ambient
temperature and V

Table 26. PLL characteristics

Symbol Parameter

f

PLL_IN

f

PLL_OUT

(1)

Wakeup from Sleep mode 1.8 µs

Wakeup from Stop mode (regulator in run mode) 3.6

Wakeup from Stop mode (regulator in low-power mode) 5.4

(1)

Wakeup from Standby mode 50 µs

supply voltage conditions summarized in Tab l e 8 .

DD

Val ue

PLL input clock

(2)

Min

(1)

Typ Max

18.025MHz

(1)

PLL input clock duty cycle 40 60 %

PLL multiplier output clock 16 36 MHz

supply

DD

µs

Unit

Doc ID 15058 Rev 5 47/79

Electrical characteristics STM32F101x4, STM32F101x6

Table 26. PLL characteristics

Val ue

Symbol Parameter

Min

(1)

Typ Max

(1)

Unit

t

LOCK

PLL lock time 200 µs

Jitter Cycle-to-cycle jitter 300 ps

1. Based on device characterization, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f

PLL_OUT

.

5.3.9 Memory characteristics

Flash memory

The characteristics are given at TA = –40 to 85 °C unless otherwise specified.

Table 27. Flash memory characteristics

Symbol Parameter Conditions Min

t

prog

t

ERASE

t

ME

I

DD

V

prog

1. Guaranteed by design, not tested in production.

16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs

Page (1 KB) erase time TA = –40 to +85 °C 20 40 ms

Mass erase time TA = –40 to +85 °C 20 40 ms

Supply current

Programming voltage 2 3.6 V

Read mode
f

= 36 MHz with 1 wait

HCLK

state, V

= 3.3 V

DD

Write / Erase modes
f

= 36 MHz, VDD = 3.3 V

HCLK

Power-down mode / Halt,

= 3.0 to 3.6 V

V

DD

(1)

Typ Max

20 mA

50 µA

(1)

Unit

5mA

Table 28. Flash memory endurance and data retention

Symbol Parameter Conditions

N

t

1. Based on characterization not tested in production.

2. Cycling performed over the whole temperature range.

5.3.10 EMC characteristics

Endurance TA = –40 °C to 85 °C

END

RET

Data retention

TA = 85 °C, 1 kcycle

T

Susceptibility tests are performed on a sample basis during device characterization.

48/79 Doc ID 15058 Rev 5

= 55 °C, 10 kcycle

A

(2)

(2)

Min

10

30

20

Val ue

(1)

Typ Max

Unit

kcycles

Ye a r s

STM32F101x4, STM32F101x6 Electrical characteristics

Functional EMS (Electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until

a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V

V

through a 100 pF capacitor, until a functional disturbance occurs. This test is

SS

compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Tab l e 2 9 . They are based on the EMS levels and classes
defined in application note AN1709.

Table 29. EMS characteristics

Symbol Parameter Conditions Level/Class

= 3.3 V, TA = +25 °C,

V

V

V

FESD

EFTB

Voltage limits to be applied on any I/O pin to
induce a functional disturbance

Fast transient voltage burst limits to be
applied through 100 pF on VDD and V

SS

pins

to induce a functional disturbance

DD

f

= 36 MHz

HCLK

conforms to IEC 61000-4-2

VDD = 3.3 V, TA = +25 °C,
f

= 36 MHz

HCLK

conforms to IEC 61000-4-4

DD

and

2B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

● Corrupted program counter

● Unexpected reset

● Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).

Doc ID 15058 Rev 5 49/79

Electrical characteristics STM32F101x4, STM32F101x6

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC61967-2 standard which specifies the test board and the pin loading.

Table 30. EMI characteristics

Symbol Parameter Conditions

Monitored

frequency band

0.1 MHz to 30 MHz 7

= 3.3 V, TA = 25 °C,

V

DD

S

EMI

Peak level

LQFP100 package
compliant with
IEC 61967-2

130 MHz to 1GHz 13

SAE EMI Level 3.5 -

5.3.11 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Table 31. ESD absolute maximum ratings

Symbol Ratings Conditions Class

Max vs. [f

8/36 MHz

HSE/fHCLK

Maximum

value

(1)

]

Unit

dBµV30 MHz to 130 MHz 8

Unit

V

ESD(HBM)

V

ESD(CDM)

1. Based on characterization results, not tested in production.

Electrostatic discharge
voltage (human body model)

Electrostatic discharge
voltage (charge device model)

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up
performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

50/79 Doc ID 15058 Rev 5

These tests are compliant with EIA/JESD 78 IC latch-up standard.

Table 32. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class T

A

TA = +25 °C

conforming to JESD22-A114

TA = +25 °C

conforming to JESD22-C101

2 2000

II 500

= +85 °C conforming to JESD78A II level A

V

STM32F101x4, STM32F101x6 Electrical characteristics

5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above V
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).

The test results are given in Tab l e 3 3

Table 33. I/O current injection susceptibility

Symbol Description

(for standard, 3 V-capable I/O pins) should be avoided during normal product

DD

Functional susceptibility

Negative
injection

Positive

injection

Unit

I

INJ

Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13

Injected current on all FT pins -5 +0

-0 +0

mA

Injected current on any other pin -5 +5

Doc ID 15058 Rev 5 51/79

Electrical characteristics STM32F101x4, STM32F101x6

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Ta bl e 3 4 are derived from tests
performed under the conditions summarized in Tab l e 8 . All I/Os are CMOS and TTL
compliant.

Table 34. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Standard IO input low
level voltage

V

IL

IO FT

(1)

voltage

Standard IO input high
level voltage

V

IH

IO FT

(1)

voltage

input low level

input high level

–0.3 0.28*(V

–0.3 0.32*(V

0.41*(V

> 2 V

V

DD

V

≤ 2 V 5.2

DD

0.42*(V

-2 V)+1.3 V VDD+0.3 V

DD

-2 V)+1 V

DD

-2 V)+0.8 V V

DD

-2V)+0.75 V V

DD

5.5

Standard IO Schmitt
trigger voltage

hys

hysteresis

V

IO FT Schmitt trigger
voltage hysteresis

Input leakage current

I

lkg

(2)

(2)

V

(4)

≤ VIN≤ V

SS

Standard I/Os

= 5 V

V

IN

DD

I/O FT

R

R

1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

Weak pull-up equivalent

PU

PD

C

IO

(5)

resistor

Weak pull-down
equivalent resistor

(5)

I/O pin capacitance 5 pF

V

= V

IN

SS

V

= V

IN

DD

disabled.

PMOS/NMOS contribution

to the series resistance is minimum (~10% order).

200 mV

DD

(3)

5% V

±1

3

30 40 50 kΩ

30 40 50 kΩ

V

mV

µA

52/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

ai17277b

VDD (V)

1.3

0.8

2 3.6

Input range

not guaranteed

1.59

1

2.7

V

IH

=0.41(V

DD

-2)+1.3

3

0.7

CMOS standard requirement V

IH

=0.65V

DD

3.3

VIH/VIL (V)

CMOS standard requirement V

IL

=0.35V

DD

V

IL

= 0.28(V

DD

–2)+0.8

1.25

1.96

1.71

1.71

1.59

1

1.08

1.08

V

ILmax

V

IHmin

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)(MIN

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 and Figure 23 for standard I/Os, and
in Figure 24 and Figure 25 for 5 V tolerant I/Os.

Figure 22. Standard I/O input characteristics - CMOS port

Figure 23. Standard I/O input characteristics - TTL port

Doc ID 15058 Rev 5 53/79

Electrical characteristics STM32F101x4, STM32F101x6

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Figure 24. 5 V tolerant I/O input characteristics - CMOS port

Figure 25. 5 V tolerant I/O input characteristics - TTL port

54/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

Output driving current

The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V

OL/VOH

).

In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:

● The sum of the currents sourced by all the I/Os on V

consumption of the MCU sourced on V
I

(see Ta bl e 6 ).

VDD

● The sum of the currents sunk by all the I/Os on V

consumption of the MCU sunk on V
I

(see Ta bl e 6).

VSS

cannot exceed the absolute maximum rating

DD,

cannot exceed the absolute maximum rating

SS

plus the maximum Run

DD,

plus the maximum Run

SS

Output voltage levels

Unless otherwise specified, the parameters given in Ta bl e 3 5 are derived from tests
performed under the ambient temperature and V
in Ta bl e 8 . All I/Os are CMOS and TTL compliant.

Table 35. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

supply voltage conditions summarized

DD

Output Low level voltage for an I/O pin

(1)

V

OL

when 8 pins are sunk at the same time

Output High level voltage for an I/O pin

(3)

V

OH

V

V

OH

V

V

OH

V

V

OH

1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The IIO current sourced by the device must always respect the absolute maximum rating specified in

4. Based on characterization data, not tested in production.

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

OL

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

OL

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

Output low level voltage for an I/O pin

(1)

OL

when 8 pins are sunk at the same time

Output high level voltage for an I/O pin

(3)

when 8 pins are sourced at the same time

and the sum of I

Table 6 and the sum of I

(I/O ports and control pins) must not exceed I

IO

(I/O ports and control pins) must not exceed I

IO

CMOS port

I

IO

2.7 V < VDD < 3.6 V

TTL port

I

IO

2.7 V < V

I

= +20 mA

IO

2.7 V < VDD < 3.6 V

= +6 mA

I

IO

2 V < VDD < 2.7 V

VSS

= +8 mA,

(2)

= +8 mA

< 3.6 V

DD

.

VDD

(2)

(4)

(4)

,,

.

V

–0.4

DD

2.4

V

–1.3

DD

VDD–0.4

0.4

0.4

1.3

0.4

V

V

V

V

Doc ID 15058 Rev 5 55/79

Electrical characteristics STM32F101x4, STM32F101x6

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 26 and

Ta bl e 3 6, respectively.

Unless otherwise specified, the parameters given in Ta bl e 3 6 are derived from tests
performed under the ambient temperature and V
in Ta bl e 8 .

Table 36. I/O AC characteristics

MODEx

[1:0] bit

value

10

01

11

Symbol Parameter Conditions Max Unit

(1)

f

max(IO)out

t

f(IO)out

t

r(IO)out

f

max(IO)out

t

f(IO)out

t

r(IO)out

F

max(IO)out

t

f(IO)out

t

r(IO)out

Maximum frequency

Output high to low level fall
time

Output low to high level rise
time

Maximum frequency

Output high to low level fall
time

Output low to high level rise
time

Maximum Frequency

Output high to low level fall
time

Output low to high level rise
time

Pulse width of external

-t

EXTIpw

signals detected by the
EXTI controller

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.

2. The maximum frequency is defined in Figure 26.

3. Guaranteed by design, not tested in production.

(1)

(2)

(2)

(2)

supply voltage conditions summarized

DD

CL = 50 pF, V

= 50 pF, V

C

L

CL= 50 pF, V

= 50 pF, V

C

L

CL= 30 pF, V

= 50 pF, V

C

L

C

= 50 pF, V

L

CL = 30 pF, V

= 50 pF, V

C

L

CL = 50 pF, VDD = 2 V to 2.7 V 12

C

= 30 pF, V

L

CL = 50 pF, V

CL = 50 pF, V

= 2 V to 3.6 V 2 MHz

DD

(3)

125

= 2 V to 3.6 V

DD

= 2 V to 3.6 V 10 MHz

DD

= 2 V to 3.6 V

DD

= 2.7 V to 3.6 V 50 MHz

DD

= 2.7 V to 3.6 V 30 MHz

DD

= 2 V to 2.7 V 20 MHz

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2.7 V to 3.6 V 5

DD

= 2.7 V to 3.6 V 8

DD

= 2 V to 2.7 V 12

DD

125

25

25

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

10 ns

ns

ns

ns

56/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

ai14131

10%

90%

50%

t

r(IO)out

OUTPUT

EXTERNAL

ON 50pF

Maximum fr equency is achieved if (tr + tf) ≤ 2/3) T and if the duty cycle is (45-55%)

10 %

50%

90%

when loaded by 50pF

T

t

r(IO)out

ai14132d

STM32F10x

R

PU

NRST

(2)

V

DD

Filter

Internal reset

0.1 µF

External
reset circuit

(1)

Figure 26. I/O AC characteristics definition

5.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R

Unless otherwise specified, the parameters given in Ta bl e 3 7 are derived from tests
performed under the ambient temperature and V
in Ta bl e 8 .

Table 37. NRST pin characteristics

(see Ta bl e 3 4).

PU

supply voltage conditions summarized

DD

Symbol Parameter Conditions Min Typ Max Unit

V

IL(NRST)

V

IH(NRST)

V

V

V

NF(NRST)

1. Guaranteed by design, not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

(1)

NRST Input low level voltage –0.5 0.8

(1)

NRST Input high level voltage 2 VDD+0.5

hys(NRST)

R

PU

F(NRST)

the series resistance must be minimum

NRST Schmitt trigger voltage
hysteresis

Weak pull-up equivalent resistor

(1)

NRST Input filtered pulse 100 ns

(1)

NRST Input not filtered pulse 300 ns

(~10% order).

(2)

200 mV

V

IN

= V

30 40 50 kΩ

SS

Figure 27. Recommended NRST pin protection

V

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 37. Otherwise the reset will not be taken into account by the device.

Doc ID 15058 Rev 5 57/79

max level specified in

IL(NRST)

Electrical characteristics STM32F101x4, STM32F101x6

5.3.15 TIM timer characteristics

The parameters given in Tab l e 3 8 are guaranteed by design.

Refer to Section 5.3.12: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).

Table 38. TIMx

Symbol Parameter Conditions Min Max Unit

(1)

characteristics

t

res(TIM)

f

EXT

Res

Timer resolution time

Timer external clock
frequency on CH1 to CH4

Timer resolution 16 bit

TIM

16-bit counter clock period

t

COUNTER

when internal clock is
selected

t

MAX_COUNT

1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.

Maximum possible count

5.3.16 Communications interfaces

I2C interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 3 9 are derived from tests
performed under the ambient temperature, f
conditions summarized in Ta bl e 8 .

The STM32F101xx Low-density access line I
standard I
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V

The I

injection characteristics

(SDA and SCL)

2

C communication protocol with the following restrictions: t

2

C characteristics are described in Ta b le 3 9 . Refer also to

for more details on the input/output alternate function characteristics

.

1

f

0

f

TIMxCLK

TIMxCLK

= 36 MHz

= 36 MHz

27.8 ns

f

TIMxCLK

/2

018MHz

1 65536

f

TIMxCLK

= 36 MHz

0.0278 1820 µs

65536 × 65536

f

= 36 MHz

TIMxCLK

frequency and VDD supply voltage

PCLK1

2

C interface meets the requirements of the

119.2 s

he I/O pins SDA and

is disabled, but is still present.

DD

Section 5.3.12: I/O current

t

TIMxCLK

MHz

t

TIMxCLK

t

TIMxCLK

58/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

Table 39. I2C characteristics

Symbol Parameter

Standard mode I

2C(1)

Fast mode I2C

Min Max Min Max

(1)(2)

Unit

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA)

t

r(SCL)

t

f(SDA)

t

f(SCL)

t

h(STA)

t

su(STA)

t

su(STO)

t

w(STO:STA)

C

Guaranteed by design, not tested in production.

1.

2. f

PCLK1

4 MHz to achieve fast mode I
maximum I2C fast mode clock.

The maximum hold time of the Start condition has only to be met if the interface does not stretch the low

3.
period of SCL signal.

The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

4.
undefined region of the falling edge of SCL.

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100

SDA data hold time 0

(3)

(4)

0

SDA and SCL rise time 1000 20+0.1Cb300

SDA and SCL fall time 300 300

Start condition hold time 4.0 0.6

Repeated Start condition setup
time

4.7 0.6

Stop condition setup time 4.0 0.6 µs

Stop to Start condition time (bus
free)

Capacitive load for each bus line 400 400 pF

b

must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than

2

C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz

4.7 1.3 µs

900

µs

(3)

ns

µs

Doc ID 15058 Rev 5 59/79

Electrical characteristics STM32F101x4, STM32F101x6

ai14133d

Start

SDA

100 Ω

4.7kΩ

I²C bus

4.7kΩ

100 Ω

V

DD

V

DD

STM32F10x

SDA

SCL

t

f(SDA)

t

r(SDA)

SCL

t

h(STA)

t

w(SCLH)

t

w(SCLL)

t

su(SDA)

t

r(SCL)

t

f(SCL)

t

h(SDA)

Start repeated

Start

t

su(STA)

t

su(STO)

Stop

t

su(STO:STA)

Figure 28. I2C bus AC waveforms and measurement circuit

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

Table 40. SCL frequency (f

f

(kHz)

SCL

= MHz, VDD = 3.3 V)

PCLK1

400 0x801E

DD

.

(1)(2)

I2C_CCR value

(1)

R

= 4.7 kΩ

P

300 0x8028

200 0x803C

100 0x00B4

50 0x0168

20 0x0384

1. RP = External pull-up resistance, f

2. For speeds around 200 kHz, the tolerance on the achieved speed is of
tolerance on the achieved speed
components used to design the application.

60/79 Doc ID 15058 Rev 5

= I2C speed,

SCL

±2%. These variations depend on the accuracy of the external

±5%. For other speed ranges, the

STM32F101x4, STM32F101x6 Electrical characteristics

SPI interface characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 1 are derived from tests
performed under the ambient temperature, f
conditions summarized in Ta bl e 8 .

Refer to Section 5.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 41. SPI characteristics

Symbol Parameter Conditions Min Max Unit

frequency and VDD supply voltage

PCLKx

f

SCK

1/t

c(SCK)

t

r(SCK)

t

f(SCK)

t

su(NSS)

t

h(NSS)

t

w(SCKH)

t

w(SCKL)

t

su(MI)

t

su(SI)

t

h(MI)

t

h(SI)

t

a(SO)

t

dis(SO)

t

v(SO)

t

v(MO)

t

h(SO)

t

h(MO)

SPI clock frequency

Master mode 0 18

Slave mode 0 18

SPI clock rise and fall
time

(1)

NSS setup time Slave mode 4 t

(1)

NSS hold time Slave mode 73

(1)

SCK high and low time

(1)

Data input setup time

(1)

Master mode

Data input setup time

(1)

Capacitive load: C = 30 pF 8

Master mode, f

= 36 MHz,

PCLK

presc = 4

SPI 1

Slave mode

Data input hold time

(1)

Master mode

Data input hold time

(1)

SPI 1

Slave mode

Slave mode, f

(1)(2)

Data output access time

presc = 4

Slave mode, f

(1)(3)

Data output disable time Slave mode 10

(1)

Data output valid time Slave mode (after enable edge) 25

(1)

Data output valid time

(1)

Data output hold time

(1)

Master mode (after enable
edge)

Slave mode (after enable edge) 25

Master mode (after enable

= 36 MHz,

PCLK

= 24 MHz 0 4 t

PCLK

edge)

PCLK

50 60

1

3

055

PCLK

3

4

MHz

ns

1. Based on characterization, not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.

3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z

Doc ID 15058 Rev 5 61/79

Electrical characteristics STM32F101x4, STM32F101x6

ai14134c

SCK Input

CPHA=0

MOSI

INPUT

MISO

OUT PUT

CPHA=0

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

NSS input

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

ai14135

SCK Input

CPHA=1

MOSI

INPUT

MISO

OUT PUT

CPHA=1

MS B O U T

MSB IN

BI T6 OU T

LSB IN

LSB OUT

CPOL=0

CPOL=1

BIT1 IN

t

SU(NSS)

t

c(SCK)

t

h(NSS)

t

a(SO)

t

w(SCKH)

t

w(SCKL)

t

v(SO)

t

h(SO)

t

r(SCK)

t

f(SCK)

t

dis(SO)

t

su(SI)

t

h(SI)

NSS input

Figure 29. SPI timing diagram - slave mode and CPHA = 0

Figure 30. SPI timing diagram - slave mode and CPHA = 1

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

DD

.

(1)

62/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

ai14136

SCK Input

CPHA=0

MOSI

OUTUT

MISO

INP UT

CPHA=0

MSBIN

M SB OUT

BIT6 IN

LSB OUT

LSB IN

CPOL=0

CPOL=1

B I T1 OUT

NSS input

t

c(SCK)

t

w(SCKH)

t

w(SCKL)

t

r(SCK)

t

f(SCK)

t

h(MI)

High

SCK Input

CPHA=1

CPHA=1

CPOL=0

CPOL=1

t

su(MI)

t

v(MO)

t

h(MO)

Figure 31. SPI timing diagram - master mode

(1)

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7V

DD

.

Doc ID 15058 Rev 5 63/79

Electrical characteristics STM32F101x4, STM32F101x6

5.3.17 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Ta bl e 4 2 are derived from tests
performed under the ambient temperature, f
conditions summarized in Ta bl e 8 .

Note: It is recommended to perform a calibration after each power-up.

Table 42. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

frequency and V

PCLK2

supply voltage

DDA

V

f

TRIG

R

R

C

t

t

t

STAB

t

CONV

DDA

f

ADC

f

S

V

AIN

AIN

ADC

ADC

CAL

t

lat

latr

t

S

Power supply 2.4 3.6 V

ADC clock frequency 0.6 14 MHz

(1)

Sampling rate 0.05 1 MHz

f

= 14 MHz 823 kHz

(1)

External trigger frequency

Conversion voltage range

(1)

External input impedance

(1)

Sampling switch resistance 1 kΩ

Internal sample and hold

(1)

(2)

ADC

See Equation 1 and

Ta bl e 4 3 for details

0 (V

SSA

or V

tied to ground)

REF-

V

capacitor

f

= 14 MHz 5.9 µs

(1)

Calibration time

ADC

83 1/f

= MHz 0.214 µs

f

Injection trigger conversion

(1)

ADC

latency

= 14 MHz 0.143 µs

f

Regular trigger conversion

(1)

ADC

latency

(1)

Sampling time f

(1)

Power-up time 0 0 1 µs

Total conversion time

(1)

= 14 MHz

ADC

f

= 14 MHz 1 18 µs

ADC

(including sampling time)

0.107 17.1 µs

1.5 239.5 1/f

14 to 252 (t

for sampling +12.5 for

S

successive approximation)

17 1/f

REF+

ADC

V

50 kΩ

8pF

ADC

(3)

3

2

(3)

1/f

1/f

1/f

ADC

ADC

ADC

ADC

1. Guaranteed by design, not tested in production.

2. V

is internally connected to V

REF+

3. For external triggers, a delay of 1/f

DDA

PCLK2

and V

is be internally connected to V

REF-

must be added to the latency specified in Table 42.

64/79 Doc ID 15058 Rev 5

SSA

.

STM32F101x4, STM32F101x6 Electrical characteristics

R

AIN

T

S

f

ADCCADC

2

N2+

()ln××

------------------------------------------------------------- - R

ADC

–<

Equation 1: R

max formula:

AIN

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

Table 43. R

Ts (cycles) tS (µs) R

max for f

AIN

= 14 MHz

ADC

(1)

max (kΩ)

AIN

1.5 0.11 0.4

7.5 0.54 5.9

13.5 0.96 11.4

28.5 2.04 25.2

41.5 2.96 37.2

55.5 3.96 50

71.5 5.11 NA

239.5 17.1 NA

1. Guaranteed by design, not tested in production.

Table 44. ADC accuracy - limited test conditions

Symbol Parameter Test conditions Typ Max

(1) (2)

(3)

Unit

ET Total unadjusted error

EO Offset error ±1 ±1.5

EG Gain error ±0.5 ±1.5

ED Differential linearity error ±0.7 ±1

EL Integral linearity error ±0.8 ±1.5

f

= 28 MHz,

PCLK2

f

= 14 MHz, R

ADC

= 3 V to 3.6 V

V

DDA

= 25 °C

T

A

< 10 kΩ,

AIN

Measurements made after
ADC calibration

±1.3 ±2

LSB

1. ADC DC accuracy values are measured after internal calibration.

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non­robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.

INJ(PIN)

and ΣI

in Section 5.3.12 does not

INJ(PIN)

3. Based on characterization, not tested in production.

Doc ID 15058 Rev 5 65/79

Electrical characteristics STM32F101x4, STM32F101x6

E

O

E

G

1LSB

IDEAL

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

E

T

=Total u nadjusted er ror: maximum deviation

between the actual and the ideal transfer curves.

E

O

=Offset error: deviation between the first actual

transition and the first ideal one.

E

G

=Gain er ror: deviation between the last ideal

transition and the last actual one.

E

D

=Differential linearity error: maximum deviation

between actual steps and the ideal one.

E

L

=Integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.

4095

4094

4093

5

4

3

2

1

0

7

6

1234567

4093 4094 4095 4096

(1)

(2)

E

T

E

D

E

L

(3)

V

DDA

V

SSA

ai15497

V

DDA

4096

[1LSB

IDEAL =

Table 45. ADC accuracy

Symbol Parameter Test conditions Typ Max

ET Total unadjusted error

EO Offset error ±1.5 ±2.5

EG Gain error ±1.5 ±3

ED Differential linearity error ±1 ±2

(1) (2) (3)

f

= 28 MHz,

PCLK2

= 14 MHz, R

f

ADC

V

= 2.4 V to 3.6 V

DDA

< 10 kΩ,

AIN

Measurements made after
ADC calibration

(4)

±2 ±5

EL Integral linearity error ±1.5 ±3

1. ADC DC accuracy values are measured after internal calibration.

2. Better performance could be achieved in restricted V

3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non­robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for I
affect the ADC accuracy.

, frequency and temperature ranges.

DD

INJ(PIN)

and ΣI

in Section 5.3.12 does not

INJ(PIN)

4. Based on characterization, not tested in production.

Figure 32. ADC accuracy characteristics

Unit

LSB

66/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Electrical characteristics

ai14139d

STM32F10xxx

V

DD

AINx

IL±1 µA

0.6 V

V

T

R

AIN

(1)

C

parasitic

V

AIN

0.6 V

V

T

R

ADC

(1)

C

ADC

(1)

12-bit

converter

Sample and hold ADC
converter

Figure 33. Typical connection diagram using the ADC

1. Refer to Table 42 for the values of R

2. C

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

parasitic

pad capacitance (roughly 7 pF). A high C
this, f

should be reduced.

ADC

AIN

, R

and C

ADC

value will downgrade conversion accuracy. To remedy

parasitic

ADC

.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 34. The 10 nF capacitors
should be ceramic (good quality). They should be placed them as close as possible to the
chip.

Figure 34. Power supply and reference decoupling

1 µF // 10 nF

STM32F10xx4/6

V

DDA

V

SSA

ai15498

Doc ID 15058 Rev 5 67/79

Electrical characteristics STM32F101x4, STM32F101x6

5.3.18 Temperature sensor characteristics

Table 46. TS characteristics

Symbol Parameter Min Typ Max Unit

(1)

T

L

Avg_Slope

(1)

V

25

(2)

t

START

S_temp

(3)(2)

T

V

(1)

Average slope 4.0 4.3 4.6 mV/°C

linearity with temperature

SENSE

Voltage at 25°C 1.34 1.43 1.52 V

Startup time 4 10 µs

ADC sampling time when reading the
temperature

1. Guaranteed by characterization, not tested in production.

2. Guaranteed by design, not tested in production.

3. Shortest sampling time can be determined in the application by multiple iterations.

±1 ±2

17.1 µs

°C

68/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Package characteristics

6 Package characteristics

6.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Doc ID 15058 Rev 5 69/79

Package characteristics STM32F101x4, STM32F101x6

Seating

Plane

C

A3

A1

A2

A

ddd C

Pin no. 1 ID

R = 0.20

Bottom View

1

48

e

E

L

L

12

13

D2

b

24

25

b

E2

36

37

e

D

V0_ME

0.50

7.30

0.75

5.80

5.80

6.20

6.20

5.60

5.60

13

1

24

37

ai15799

12

48

36

25

0.55

0.30

0.20

Figure 35. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package

outline

(1)

Figure 36. Recommended footprint

(dimensions in mm)

(1)(2)

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 47. VFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.020 0.050 0.0008 0.0020

A2 0.650 1.000 0.0256 0.0394

A3 0.250 0.0098

b 0.180 0.230 0.300 0.0071 0.0091 0.0118

D 6.850 7.000 7.150 0.2697 0.2756 0.2815

D2 2.250 4.700 5.250 0.0886 0.1850 0.2067

E 6.850 7.000 7.150 0.2697 0.2756 0.2815

E2 2.250 4.700 5.250 0.0886 0.1850 0.2067

e 0.450 0.500 0.550 0.0177 0.0197 0.0217

L 0.300 0.400 0.500 0.0118 0.0157 0.0197

ddd 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

70/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Package characteristics

Seating plane

ddd C

C

A3

A1

AA2

Pin # 1 ID
R = 0.20

ZR_ME

E2

b

19

10

18

27

28

36

19

D2

E

D

e

L

0.30

6.30

0.50

1.00

4.30

4.30

4.80

4.80

4.10

4.10

1

28

9

19

ai14870b

36

27

18

10

0.75

Figure 37. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package

outline

(1)

Figure 38. Recommended footprint

(dimensions in mm)

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead solder joint life.

Table 48. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data

millimeters inches

Symbol

Min Typ Max Min Typ Max

(1)(2)

(1)

A 0.800 0.900 1.000 0.0315 0.0354 0.0394

A1 0.020 0.050 0.0008 0.0020

A2 0.650 1.000 0.0256 0.0394

A3 0.250 0.0098

b 0.180 0.230 0.300 0.0071 0.0091 0.0118

D 5.875 6.000 6.125 0.2313 0.2362 0.2411

D2 1.750 3.700 4.250 0.0689 0.1457 0.1673

E 5.875 6.000 6.125 0.2313 0.2362 0.2411

E2 1.750 3.700 4.250 0.0689 0.1457 0.1673

e 0.450 0.500 0.550 0.0177 0.0197 0.0217

L 0.350 0.550 0.750 0.0138 0.0217 0.0295

ddd 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 15058 Rev 5 71/79

Package characteristics STM32F101x4, STM32F101x6

A

A2

A1

c

L1

L

E

E1

D

D1

e

b

ai14398b

48

3249

64 17

116

1.2

0.3

33

10.3

12.7

10.3

0.5

7.8

12.7

ai14909

Figure 39. LQFP64 – 10 x 10 mm, 64 pin low-profile

quad flat package outline

(1)

Figure 40. Recommended

footprint

(1)(2)

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 49. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A1 0.05 0.15 0.0020 0.0059

A2 1.35 1.40 1.45 0.0531 0.0551 0.0571

D1 10.00 0.3937

E1 10.00 0.3937

L1 1.00 0.0394

1. Values in inches are converted from mm and rounded to 4 decimal digits.

72/79 Doc ID 15058 Rev 5

A 1.60 0.0630

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 0.20 0.0035 0.0079

D 12.00 0.4724

E 12.00 0.4724

e 0.50 0.0197

θ 0° 3.5° 7° 0° 3.5° 7°

L 0.45 0.60 0.75 0.0177 0.0236 0.0295

Number of pins

N64

STM32F101x4, STM32F101x6 Package characteristics

D

D1

D3

A1

L1

L

k

c

b

ccc

C

A1

A2A

C

Seating plane

0.25 mm

Gage plane

E3

E1

E

12

13

24

25

48

1

36

37

Pin 1
identification

5B_ME

9.70

5.80

7.30

12

24

0.20

7.30

1

37

36

1.20

5.80

9.70

0.30

25

1.20

0.50

ai14911b

1348

Figure 41. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat

package outline

(1)

Figure 42. Recommended

footprint

1. Drawing is not to scale.

2. Dimensions are in millimeters.

Table 50. LQFP48 – 7 x 7mm, 48-pin low-profile quad flat package mechanical data

millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

(1)(2)

A 1.600 0.0630

A1 0.050 0.150 0.0020 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 0.200 0.0035 0.0079

D 8.800 9.000 9.200 0.3465 0.3543 0.3622

D1 6.800 7.000 7.200 0.2677 0.2756 0.2835

D3 5.500 0.2165

E 8.800 9.000 9.200 0.3465 0.3543 0.3622

E1 6.800 7.000 7.200 0.2677 0.2756 0.2835

E3 5.500 0.2165

e 0.500 0.0197

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 1.000 0.0394

k 0°3.5°7° 0°3.5°7°

ccc 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Doc ID 15058 Rev 5 73/79

Package characteristics STM32F101x4, STM32F101x6

6.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 8: General operating conditions on page 30.

The maximum chip-junction temperature, T

max, in degrees Celsius, may be calculated

J

using the following equation:

T

max = TA max + (PD max x ΘJA)

J

Where:

● T

● Θ

● P

● P

max is the maximum ambient temperature in °C,

A

is the package junction-to-ambient thermal resistance, in °C/W,

JA

max is the sum of P

D

max is the product of I

INT

max and P

INT

and VDD, expressed in Watts. This is the maximum chip

DD

max (PD max = P

I/O

INT

max + P

I/O

max),

internal power.

P

max represents the maximum power dissipation on output pins where:

I/O

P

max = Σ (VOL × IOL) + Σ((V

I/O

taking into account the actual V

OL

– VOH) × IOH),

DD

/ IOL and VOH / I

of the I/Os at low and high level in the

OH

application.

Table 51. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

LQFP 64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP 48 - 7 x 7 mm / 0.5 mm pitch

Θ

JA

Thermal resistance junction-ambient

VFQFPN 48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

VFQFPN 36 - 6 x 6 mm / 0.5 mm pitch

45

55

16

18

°C/W

6.2.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.

74/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Package characteristics

0

100

200

300

400

500

600

700

65 75 85 95 105 115

TA (°C)

P

D

(mW)

Suffix 6

6.2.2 Evaluating the maximum junction temperature for an application

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 52: Ordering information scheme.

Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).

The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F101xx junction temperature range.

Example: high-performance application

Assuming the following application conditions:

Maximum ambient temperature T
I

= 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low

DDmax

level with I
mode at low level with I

P

INTmax =

P

IOmax =

This gives: P

P

Dmax =

Thus: P

Dmax

= 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output

OL

= 20 mA, VOL= 1.3 V

OL

50 mA × 3.5 V= 175 mW

20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW

= 175 mW and P

INTmax

175 + 272 = 447 mW

= 447 mW

Using the values obtained in Tab le 5 1 T

– For LQFP64, 45 °C/W

T

= 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C

Jmax

This is within the junction temperature range of the STM32F101xx (–40 < T

= 82 °C (measured according to JESD51-2),

Amax

= 272 mW

IOmax

is calculated as follows:

Jmax

< 105 °C).

J

Figure 43. LQFP64 P

max vs. T

D

A

Doc ID 15058 Rev 5 75/79

Ordering information scheme STM32F101x4, STM32F101x6

7 Ordering information scheme

Table 52. Ordering information scheme

Example: STM32 F 101 C 4 T 6 A xxx

Device family

STM32 = ARM-based 32-bit microcontroller

Product type

F = general-purpose

Device subfamily

101 = access line

Pin count

T = 36 pins
C = 48 pins
R = 64 pins

Flash memory size

4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory

Package

T = LQFP
U = VFQFPN

Temperature range

6 = Industrial temperature range, –40 to 85 °C.

Internal code

“A” or blank

(1)

Options

xxx = programmed parts
TR = tape and real

1. For STM32F101x6 devices with a blank internal code, please refer to the STM32F103x6/8/B datasheet
available from the ST website: www.st.com.

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

76/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6 Revision history

8 Revision history

Table 53. Document revision history

Date Revision Changes

23-Sep-2008 1 Initial release.

I/O information clarified on page 1. Figure 7: Memory map modified.
In Table 4: Low-density STM32F101xx pin definitions: PB4, PB13, PB14,

PB15, PB3/TRACESWO moved from Default column to Remap column.

is not available in the offered packages: Figure 1: STM32F101xx

V

REF-

Low-density access line block diagram, Figure 10: Power supply scheme

and Figure 34: Power supply and reference decoupling updated,

07-Apr-2009 2

24-Sep-2009 3

Figure 30: Power supply and reference decoupling (V
to V

) removed.

DDA

Note modified in Table 12: Maximum current consumption in Run mode,

code with data processing running from Flash and Table 14: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 15, Figure 16 and Figure 17 show typical curves.

ACC

max values modified in Table 23: HSI oscillator characteristics.

HSI

Small text changes.

Note 5 updated and Note 4 added in Table 4: Low-density
STM32F101xx pin definitions.

RERINT

and T

V

voltage. Typical I

added to Table 11: Embedded internal reference

Coeff

DD_VBAT

value added in Table 15: Typical and maximum

current consumptions in Stop and Standby modes. Figure 14: Typical
current consumption on VBAT with RTC on versus temperature at
different VBAT values added.

f

min modified in Table 19: High-speed external user clock

HSE_ext

characteristics.

and CL2 replaced by C in Table 21: HSE 4-16 MHz oscillator

C

L1

characteristics and Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz), notes modified and moved below the tables.
Note 1 modified below Figure 20: Typical application with an 8 MHz

crystal.
Table 23: HSI oscillator characteristics modified. Conditions removed

from Table 25: Low-power mode wakeup timings.

Figure 27: Recommended NRST pin protection modified.

IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 48.

Jitter added to Table 26: PLL characteristics.

and R

C

ADC

R

max values modified in Table 43: RAIN max for fADC = 14 MHz.

AIN

parameters modified in Table 42: ADC characteristics.

AIN

Small text changes.

not connected

REF+

Doc ID 15058 Rev 5 77/79

Revision history STM32F101x4, STM32F101x6

Table 53. Document revision history (continued)

Date Revision Changes

Added VFQFPN48 package.
Updated note 2 below Table 39: I2C characteristics

20-May-2010 4

19-Apr-2011 5

Updated Figure 28: I2C bus AC waveforms and measurement circuit(1)
Updated Figure 27: Recommended NRST pin protection
Updated Section 5.3.12: I/O current injection characteristics

Updated footnotes below Table 5: Voltage characteristics on page 29
and Table 6: Current characteristics on page 30

Updated tw min in Table 19: High-speed external user clock

characteristics on page 42

Updated startup time in Table 22: LSE oscillator characteristics (fLSE =

32.768 kHz) on page 45

Added Section 5.3.12: I/O current injection characteristics
Updated Section 5.3.13: I/O port characteristics

78/79 Doc ID 15058 Rev 5

STM32F101x4, STM32F101x6

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