security supervisor with battery switchover
Features
■ STM1404 supports FIPS-140 security level 4
– Four high-impedance physical tamper
inputs
– Over/under operating voltage detector
– Security alarm (SAL
– Over/under operating temperature detector
– Over/under temperature thresholds are
customer-selectable and factory-
programmed
■ Supervisory functions
– Automatic battery switchover
–RST
output (open drain)
– Manual (push-button) reset input (MR
– Power-fail comparator (PFI/PFO
■ Vccsw (V
switch output)
CC
– Low when switched to V
– High when switched to V
indicator)
■ Battery low voltage detector (power-up)
) on tamper detection
)
)
CC
(BATT ON
BAT
STM1404
3 V FIPS-140
QFN16, 3 mm x 3 mm (Q)
■ Optional V
– (Available for STM1404A only)
■ Low battery supply current (5.3 µA typ)
■ Secure low profile 16-pin, 3 x 3 mm, QFN
package
■ RoHS compliance
– Lead-free components compliant with the
RoHS directive
(1.237 V)
REF
Table 1. Device summary
Standard
Device
STM1404A ✔✔✔ ✔✔ON Normal mode
STM1404B
STM1404C ✔✔✔ ✔Note
1. Reset output, power-fail comparator, battery low detection (SAL, RST, PFO, and BLD are open drain).
2. Normal mode: low when V
3. Contact local ST sales office for availability.
4. Pin 9 is the V
August 2008 Rev 5 1/36
supervisory
functions
(3)
✔✔✔ ✔Note
pin for STM1404A. It is the V
REF
Physical
tamper
(1)
inputs
is internally switched to VCC and high when V
OUT
Over/under
voltage
alarms
pin for STM1404B/C.
TPU
Over/under
temperature
alarms
V
REF
(1.237 V)
option
(4)
(4)
is internally switched to battery.
OUT
status,
V
OUT
during alarm
High-Z High
Ground High
Vccsw status,
during alarm
(2)
www.st.com
1
Contents STM1404
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 V
pin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OUT
1.1.1 STM1404A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2 STM1404B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.3 STM1404C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 SAL, security alarm output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 TP
2.3 TP
2.4 BLD, V
2.5 Active-low RST
2.6 MR
2.7 PFO
2.8 PFI, power-fail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9 V
2.10 V
2.11 V
2.12 V
2.13 V
2.14 V
, TP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1
, TP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
2.3.1 Vccsw, VCC switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
low voltage detect output (open drain) . . . . . . . . . . . . . . . . . . 13
BAT
output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
, manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
, power-fail output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
, reference voltage output (1.237, typ) . . . . . . . . . . . . . . . . . . . . . . . 14
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BAT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS
3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Negative-going V
transients and undershoot . . . . . . . . . . . . . . . . . . . . 17
CC
4 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/36
STM1404 Contents
4.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/36
List of tables STM1404
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Physical and environmental tamper detection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size mechanical data. . . . 32
Table 9. Ordering information scheme (see Figure 31 on page 34 for marking information) . . . . . . 33
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4/36
STM1404 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Tamper pin (TP
Figure 6. Tamper pin (TP
Figure 7. Tamper pin (TP
Figure 8. Tamper pin (TP
Figure 9. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. V
BAT
-to-V
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. V
threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PFI
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. Power-up t
Figure 16. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. PFI to PFO
Figure 18. RST
Figure 19. RST
output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22. V
to reset propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CC
Figure 23. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. MR
timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 26. STM1404 switchover diagram, condition A (V
Figure 27. STM1404 switchover diagram, condition B (V
Figure 28. Temperature hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 31
Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 32
Figure 31. Topside marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
or TP3) normally high (NH) external hookup (switch closed) . . . . . . . . . 10
1
or TP3) normally high (NH) external hookup (switch open). . . . . . . . . . . 10
1
or TP4) normally low (NL) external hookup (switch closed) . . . . . . . . . . 10
2
or TP4) normally low (NL) external hookup (switch open). . . . . . . . . . . . 11
2
on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OUt
vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
rec
propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
< VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 26
BAT
> VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 26
BAT
5/36
Description STM1404
1 Description
The STM1404 family of security supervisors are a low power family of intrusion (tamper)
detection chips targeted at manufacturers of POS terminals and other systems, to enable
them to meet physical and/or environmental intrusion monitoring requirements as
mandated by various standards, such as Federal Information Processing Standards (FIPS)
Pub 140 entitled “Security Requirements for Cryptographic Modules,” published by the
National Institute of Standards and Technology, U.S. Department of Commerce), EMVCo,
ISO, ZKA, and VISA PED.
STM1404 will target the highest security level 4 and include both physical and
environmental (voltage and temperature) monitoring.
The STM1404 include automatic battery switchover, RST
(push-button) reset input (MR
environmental tamper detect/security alarm, and battery low voltage detect features.
The STM1404A also offers a V
is V
1.1 V
The STM1404 is available in three versions, corresponding to three modes of the V
(supply voltage out), when the SAL
detection:
(internally switched VCC or V
TPU
pin modes
OUT
1.1.1 STM1404A
V
stays ON (at VCC or V
OUT
1.1.2 STM1404B
V
is set to High-Z when SAL is driven low (activated).
OUT
1.1.3 STM1404C
V
is driven to ground when SAL is activated (may be used when V
OUT
directly to the V
All variants (see Table 1: Device summary) are pin-compatible and available in a security-
friendly, low profile, 16-pin QFN package.
output (open drain), manual
), power-fail comparator (PFI/PFO), physical and/or
(1.237V) as an option on pin 9. On STM1404B/C this pin
REF
) when SAL is driven low (activated).
BAT
pin of the external SRAM that holds the cryptographic codes).
CC
).
BAT
(security alarm) is asserted (active-low) upon tamper
OUT
OUT
is connected
pin
6/36
STM1404 Description
Figure 1. Logic diagram
V
REF
(3)
or
V
BLD
V
TPU
(1)
BAT
V
CC
(2)
V
CCSW
MR
STM1404
PFI
TP1 (NH)
TP
TP
(NH)
TP
3
4
(NL)
1. V
2. Normal mode: low when V
3. SAL
Table 2. Signal names
only for STM1404A; V
REF
battery.
, RST, PFO, and BLD are open drain.
(1)
Vccsw
TPU
OUT
MR
2
(NL)
for STM1404B/C.
is internally switched to VCC and High when V
VCC switch output
Manual (push-button) reset input
PFI Power-fail input
- TP
TP
1
4
V
OUT
(2)
RST
(2)
PFO
(2)
SAL
(2)
BLD
(3)
V
REF
(3)
V
TPU
V
BAT
V
CC
V
SS
1. Normal mode: low when V
battery.
2. SAL, RST, PFO, and BLD are open drain.
3. V
only for STM1404A; V
REF
is internally switched to VCC and high when V
OUT
TPU
Independent physical tamper detect pins 1 through 4
Supply voltage output
Active-low reset output
Power-fail output
Security alarm output
Battery low voltage detect
1.237 V reference voltage
Tamper pull-up (VCC or V
Backup supply voltage
Supply voltage
Ground
for STM1404B/C.
Note: See Section 2: Pin descriptions on page 11 for details.
V
OUT
(3)
RST
(3)
PFO
(3)
SAL
V
SS
AI09682a
is internally switched to
OUT
)
BAT
is internally switched to
OUT
7/36
Description STM1404
Figure 2. QFN16 connections
V
CCSW
14
(1)
V
CC
13
V
12
OUT
RST
(2)
BLD
16
1
(2)
PFI
15
(2)
SS
2
3
4
5
TP
(NH)
11
10
8
76
TP
(NH)
TP
3
(NL)
TP
1
2
(NL)
MR
SAL
V
Note: See Section 2: Pin descriptions on page 11 for details.
1. Normal mode: low when V
battery.
, RST, PFO, and BLD are open drain.
2. SAL
3. V
only for STM1404A; V
REF
is internally switched to VCC and high when V
OUT
for STM1404B/C.
TPU
Figure 3. Block diagram
V
CC
(1,2)
MR
PFI
BAT54J
V
BAT
(1)
V
INT
COMPARE
V
SO
COMPARE
V
RST
COMPARE
V
PFI
V
BAT
(2)
PFO
V
REF
or
9
V
TPU
(3)
4
AI09683
is internally switched to
OUT
V
OUT
V
CCSW
t
rec
Generator
RST
PFO
(3)
(3)
V
DET
V
HV
V
TP1 (NH)
TP2 (NL)
TP3 (NH)
TP4 (NL)
LV
1. Required for battery-reverse charging protection
2. User supplied
3. Open drain
4. V
only for STM1404A; V
REF
for STM1404B/C
TPU
8/36
COMPARE @
POWER-UP
1.237V V
REF
Generator
COMPARE
COMPARE
High Temp.
Sense
TA > T
H
Low Temp.
Sense
TA < T
L
V
V
AI09684a
BLD
SAL
TPU
REF
(3)
(4)
(4)
(3)
STM1404 Description
Figure 4. Hardware hookup
(1)
Unregulated
Voltage
Regulator
V
IN
V
CC
0.1μF
V
CC
V
CCSW
STM1404
V
OUT
V
CC
V
CC
(2)
C
LPSRAM
R1
R2
(e.g., Switches, Wire Mesh)
1. Normal mode: low when V
battery.
PFI
Push-Button
BAT54J
1.0μF
From Actuator Device
is internally switched to VCC and high when V
OUT
MR
(4)
V
BAT
TP
1
TP
2
TP
3
TP
4
(3)
PFO
(3)
RST
(3)
BLD
(3)
SAL
(5)
V
REF
or
V
TPU
To Microprocessor NMI
To Microprocessor Reset
To Microprocessor
To ADC
To Physical Tamper Pins TP
is internally switched to
OUT
X
AI09690a
2. Capacitor (C) is typically ≥ 10 µF.
3. Open drain
4. Diode is required for battery reverse charge protection.
5. V
only for STM1404A; V
REF
for STM1404B/C
TPU
Figure 5. Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch
closed)
V
(STM1404A)
OUT
V
Switch Normally Closed;
Tamper Detection on Open
or
(STM1404B/C)
TPU
TP1 or TP
(1)
R
AI09698a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
9/36
3
Description STM1404
Figure 6. Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch
open)
V
(STM1404A)
OUT
V
or
(STM1404B/C)
TPU
(1)
R
Tamper Detection when Closed
Switch Normally Open
TP1 or TP
3
AI10461a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 7. Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch
closed)
V
(STM1404A)
OUT
V
Switch Normally Closed;
Tamper Detection on Open
or
(STM1404B/C)
TPU
(1)
R
TP2 or TP
4
AI09699a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 8. Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch open)
Switch Normally Open;
Tamper Detection when Closed
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
10/36
V
OUT
V
(STM1404B/C)
TPU
(STM1404A)
or
(1)
R
TP2 or TP
AI10462a
4
STM1404 Pin descriptions
2 Pin descriptions
See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals
connected to this device.
2.1 SAL, security alarm output (open drain)
This signal can be generated when ANY of the following conditions occur:
● V
● V
● When any of the physical tamper inputs, TP
● T
● T
> VHV, where VHV = upper voltage trip limit (4.2 V typ); and where V
INT
V
;
BAT
< VLV, where VLV = lower voltage trip limit (2.0 V typ); and where V
INT
V
; or
BAT
to TP4, change from their normal states to
1
= VCC or
INT
= VCC or
INT
the opposite (i.e., intrusion of a physical enclosure).
> TH, where TH is an upper temperature trip limit specified by the customer (+80°C,
A
+85°C, and +95°C), factory-programmed (STM1404 only);
< TL, where TL is a lower temperature trip limit specified by the customer (–25°C or
A
–35°C), factory-programmed (STM1404 only);
Note: 1 The default state of the SAL
output during initial power-up is undetermined.
2 The alarm function will operate either with V
from V
2.2 TP1, TP
CC
to V
3
BAT
.
Physical tamper detect pin set normally to high (NH). They are connected externally through
a closed switch or a high-impedance resistor to V
the case of STM1404B/C. A tamper condition will be detected when the input pin is pulled
low (see Figure 5 and Figure 6 on page 10). If not used, tie the pin to V
or V
2.3 TP2, TP
(for STM1404B/C).
TPU
4
Physical tamper detect pin set normally to low (NL). They are connected externally through
a high-impedance resistor or a closed switch to V
when the input pin is pulled high (see Figure 7 and Figure 8 on page 10). If not used, tie the
pin to V
SS
.
2.3.1 Vccsw, VCC switch output
This output is low when V
V
; in this mode it may be used to turn on an external p-channel MOSFET switch which
CC
can source an external device directly from V
the STM1404).
(see Section 2.10: V
OUT
on or when the part is internally switched
CC
(in the case of STM1404A) or V
OUT
(for STM1404A)
OUT
. A tamper condition will be detected
SS
on page 13) is internally switched to
OUT
for currents greater than 80 mA (bypassing
CC
TPU
(in
This pin goes high when V
“BATTERY ON” indicator.
is internally switched to V
OUT
11/36
and may be used as a
BAT
Pin descriptions STM1404
If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows:
1. STM1404A (V
remains ON when SAL is active-low): Vccsw pin will continue to
OUT
operate in normal mode;
2. STM1404B (V
is taken to High-Z when SAL is active-low): Vccsw pin will be set to
OUT
high when this occurs; and
3. STM1404C (V
is driven to ground when SAL is active-low): Vccsw pin will be set to
OUT
high when this occurs.
2.4 BLD, V
low voltage detect output (open drain)
BAT
This is an internally loaded test of the battery, activated only during a power-up sequence to
insure that the battery is good either prior to or after encapsulation of the module. There are
three customer options for V
● 2.3 V (2.5 V – external diode drop of about 0.2 V) for a 3 V lithium cell
● 2.5 V (2.7 V – 0.2 V) for a 3 V lithium cell or
● 3.2 V (3.4 V – 0.2 V) for a 3.68 V lithium “AA” battery
DET
:
This output pin will go active-low when it detects a voltage on the V
will be released when V
drops below V
CC
RST
.
2.5 Active-low RST output (open drain)
Goes low and stays low when VCC drops below V
customer), or when MR
above V
and MR goes from low to high.
RST
is logic low. It remains low for t
RST
2.6 MR, manual reset input
A logic low on MR asserts the RST output. The RST output remains asserted as long as MR
is low and for t
(typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground
with a switch. Leave it open if unused.
after MR returns to high. This active low input has an internal 40 kΩ
rec
pin below V
BAT
DET
. BLD
(Reset Threshold selected by the
(200ms, typical) AFTER VCC rises
rec
2.7 PFO, power-fail output (open drain)
When PFI is less than V
(battery switchover threshold ~ 2.4 V), PFO
this pin open if unused.
(power-fail input threshold voltage) or VCC falls below VSW
PFI
goes low, otherwise, PFO remains high. Leave
2.8 PFI, power-fail input
When PFI is less than V
active-low. If this function is unused, connect this pin to V
12/36
, or when VCC falls below VSW (see PFO, above), PFO goes
PFI
SS
.
STM1404 Pin descriptions
2.9 V
This is valid only when VCC is between 2.4 V and 3.6 V. When VCC falls below 2.4 V (VSW),
V
available on the STM1404A. On the STM1404B/C, this pin is V
or V
2.10 V
This is the supply voltage output. When VCC rises above VSO (battery backup switchover
voltage), V
V
(~2.4 V), or V
connected externally to a capacitor that will retain a charge for a period of time, in case an
intruder forces V
terminal of the battery to the V
capacitor. Three variations of parts will be offered with the following options:
1. STM1404A: V
2. STM1404B: V
3. STM1404C: V
, reference voltage output (1.237, typ)
REF
is pulled to ground with an internal 100 kΩ resistor. This is an optional feature
REF
). If unused, this pin should float.
BAT
(internally switched VCC
TPU
OUT
is supplied from VCC. In this condition, V
OUT
through a p-channel MOSFET switch. When VCC falls below the lower value of VSW
CC
BAT
, V
is supplied from V
OUT
CC
or V
OUT
to ground. The rectifying diode connected from the positive
BAT
pin of the STM1404 will prevent discharge of the
BAT
remains ON when SAL is active-low; Vccsw pin will continue to
. It is recommended that the V
BAT
operate in normal mode (see Section 2.3.1: Vccsw, V
is taken to High-Z when SAL is active-low; Vccsw pin will be set to
OUT
high when this occurs; and
is driven to ground when SAL is active-low; Vccsw pin will be set to
OUT
high when this occurs.
may be connected externally to
OUT
pin be
OUT
switch output on page 11);
CC
2.11 V
For STM1404B and STM1404C, this pin provides pull-up voltage for the physical tamper
pins (TP1-4). This pin is not to be used as voltage supply source for any other purpose.
Note: V
2.12 V
This is the supply voltage (2.2 V to 3.6 V).
2.13 V
This is the secondary (backup battery) supply voltage. The pin is connected to the positive
terminal of the battery with a rectifying diode like the BAT54J from STMicroelectronics for
reverse charge protection. Voltage at this pin, after diode rectification, will be approximately
0.2 V less than the battery voltage, and will depend on the type of battery used as well as
the I
V
2.14 V
Ground, VSS, is the reference for the power supply. It must be connected to system ground.
TPU
is the internally switched supply voltage from either the VCC pin or the V
TPU
CC
BAT
being drawn. (A capacitor of at least 1.0 µF connected between the V
BAT
is required.) If no battery is used, connect the V
SS
pin to the VCC pin.
BAT
SS
pin.
BAT
pin and
BAT
13/36
Operation STM1404
3 Operation
3.1 Reset input
The STM1404 security supervisor asserts a reset signal to the MCU whenever VCC goes
below the reset threshold (V
RST
is guaranteed to be a logic low for 0 V < VCC < V
a backup battery, RST
is guaranteed valid down to VCC =1V.
), or when the push-button reset input (MR) is taken low.
RST
RST
if V
is greater than 1 V. Without
BAT
During power-up, once V
the reset time-out period, t
If V
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
CC
low for at least the reset time-out period (t
exceeds the reset threshold an internal timer keeps RST low for
CC
. After this interval RST returns high.
rec
rec
the internal timer clears. The reset timer starts when V
3.2 Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure 25 on page 24) after it returns high. The MR
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR
to ground to create a manual reset function; external debounce circuitry is not required.
If MR
is driven from long cables or the device is used in a noisy environment, connect a
0.1µF capacitor from MR
tied to V
when not used.
CC
to VSS to provide additional noise immunity. MR may float, or be
3.3 Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through V
automatically switch the SRAM to the backup supply when V
Note: If backup battery is not used, connect both V
This family of security supervisors does not always connect V
greater than V
(~2.4 V) or V
BAT
battery) to have a higher voltage than V
Assuming that V
before V
gets too close to the 2.0 V minimum required to reliably retain data in most
OUT
external SRAMs. When V
point. V
is connected to VCC through a 3 Ω PMOS power switch.
OUT
Note: The backup battery may be removed while V
decoupled (0.1 µF typ), without danger of triggering a reset.
. With a backup battery installed with voltage V
OUT
. V
CC
connects to V
BAT
(through a 100Ω switch) when VCC is below VSW
OUT
(whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V
.
CC
> 2.0 V, switchover at VSO ensures that battery backup mode is entered
BAT
recovers, hysteresis is used to avoid oscillation around the VSO
CC
). Any time VCC goes below the reset threshold
returns above the reset threshold.
CC
(see
rec
input has an internal 40 kΩ pull-up
, the devices
BAT
falls.
CC
and V
BAT
is valid, assuming V
CC
OUT
to VCC.
BAT
to V
OUT
is adequately
BAT
when V
BAT
is
14/36
STM1404 Operation
Table 3. I/O status in battery backup
Pin Status
V
OUT
V
CC
PFI Disabled
PFO
MR
RST
V
BAT
Vccsw Logic high
V
REF
BLD
V
TPU
Connected to V
Disconnected from V
Logic low
Disabled
Logic low
Connected to V
Pulled to VSS below 2.4 V (VSW)
Logic high
Connected to V
through internal switch
BAT
OUT
OUT
through an internal switch
BAT
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the V
output (PFO
comparator). If PFI is less than the power-fail threshold (V
RST
) will go low. This function is intended for use as an undervoltage detector to
), the power-fail
PFI
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 4 on page 9) to either the unregulated DC input (if it is available) or the
regulated output of the V
voltage at PFI falls below V
regulator. The voltage divider can be set up such that the
CC
several milliseconds before the regulated VCC input to the
PFI
STM1404 or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator is turned off and PFO
low (see Figure 9 on page 16). This occurs after V
power returns, the power-fail comparator is enabled and PFO
is unused, PFI should be connected to V
connected to MR
so that a low voltage on PFI will generate a reset output.
3.4 Applications information
These supervisor circuits are not short-circuit protected. Shorting V
excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both V
the device as possible.
CC
and V
BAT
goes (or remains)
drops below VSW (~2.4 V). When
CC
follows PFI. If the comparator
and PFO left unconnected. PFO may be
SS
to ground -
OUT
pins to ground by placing 0.1 µF capacitors as close to
15/36
Operation STM1404
Figure 9. Power-fail comparator waveform
V
CC
V
RST
VSW (2.4V)
PFO
trec
PFO follows PFI
RST
PFO follows PFI
3.5 Negative-going VCC transients and undershoot
The STM1404 devices are relatively immune to negative-going VCC transients (glitches).
Figure 23 on page 22 was generated using a negative pulse applied to V
+ 0.3 V and ending below the reset threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum pulse width a negative V
without causing a reset pulse. As the magnitude of the transient increases (further below the
threshold), the maximum allowable pulse width decreases. Any combination of duration and
overdrive which lies under the curve will NOT generate a reset signal. Typically, a V
transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a
reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the V
provides additional transient immunity (see Figure 10).
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
that drive it to values below VSS by as much as
CC
to VSS (cathode connected to VCC, anode to VSS).
CC
AI08861a
, starting at V
CC
transient can have
CC
CC
pin
CC
RST
Figure 10. Supply voltage protection
V
CC
0.1μF DEVICE
16/36
V
CC
V
SS
AI02169
STM1404 Tamper detection
4 Tamper detection
4.1 Physical
There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high
(NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see
Table 7 on page 29). These inputs can be connected externally to several types of actuator
devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its
state to change will trigger the security alarm (SAL
tamper condition no longer exists, the SAL
TP
and TP3 are set normally to high (NH). They are connected externally through a closed
1
switch or a high-impedance resistor to V
V
(in the case of STM1404B/C), A tamper condition will be detected when the input pin
TPU
will return to its normal high state.
OUT
is pulled low (see Figure 5 and Figure 6 on page 10). If not used, tie the pin to V
TP
and TP4 are set normally to low (NL). They are connected externally through a high-
2
impedance resistor or a closed switch to V
SS
input pin is pulled high (see Figure 7 and Figure 8 on page 10). If not used, tie the pin to
V
.
SS
) and drive it to active-low. Once the
(in the case of STM1404A or STM1404A) or
or V
OUT
TPU
. A tamper condition will be detected when the
.
4.2 Supply voltage
The internally switched supply voltage, V
monitored. If V
should exceed the over voltage trip point, VHV (set at 4.2V, typical), or
INT
should go below the under voltage trip point, V
active-low. Once the tamper condition no longer exists, the SAL
high state.
(either VCC input or V
INT
4.3 Temperature
The STM1404 has a built-in, bandgap-based sensor to monitor the temperature. If a preset
(customer-selectable, factory-programmed) over-temperature trip point (T
temperature trip point (T
When no tamper condition exists, SAL
page 11).
When a tamper is detected, the SAL
V
can be driven to one of three states, depending on which variant of STM1404 is being
OUT
used (see Table 1 on page 1):
● ON
● High-Z or
● Ground (V
SS
)
Note: The STM1404 must be initially powered above V
For example, if the battery is on while V
V
rises above V
CC
on battery or V
RST
. This is done to avoid false alarms when the device goes from no power to
CC
its operational state.
) is exceeded, the SAL is asserted low.
L
is normally high (see Section 2: Pin descriptions on
is activated (driven low), independent of the part type.
= 0 V, no alarm condition can be detected until
(and t
expires). From this point on, alarms can be detected either
rec
CC
input) is continuously
BAT
(set at 2.0v, typical). SAL will be driven
LV
pin will return to its normal
) or under-
H
to enable the tamper detection alarms.
RST
17/36
Typical operating characteristics STM1404
5 Typical operating characteristics
Note: Typical values are at TA = 25°C.
Figure 11. V
-to-V
BAT
220
200
180
160
ON-RESISTANCE [Ω]
140
OUT
120
- to - V
100
BAT
–60 –40 –20 0 20 40 60 80 100 120 140
V
on-resistance vs. temperature
OUt
VCC = 0V
V
= 2V
BAT
TEMPERATURE [°C]
V
BAT
= 3V
Figure 12. Supply current vs. temperature (no load)
30
25
20
V
= 3.3V
BAT
AI09691
15
Supply Current [µA]
10
5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100
TEMPERATURE [°C]
2.5V
3.3V
3.6V
AI09692
18/36
STM1404 Typical operating characteristics
Figure 13. V
threshold vs. temperature
PFI
1.255
1.250
1.245
1.240
1.235
THRESHOLD [V]
PFI
V
1.230
1.225
–50 –30 –10 10 30 50 70 90 110 130
V
= 3.3V
CC
V
= 2.5V
CC
V
= 3.0V
BAT
TEMPERATURE [°C]
Figure 14. Reset comparator propagation delay vs. temperature
24
22
20
18
16
14
12
PROPAGATION DELAY [µs]
10
–60 –40 –20 0 20 40 60 80 100
TEMPERATURE [°C]
V
= 3.0V
BAT
100mV OVERDRIVE
AI09693
AI09143
Figure 15. Power-up t
215
24
22
210
20
18
205
[ms]
16
rec
t
14
200
12
PROPAGATION DELAY [µs]
10
–60 –40 –20 0 20 40 60 80 100
195
–50 –30 –10 10 30 50 70 90 110 130
vs. temperature
rec
V
BAT
100mV OVERDRIVE
TEMPERATURE [°C]
= 3.0V
Figure 16. Normalized reset threshold vs. temperature
1.002
1.000
0.998
[V]
0.996
V
= 3.0V
0.994
–60 –40 –20 0 20 40 60 80 100 120 140
NORMALIZED RESET THRESHOLD
BAT
TEMPERATURE [°C]
AI09143
AI09145
19/36
Typical operating characteristics STM1404
Figure 17. PFI to PFO propagation delay vs. temperature
9
8
7
6
5
4
3
PROPAGATION DELAY [µs]
2
1
0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE [°C]
AI09148
Figure 18. RST
3.5
3.0
2.5
2.0
1.5
1.0
RST OUTPUT VOLTAGE [V]
0.5
0
Figure 19. RST
4.0
3.0
output voltage vs. supply voltage
V
CC
V
RST
500 ms/div
response time (assertion)
AI09149b
V
CC
2.0
LEVEL [V]
CC
V
1.0
0.0
20/36
2 µs/div
V
RST
AI09151b
STM1404 Typical operating characteristics
Figure 20. Power-fail comparator response time (assertion)
4.0
3.0
PFO
2.0
LEVEL [V]
PFO
V
1.0
0.0
PFI
2µs/div
Figure 21. Power-fail comparator response time (de-assertion)
4.0
3.5
3.0
2.5
2.0
LEVEL (V)
1.5
PFO
V
1.0
0.5
PFI
PFO
1.45
1.40
1.35
1.30
1.25
1.20
1.15
AI09153b
1.45
1.40
1.35
1.30
1.25
1.20
LEVEL [V]
PFI
V
LEVEL (V)
PFI
V
0.0
2 µs/div
1.15
AI09154
21/36
Typical operating characteristics STM1404
Figure 22. VCC to reset propagation delay vs. temperature
60
50
40
30
10V/ms
1V/ms
0.25V/ms
20
10
PROPAGATION DELAY [µs]
0
–60 –40 –20 0 20 40 60 80 100
TEMPERATURE [°C]
AI09155
Figure 23. Maximum transient duration vs. reset threshold overdrive
250
200
150
100
50
TRANSIENT DURATION [µs]
0
1 10 100 1000 10000
RESET COMPARATOR OVERDRIVE, V
– VCC [mV]
RST
AI09156
22/36
STM1404 Maximum ratings
6 Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
T
STG
T
SLD
V
IO
V
CC/VBAT
I
O
P
D
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
Storage temperature (VCC off, V
(1)
Lead solder temperature for 10 seconds 260 °C
off) –55 to 150 °C
BAT
Input or output voltage –0.3 to VCC +0.3 V
Supply voltage –0.3 to 4.5 V
Output current 20 mA
Power dissipation 320 mW
23/36
DC and AC parameters STM1404
7 DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5. Operating and AC measurement conditions
Parameter STM1404 Unit
V
CC/VBAT
Ambient operating temperature (T
supply voltage 2.2 to 3.6 V
)–40 to 85°C
A
Input rise and fall times ≤ 5ns
Input pulse voltages 0.2 to 0.8V
Input and output timing ref. voltages 0.3 to 0.7V
CC
CC
V
V
Figure 24. AC testing input/output waveforms
0.8V
Figure 25. MR
MR
RST
CC
0.2V
CC
timing waveform
tMLRL
tMLMH
trec
0.7V
0.3V
AI02568
CC
CC
AI09694
24/36
STM1404 DC and AC parameters
Figure 26. STM1404 switchover diagram, condition A (V
VCC = 3.3V
V
RST
VSW = 2.4V
V
BAT
V
– 75mV
BAT
Figure 27. STM1404 switchover diagram, condition B (V
VCC = 3.3V
V
BAT
VSW = 2.4V
Table 6. DC and AC characteristics
Sym
V
,
CC
(2)
V
BAT
I
CC
(3)
I
BAT
Alter-
native
Description Test condition
(1)
Operating voltage TA = –40 to +85°C 2.2 3.6 V
VCC supply current
(STM1404A)
Typ @ 3.3 V, 25°C
supply current
V
CC
(STM1404B,C)
supply current in
V
CC
battery backup mode
V
supply current in
BAT
battery backup mode
Excluding I
(V
= 2.3 V, VCC = 2.0
BAT
V, M R = VCC)
Excluding I
(V
BAT
I
OUT1
= 3.6 V)
= 5 mA
OUT
OUT
(4)
(VCC > VSW)
< VSW)
BAT
V
OUT
V
– 35mV
BAT
AI10463
> VSW)
BAT
V
OUT
VSW + 40mV
AI10464
Min Typ Max Unit
50 65 µA
35 50 µA
25 35 µA
5.3 8.0 µA
–
V
V
CC
– 0.03
CC
0.015
V
V
V
V
OUT1
OUT2
TPU1
V
voltage (active)
OUT
V
voltage
OUT
(battery
backup)
Internal switched
supply voltage (active)
I
= 80 mA
OUT1
(V
> VSW)
CC
I
= 250 µA,
OUT1
V
> V
CC
= 250 µA,
I
OUT2
V
= 2.2 V
BAT
I
= 1 mA,
OUT2
V
= 2.2 V
BAT
SOURCE
= 5 mA
I
(VCC > VSW)
VCC – 0.3 VCC – 0.15 V
SW
(4)
VCC –
0.0015
V
– 0.1 V
BAT
– 0.3 V
V
CC
VCC –
0.0006
– 0.04 V
BAT
V
– 0.16 V
BAT
V
25/36
DC and AC parameters STM1404
Table 6. DC and AC characteristics (continued)
Sym
V
TPU2
I
V
V
V
V
I
LO
LI
IH
IL
OL
OL
Alter-
native
= 1 mA
= V
IN
= V
IN
CC
(max),
CC
CC
(1)
(5)
Min Typ Max Unit
V
– 0.10 V
BAT
–25 2 +25 nA
–1 +1 µA
–1 +1 µA
0.7V
CC
CC
0.3 V
V
V
Description Test condition
Internal switched
supply voltage (battery
backup)
Input leakage current
(MR)
Input leakage current
(PFI)
Input leakage current
(TP1-TP4)
I
SOURCE
(V
= 2.2 V)
BAT
= 0 V; VCC = 3V 20 75 350 µA
MR
0 V = V
0 V = V
Output leakage current 0 V = VIN = V
Input high voltage (MR)
(max) < VCC < 3.6 V
V
Input low voltage (MR)0.3V
Output low voltage
(PFO, RST, Vccsw,
, BLD)
SAL
RST
V
CC
I
SINK
= V
RST
= 3.2 mA
IOL = 40 µA; VCC = 1.0 V;
Output low voltage
(RST)
= VCC;
V
BAT
TA = 0°C to 85°C
I
= 200 µA;
OL
VCC = 1.2 V; V
BAT
= V
CC
0.3 V
0.3 V
26/36
STM1404 DC and AC parameters
Table 6. DC and AC characteristics (continued)
OHB
Alter-
native
Description Test condition
VOH battery backup
(Vccsw)
Sym
V
Pull-up supply voltage
(open drain)
Power-fail comparator
V
PFI
PFI input threshold PFI falling (VCC < 3.6 V) 1.212 1.237 1.262 V
PFI hysteresis PFI rising (V
t
PFD
PFI to PFO
propagation delay
Battery switchover
Battery backup
switchover voltage
V
SO
Hysteresis 40 mV
Battery low voltage detect
(1)
I
SOURCE
RST
= 100 µA 0.8V
, SAL, BLD, PFO 3.6 V
< 3.6 V) 10 20 mV
CC
Min Typ Max Unit
BAT
V
2µs
> V
V
BAT
BAT
BAT
BAT
< V
> V
< V
SW
SW
SW
SW
Power-
down
(6)(7)
V
V
Power-up
V
V
SW
V
SW
V
BAT
V
SW
V
BAT
2.4 V
V
V
V
V
V
DET
Battery detect
threshold
Voltage reference (option for STM1404A)
Voltage reference (see
Section 2.9: V
V
REF
reference voltage
REF
,
output (1.237, typ) on
page 13)
I
REF+
I
REF–
V
n
Source current
Sink current 10 13 µA
Output voltage noise f = 100 Hz to 100 kH 10-100 µV
M 2.25 2.30 2.34 V
On power-
up only
N 2.45 2.50 2.55 V
O 3.14 3.20 3.26 V
(8)
0°C to 85°C 1.212 1.237 1.262 V
–40° to 0°C 1.200 1.237 1.274 V
0°C to 85°C 15 25 µA
–40° to 0°C 10 15 µA
rms
27/36
DC and AC parameters STM1404
Table 6. DC and AC characteristics (continued)
Sym
Alter-
native
Description Test condition
(1)
Min Typ Max Unit
Reset thresholds
VCC falling 3.00 3.075 3.15 V
T
rising 3.00 3.085 3.17 V
V
CC
V
falling 2.85 2.925 3.00 V
(9)
V
RST
Reset threshold
S
R
t
rec
RST pulse width 140 200 280 ms
CC
rising 2.85 2.935 3.02 V
V
CC
V
falling 2.55 2.625 2.70 V
CC
V
rising 2.55 2.635 2.72 V
CC
Push-button reset input
t
MLMHtMR
t
MLRLtMRD
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = V
noted); typical values are for 3.3 V and 25°C.
supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at
2. V
CC
V
= 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). V
BAT
pin.
3. Tested at V
4. Guaranteed by design.
5. The leakage current measured on the RST
impedance).
6. When V
7. When V
8. Maximum external capacitive load on V
9. The reset threshold tolerance is wider for V
internal oscillation.
BAT
> VCC > VSW, V
BAT
> VCC > V
SW
MR pulse width 100 ns
MR to RST output
delay
(max) to 3.6 V; and V
RST
BAT
= 3.6 V, and VCC = 0 V.
, SAL, PFO, and BLD pins are tested with the output not asserted (output high
remains connected to VCC until VCC drops below VSW.
OUT
, V
BAT
remains connected to VCC until VCC drops below the battery voltage (V
OUT
pin cannot exceed 1 nF.
REF
rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
CC
60 500 ns
= 2.8 V (except where
BAT
is voltage measured at the
) – 75 mV.
BAT
28/36
STM1404 DC and AC parameters
Table 7. Physical and environmental tamper detection levels
Sym Parameter
V
HV
V
LV
V
HTP
V
LT P
T
H
T
L
T
HYST
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VLV to VHV (except where noted). All physical and
environmental tamper functions are operational across the full temperature alarm range for STM1404.
2. In the case of STM1404A, physical tamper input pins (TP
C, TPX are referenced to V
3. V
CC
Overvoltage trip level 4.0 4.2 4.4 V
Undervoltage trip level 1.9 2.0 2.1 V
SAL
propagation delay time
(after over/under voltage detection)
Trip point for NH physical tamper
input pins (TP1 or TP3)
Trip point for NL physical tamper
input pins (TP
propagation delay time
SAL
or TP4)
2
(after physical tamper pin
detection)
Physical tamper input (TP
) glitch
X
immunity
Factory-programmed I
Temperature hysteresis 10 °C
pin (pin 9).
TPU
= V
(max) to 3.6 V
RST
VHV + 200 mV or
(3)
Test
conditions
(1)
VLV – 200 mV
V
=
HTP
V
OUT/VTPU
= V
V
LT P
SS
VDD = 3.6
= 0 mA
OUT
) are referenced to V
X
Min Typ Max Unit
25 50 µs
V
OUT
- 1.3
(2)
V
OUT
- 0.3
(2)
0.3 1.0 V
;
30 50 µs
15 µs
–5 80, 85, 95 +5 °C
–5 –25, –35 +5 °C
(pin 12). In the case of STM1404B or
OUT
V
Figure 28. Temperature hysteresis
T
H
T
HYST(High)
Temperature
T
HYST(Low)
T
L
SAL
AI11147b
29/36
Package mechanical data STM1404
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
Note: Drawing is not to scale.
ddd
E2
A3
C
b
L
K
D2
e
1
2
3
A1
K
QFN16-A
A
Ch
30/36
STM1404 Package mechanical data
Table 8. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size mechanical
data
mm inches
Symb
Typ Min Max Typ Min Max
A 0.90 0.80 1.00 0.035 0.032 0.039
A1 0.02 0.00 0.05 0.001 0.000 0.002
A3 0.20 – – 0.008 – –
b 0.25 0.18 0.30 0.010 0.007 0.012
D 3.00 2.90 3.10 0.118 0.114 0.122
D2 1.70 1.55 1.80 0.067 0.061 0.071
E 3.00 2.90 3.10 0.118 0.114 0.122
E2 1.70 1.55 1.80 0.067 0.061 0.071
e0.50– –0.020– –
K 0.20 – – 0.008 – –
L 0.40 0.30 0.50 0.016 0.012 0.020
ddd – 0.08 – – 0.003 –
Ch –0.33– –0.013–
N16 16
Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended
footprint
Note: Substrate pad should be tied to V
3.55
AI09126
.
SS
1.60
2.0
0.28
31/36
Part numbering STM1404
9 Part numbering
Table 9. Ordering information scheme (see Figure 31 on page 33 for marking information)
Example: STM1404 A T M D Q 6 F
Device type
STM1404: over/under temperature detect
V
status (SAL = active-low)
OUT
A: V
B
C: V
Reset threshold voltage
T: V
S: V
R: V
= ON; Vccsw = normal mode
OUT
(1)
: V
= High-Z; Vccsw = high
OUT
= ground; Vccsw = high
OUT
= 3.00 V to 3.15 V
RST
= 2.85 V to 3.00 V
RST
= 2.55 V to 2.70 V
RST
Battery low voltage detect threshold (V
M: V
N: V
O: V
= 2.3 V (typ)
DET
= 2.5 V (typ)
DET
= 3.2 V (typ)
DET
DET
)
Under (TL)/over (TH) temperature alarm thresholds (STM1404 only)
B: –25/+80°C H: –35/+80°C
C: –25/+85°C I: –35/+85°C
D: –25/+95°C J: –35/+95°C
Package
Q = QFN16 (3 mm x 3 mm)
Temperature range
6 = –40 to 85°C
Shipping method
®
F = ECOPACK
1. Contact local ST sales office for availability.
package, tape & reel
For other options, or for more information on any aspect of this device, please contact the ST sales office
nearest you.
32/36
STM1404 Part numbering
Figure 31. Topside marking information
04
(1)
XXXX
(2)
YWW
AI12218
1. Options codes:
X = A, B, or C (for V
X = T, S, or R (for reset threshold)
X = M, N, or O (for battery low voltage detect threshold)
X = B, C, D, H, I, or J (for temperature alarm threshold)
2. Traceability codes
Y = Year
WW = Work Week
OUT
)
33/36
Revision history STM1404
10 Revision history
Table 10. Document revision history
Date Revision Changes
11-Oct-2004 1 First edition
26-Nov-2004 1.1
22-Dec-2004 1.2 Update characteristics (Figure 4, Tables 6, 7, 9).
03-Feb-2005 1.3 Update characteristics (Figure 4, Tables 6, 7).
25-Feb-2005 1.4 Update temperature trip limits (Ta b l e 9 )
06-May-2005 1.5 Update characteristics (Figure 3, 4, 28 and Table 6, 7).
05-Aug-2005 2
06-Jan-2006 3
08-Feb-2007 4
21-Aug-2008 5 Minor formatting changes; updated Ta b le 1 , 7 and Section 8.
Corrected footprint dimensions; update characteristics (Figure 1, 2, 3, 4,
5, 6, 7, 8, 26, 27, 30 and Table 1, 2, 3, 6, 7).
Removed STM1403 references (Figure 1, 2, 3, 4, 5, 6, 7, 8, 26, 27, 28
and Table 1, 2, 5, 6, 7,
Update status, characteristics, lead-free text, marking (Figure 4, 31 and
Ta bl e 6, 7, 9).
Update cover page, Figure 3: Block diagram, Table 7: Physical and
environmental tamper detection levels, Figure 28: Temperature
hysteresis, and part numbering (Table 9.)
9).
34/36
STM1404
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