The STLC5046 is a monolithic programmable 4
channel codec and filter. It operates with a single
+3.3 V supply.
The analog interface is based on a receive output
buffer driving the SLIC RX input and on an
amplifier input stage.
STLC5046
LQFP64
Due to the single supply voltage a proper mid
supply reference level is generated internally by
the device and all analog signals are referred to
this level (AGND).
The PCM interface uses one common 8 kHz
frame sync. pulse for transmit and receive
direction. The bit clock can be selected between
four standards: 1.536/1.544 MHz, 2.048 MHz,
4.096 MHz, 8192 MHz. Device programmability is
achieved by means of 41 registers allowing to set
the different parameters like TX/RX gains,
encoding Law (A/µ), time slot assignment,
independent channels power up/down,
loopbacks, PCM bits offset.
Thanks to pin-strap option, the most significant of
the above parameters can be set by hardware
connection of dedicated pins. This allow to use
this device also on line card without MCU on
board. When pin-strap option is selected different
pins of the device will change their function (see
pin description).
In MCU control mode the STLC5046 can be
programmed via serial interface running up to
4MHz.
Receive analog amplifier output channel 0. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
Receive analog amplifier output channel 1. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
42 VFRO2 AO
48 VFRO3 AO
Receive analog amplifier output channel 2. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
Receive analog amplifier output channel 3. PCM data received on the programmed
time slot on DR input is decoded and appears at this output.
35 VFXI0 AI TX Input amplifier channel 0. Typ 1M.input impedance
38 VFXI1 AI TX Input amplifier channel 1. Typ 1M.input impedance
43 VFXI2 AI TX Input amplifier channel 2. Typ 1M.input impedance
46 VFXI3 AI TX Input amplifier channel 3. Typ 1M.input impedance
40 CAP AI
AGND voltage filter pin. A 100nF capacitor must be connected between ground and
this pin.
Power supply
25, 36,
37, 44,
45, 56,
26,30,
31, 50,
51,55
VCC/0/1/2
/3/ 4/5
VEE/0/1/2
/3/ 4/5
APS
Total 6 pins: 3.3 V analog power supplies, should be shorted together, require
100nF decoupling capacitor to VEE.
APS Total 6 pins: analog ground, should be shorted together.
9 VDD DPS Digital power supply 3.3 V, require 100 nF decoupling capacitor to VSS.
8 VSS DPS Digital ground
Doc ID 7052 Rev 57/51
Block diagram and pin connectionSTLC5046
Table 3.Pin description (continued)
N. Name Type Function
41 SUB DPS
Substrate connection. Must be shorted together with VEE and VSS pins as close as
possible the chip.
Not connected
15, 16,
17, 18,
32, 34,
N.C. Not connected.
47, 49,
64
1,2,63 RES Reserved: must be left not connected.
Digital
27 M0 DI Mode select, see M1
M1M0Mode select
54 M1 DI
0
1
0
1
Pin-strap mode: basic functions selected by proper pin strapping
1
MCU mode: device controlled via serial interface
0
Reset status
0
Not allowed
1
Master clock input. Four possible frequencies can be used: 1.536/1.544 MHz;
13 MCLK DI
2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect the frequency
applied. This signal is also used as bit clock and it is used to shift data into and out
of the DR and DX pins.
Transmit time slot (open drain output, 3.2mA). Normally it is floating in high
12 TSX
ODO
impedance state except when a time slot is active on the DX output. In this case
output pulls low to enable the backplane line driver.
TSX
Transmit PCM interface. It remains in high impedance state except during the
11 DX DTO
assigned time slots during which the PCM data byte is shifted out on the rising edge
of MCLK.
10 DR DI
Receive PCM interface. It remains inactive except during the assigned receive time
slots during which the PCM data byte is shifted in on the falling edge of MCLK.
SLIC control I/O pin #7. Can be programmed as input or output via DIR register.
61 IO7 DIO
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn
60 IO8 DIO SLIC control I/O pin #8. (see IO7 description).
59 IO9 DIO SLIC control I/O pin #9. (see IO7 description).
58 IO10 DIO SLIC control I/O pin #10. (see IO7 description).
57 IO11 DIO SLIC control I/O pin #11. (see IO7 description).
Digital (dual mode)
8/51Doc ID 7052 Rev 5
output signals controlling the SLICs.
STLC5046Block diagram and pin connection
Table 3.Pin description (continued)
N. Name Type Function
MCU control mode: FS.
Frame Sync. Pulse. A pulse or a square wave waveform with an 8kHz repetition
rate is applied to this pin to define the start of the receive and transmit frame.
14FS/FS0DI
19IO0/GR2DIO/DI
20IO1/PD2DIO/DI
Effective start of the frame can be then shifted of up to 7 clock pulses independently
in receive and transmit directions by proper programming of the PCMSH register.
Pin-strap control mode: FS0.
Frame Sync. pulse of channel #0. One MCLK cycle long, starts PCM data transfer
in the Time Slot following its falling edge (Short Frame Delayed Timing).
MCU control mode: IO0.
Slic control I/O pin #0. Can be programmed as input or output via DIR register.
Depending on content of CONF register can be a static input/output or a dynamic
input/output synchronized with the CSn
Pin-strap control mode: GR2.
Receive gain programming channel 2:
1: Receive gain = -0.8 dB
0: Rec. gain = -4.3 dB
MCU control mode: IO1.
Slic control I/O pin #1. (see IO0 description).
Pin-strap control mode: PD2.
Power Down command channel 2:
1: Channel 2 Codec is in power down.
(equivalent to CONF reg bit2 = 1)
0: Channel 2 Codec is in power up.
(equivalent to CONF reg. bit2 = 0)
output signals controlling the SLICs.
21IO2/GR3DIO/DI
22IO3/PD3DIO/DI
23IO4/FS1DIO/DI
24IO5/FS2DIO/DI
MCU control mode: IO2.
Slic control I/O pin #2. (see IO0 description)
Pin-strap control mode: GR3.
Receive gain programming channel 3. (see GR2 description)
MCU control mode: IO3.
Slic control I/O pin #3. (see IO0 description).
Pin-strap control mode: PD3.
Power down command channel 3. (see PD2 description)
MCU control mode: IO4
Slic control I/O pin #4. (see IO0 description).
Pin-strap control mode: FS1.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
MCU control mode: IO4.
Slic control I/O pin #5. (see IO0 description).
Pin-strap control mode: FS2.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
Doc ID 7052 Rev 59/51
Block diagram and pin connectionSTLC5046
Table 3.Pin description (continued)
N. Name Type Function
MCU control mode: IO4.
Slic control I/O pin #6. (see IO0 description).
62IO6/FS3DIO/DI
28CS0
29CS1
53CS2/GX2DO/DI
/GX0DO/DI
/GX1DO/DI
Pin-strap control mode: FS3.
Frame sync. pulse of channel #1. One MCLK cycle long, starts PCM data transfer in
the time slot following its falling edge (short frame delayed timing).
MCU control mode: CS0.
Slic CS control #0.
Depending on CONF reg. content can be a CS output for SLIC #0 or a static I/O.
When configured as CS output it is automatically generated by the Codec with a
repetition time of 31.25 µs. In this mode also the IO11.0 are synchronized and carry
proper data in and out synchronous with CS.
Pin-strap control mode: GX0.
Transmit gain programming channel 0:
1: Transmit gain = 0 dB
0: Transmit gain = - 3.5 dB
MCU control mode: CS1
Slic CS control #1, (see CS0
Pin-strap control mode: GX1.
Transmit gain programming channel 1 (see GX0 description)
MCU control mode: CS2
Slic CS control #2, (see CS0
Pin-strap control mode: GX2.
Transmit gain programming channel 2 (see GX0 description)
:
description).
.
description).
MCU control mode: CS3
52CS3
4CS
7
6CI/PD0DI/DI
/GX3DO/DI
/PD1DI/DI
CCLK/GR1
DI/DI
Slic CS control #3, (see CS0 description).
Pin-strap control mode: GX3.
Transmit gain programming channel 3 (see GX0 description)
MCU control mode: CS
Chip Select of Serial Control Bus. When this pin is low control information can be
written to or read from the device via the CI and CO pins.
Pin-strap control mode: PD1.
Power Down command channel 1. (see PD2 description).
MCU control mode: CCLK.
Clock of Serial Control Bus. This clock shifts serial control information into or out of
CI or CO when CS input is low depending on the current instruction. CCLK may be
asynchronous with the other system clocks.
Pin-strap control mode: GR1.
Receive gain programming ch. 1, (see GR2 description).
MCU control mode: CI.
Control Data Input of Serial Control Bus. Control data is shifted in the device when
CS
Pin-strap control mode: PD0.
Power Down command channel 0. (see PD2 description).
.
.
is low and clocked by CCLK.
10/51Doc ID 7052 Rev 5
STLC5046Block diagram and pin connection
Table 3.Pin description (continued)
N. Name Type Function
MCU control mode: CO.
Control Data Output of Serial Control Bus. Control data is shifted out the device
5CO/GR0DTO/DI
3INT
/AMU ODO/DI
when CS
H. I., valid data are shifted out during the following 8 CCLK pulses.
Pin-strap control mode: GR0.
Receive gain programming ch. 0, (see GR2 description).
MCU control mode: INT
Interrupt output (open drain), goes low when a data change has been detected in
the I/O pins. One mask registers allow to mask any I/O pin. Interrupt is reset when
the I/O register is read.
Pin-strap control mode: AMU.
A/µ Law selection:
AMU=0: µ Law
AMU=1: A Law, even bit inverted
is low and clocked by CCLK. During the first 8 CCLK pulses the CO pin is
.
Doc ID 7052 Rev 511/51
Functional descriptionSTLC5046
2 Functional description
2.1 Power on initialization
When power is first applied it is recommended to reset the device by forcing the condition
M1.0=00, in order to clear all the internal registers.
In MCU mode M0 is set steadily Low and the device is reset by applying a negative pulse to
M1 (its operative level in MCU mode is High); same result can be obtained by writing an
High level into the control bit RES of the CONF register.
In pin-strap mode M1 is set steadily Low and the device is reset by applying a negative
pulse to M0 (its operative level in pin-strap mode is High); at the end of the Reset phase
(M0=High) the device is programmed according to the logical configuration of the control
pins.
During the reset condition all the I/On and CS_n pins are set as inputs, DX is set in high
impedance and all VFROn outputs are forced to AGND.
2.2 Power down state
Each of the four channel may be put into power down mode by setting the appropriate bit in
the CONF register or strapping to VDD the proper pin. In this mode the eventual
programmed DX channel is set in high impedance while the VFRO outputs are forced to
AGND. In pin-strap mode the value forced on the input pin is internally updated every FS
signal.
2.3 Transmit path
The analog VFXI signal through an amplifier stage is applied to a PCM converter and the
corresponding digital signal is sent to DX output.
In MCU mode, the amplifier gain can be programmed with two different values by means of
TXG Reg.: 0 dB or +3.52 dB.
A programmable gain block after the A/D conversion allows to set transmit gain in 12dB
range, with steps <0.1dB by writing proper code into GTXn register.
Setting GTXn=00h, the transmitted signal is muted, i.e. an idle PCM signal is generated on
DX.
A/µ coding Law is selected by bit5 (AMU) of CONF reg.
Setting LIN=1 (bit6 of CONF reg.) the linear coding Law is selected (16bits); in this case the
signal sent on DX will take two adjacent PCM time slots.
In Pin-strap mode, the amplifier gain is set to 0dB; only two values of Transmit gain can be
selected according to the level of GXn control input (in Pin-strap):
GXn=1 selects the gain corresponding to GTXn=FFh (0 dB)
GXn=0 selects the gain corresponding to GTXn=8Fh (-3.5 dB)
Different gain value is obtained through proper voltage divider.
A/µ coding Law is selected according to AMU pin level:
12/51Doc ID 7052 Rev 5
STLC5046Functional description
AMU=0 µ Law selected.
AMU=1 A Law selected.
VFXI input must be AC coupled to the signal source; the voltage swing allowed is 1.0Vpp
when the preamplifier gain is set 0dB or 0.66Vpp if the gain is set to 3.52dB (MCU mode
only); higher levels must be reduced through proper dividers.
Typical impedance of VFXI input is 1Mohm.
Figure 3.Transmit path
TXG: 0dB
+3.52dB
VFXI
1M
AGND
Ω
for TXG=0dB; GX=0dB (FF)
-15dBm|
Ω
600
ΣΔ
conv.
0dBm0
GX
8 bit linear
1/4 to 1
A/
Figure 4.Receive path
RXG: 0dB
-1. 94dB
-4. 44dB
-7. 96dB
=> -3dBm |
-13.98d B
VFRO
600Ω
DR
A/
μ
GR
8 bit linear
1/4 to 1
ΣΔ
conv.
for RXG=0 dB; GR=0dB (FF)
0dBm0
Figure 5.MCU mode: time slot assignment
FSFS
TS0TS23/31/61 /127
Receive Time SlotTransmit Time Slot
D7..................D0D7...................D0
DX
μ
DXAn Reg.
DRAn Reg.
2.4 Receive path
The received PCM signal DR through the decoder section, the gain select block and the D/A
converter is converted in an analog signal which is transferred to VFRO output through an
amplifier stage.
Doc ID 7052 Rev 513/51
Functional descriptionSTLC5046
In MCU mode a programmable gain block before the A/D conversion allows to set receive
gain in 12dB range, with steps <0.1 dB by writing proper code into GRXn register.
The amplifier gain can be programmed with five different values by means of RXG register:
0dB -1.94dB -4.44dB -7.96dB -13.98dB.
Setting GRXn=00h, the receive signal is muted and VFRO output is set to AGND.
A/µ coding Law is selected by bit5 (AMU) of CONF reg.
Setting LIN = 1 (bit6 of CONF reg.) the linear coding Law is selected (16bits); in this case
the signal received on DR will take two adjacent PCM time slots.
In pin-strap mode only two values of Receive Gain can be selected according to the level of
GRn control input (in pin-strap) GRn = 1 selects the gain corresponding to GRXn= E2h,
RXG = 0dB (-0.8 dB) GRn = 0 selects the gain corresponding to GRXn = AFh,
RXG = -1.94 dB (-4.3 dB).
Different gain value is obtained through proper voltage divider.
A/µ coding Law is selected according to AMU pin level:
AMU=0 µ Law selected.
AMU=1 A Law selected.
VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent
a DC current flow.
VFRO has a drive capability of 1.0mA (peak value), with a max AC swing of 2 Vpp.
In order to get the best noise performances it is recommended to keep the GRX value as
close as possible to the maximum (FFh) setting properly the additional attenuation by
means of RXG.
2.5 PCM interface
The STLC5046 dedicate five pins (six in pin-strap mode) to the interface with the PCM
highways.
MCLK represents the bit clock and is also used by the device as a source for the clock of the
internal Sigma Delta converter timings. Four possible frequencies can be used:
The operating frequency is automatically detected by the device when both MCLK and FS
are applied. MCLK is synchronizing both the transmit data (DX) and the receive data (DR).
2.5.1 MCU mode
The Frame Sync. signal FS is the common time base for all the four channels; Short (one
MCLK period) or Long (more than one MCLK period) FS are allowed.
Transmit and Receive programmable Time-Slots are framed to an internal sync. signal that
can be coincident with FS or delayed of 1 to 7 MCLK cycles depending on the programming
of PCMSH register.
14/51Doc ID 7052 Rev 5
STLC5046Functional description
DX represent the transmit PCM interface. It remains in high impedance state except during
the assigned time slots during which the PCM data byte is shifted out on the rising edge of
MCLK.
The four channels can be shifted out in any possible timeslot as defined by the DXA0 to
DXA3 registers. If one codec is set in Power Down by software programming the
corresponding timeslot is set in High Impedance. When linear coding mode is selected by
CONF register programming the output channel will need two consecutive timeslots (see
register description).
DR represent the receive PCM interface. It remains inactive except during the assigned time
slots during which the PCM data byte is shifted in on the falling edge of MCLK. The four
channels are shifted in any possible timeslot as defined by the DRA0 to DRA3 registers.
Figure 6.Pin-strap mode: time slot assignment
Receive /Transmit
Time Slot
CH0CHnCHm
D7...................D0
FS0
2.5.2 Pin-strap mode
When pin-strap mode is selected, dedicated Frame Sync. FS3..0 are provided on dual
function pins:
MCU Pin-strap Pin
FS FS0 14
IO4 FS1 23
IO5 FS2 24
IO6 FS3 62
The PCMSH register cannot be accessed, therefore the beginning of the transmit and
receive frame is identified by the rising edge of the FSn signal.
D7..................D0D7...................D0
FSn
FSm
TS23/31 /61/ 127
Each channel has its dedicated Frame Sync. signal FSn. Short or Long frame timing is
automatically selected; depending on the FS signal applied to FS0 input. The assigned
Time Slot (Transmit and Receive) takes place in the 8 MCLK cycles following the falling
edge of FSn in case of Short Frame or the rising edge in case of Long Frame. If one codec
is set in Power Down by proper pin-strap configuration the corresponding timeslot is not
loaded and the VFRO output is kept at steady AGND level.
Doc ID 7052 Rev 515/51
Functional descriptionSTLC5046
Finally by means of the LOOPB register is possible to implement a digital or analog
loop_back on any of the selected channels.
TSX
represent the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in
high impedance state except when a time slot is active on the DX output. In this case TSX
output pulls low to enable the backplane line driver. Should be strapped to VSS when not
used.
Table 4.Control byte structure
First byte (address)
7 6 5 4 3 2 1 0
R/W D/S A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
R/W = 0: Write register
= 1: Read register
R/W
= 0: Single byte
D/S
= 1: Two bytes
D/S
A5..A0: Register Address
2.6 Control interface
STLC5046 has two control modes, a microprocessor control mode and a pin-strap control
mode. The two modes are selected by M0 and M1 pins. When M0 = low, M1 = high (MCU
control mode) the MCU port is activated; and the 41 registers of the device can be
programmed. When M0 = high, M1 = low (Pin-strap mode) the microprocessor control port
is disabled and some of the digital pins change their function allowing to perform a very
basic programming of the device.
In pin-strap mode the status of the control pins is entered at power-on reset and refreshed at
any Frame Sync. cycle.
In MCU mode the control information is written to or read from STLC5046 via the serial four
wires control bus:
CCLK: Control Clock
CS
: Chip Select input
CI: Serial Data input
CO: Serial Data output
All control instructions require 2 bytes, with the exception of the single byte for command
synchronization. The first byte specify the register address, and the type of access (Read or
Write). The second byte contain the data to be loaded into the register (on CI wire) or
carried out the register content (on CO wire) depending on the R/W bit of the first byte. CO
wire is normally in High Impedance and goes to low impedance only during the second byte
in case of Read operation. This allows to use a common wire for both CI/CO.
Serial data CI is shifted to the serial input register on the rising edge of CCLK and CO is
shifted out on the falling.
16/51Doc ID 7052 Rev 5
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