ST STLC1510 User Manual

NorthenLite G.lite DMT Transceiver

■

ATM transport

■ Forward Error correction & interleaving

■

Framing & de-framing

■

DMT modulation and demodulation

■

Start-up & showtime control processing

In addition, the STLC1510 provides the following fea­tures:

■

Serial and Parallel network interface at back­end to CO equipment

■

Serial interface to the AFE chip STLC1511

■

Access to off chip memory

■

Power-up boot program stored in ROM

■ 132 balls 12x12x1.7 mm LBGA package

■

Power Consumption: 0.75 Watt

■

Power Supp.: 2.5 V (core) and 3.3 V (I/O ring)

■

STLC1510

PRODUCT PREVIEW

LBGA132

ORDERING NUMBER: STLC1510

1.0 GENERAL DESCRIPTION

The STLC1510 is a high-speed modem chip that pro­vides the digital portion of a G.992.2 DSL access at a
Central Office (CO) site. It provides downstream and
upstream data transport between an ATM byte
stream and an analog front-end chip using Discrete
Multi-Tone (DMT) Modulation.

The STLC1510 is compliant with ITU-T G.992.2
(G.Lite), G.996.1 (G.Test), G.994.1 (G.Handshake),
G.997.1 (G.Ploam).

Figure 1. Block Diagram

TxClk

TxClav

TxEnb

TxSOC

UTxData[7:0]

TxAddr[4:0]

TxParity

TxBP

RxClk

RxClav

RxEnb

RxSOC

URxData[7:0]

RxAddr[4:0]

RxParity

VDD3_3

VDD2_5

VSS

HPI_Data[7:0]

HPI_Addr [2 :0]

HPI_RWN

HPI_ASN

83

HPI

NIF

FEC

MAP

7

7

14

TAP

TDI

TCK

TDO

EPM

LAMBA Bus

TMS

TRSTN

VDD_PLL

Guard_PLL

EN_D950_EMU

ARM2H P_INT

HPI_CSN

mem

VSS_PL L

ARM_MODE

HPI_CLK

BPU

mem

mem

D950ARM

22

Pmode[1:0]

CMode[1:0]

pgmctrl

Dual
MAC

TGB

8

VCODC

RESETN

GPIO[7:0 ]

D950_CMODE

LinDr_AGC2

LinDr_AGC1

LinDr_Peak

DFE

TxSOUT[1:0]

mem

mem

INF_OUT

REF_OUT

A_SCLK
CK35M

RxSIN[1:0]

REF_CLK

SPI_CLK
SPI_ENB

SPI_DTX
SPI_DRX

November 2000

This is preliminary information ona new product now in development. Details are subject to change without notice.

1/40

STLC1510

2.0 LIST OF MAIN BLOCKS

The STLC1510 G.lite DMT Transceiver is formed by
the following blocks (refer to Figure 1.):

Embedded Processor Module (EPM)

The EPM includes two embedded processor cores:
the ARM7TDMI, a RISC microprocessor, and the
D950, a 16-bit DSP processor. The RISC micropro­cessor handles the chip control, G.Lite start-up and
showtime control and DSP initialization. It also imple­ments the Framing and Interleaving/Deinterleaving
function required by G.992.2 standard.

Block Processing Unit (BPU)

Computationally intensive digital signal processing
functions are performed in this engine. This engine
utilizes customized DSP architecture that includes
two multiplier/accumulator (MAC).

DigitalFront-End (DFE)

This block provides the interface to an external ana­log front-end (AFE) device. This block provides deci­mation, interpolation for the signal sample for the
ADC and DAC on the AFE and signal level monitor­ing for the analog AGC.

NetworkInterface (NIF)

The NIF is aselectable interface that carries the ATM
signals to and from the STLC1510. This interface
supports one parallel interface (Utopia Level 2) or a
serial data interface. The NIF includes a FIFO to buff­er the data between the clock domains of the back­end interface and the internal clock.

ForwardError-Correction (FEC)

The Forward Error Correction is done using Reed­Solomon Coding. The R-S FEC encoding is per­formed byte-wise in the transceiver on the transmit­ted bytes. The two basic parameters that determine
the performance of the code are the code word size,
which consists ofone or more DMT symbols (S), and
the number of redundant check bytes R.

Timing Generation Block(TGB)

The timing generation block generates global clock
and synchronization signals for the STLC1510. It
uses the input clock signals to derive the main inter­nal and output clock signals, as well as all synchroni­zation pulses required to coordinate timing between
the sub-blocks.

Test Access Port (TAP)

This block provides the test access to the STLC1510
using JTAG and BIST techniques.

HPI Interface

A host processor interface is provided to allow the
STLC1510 to be optionally controlled by an external
microcontroller.

3.0 TRANSIENT ENERGY CAPABILITIES

3.1 ESD

ESD (Electronic Discharged) tests have been per­formed for the Human Body Model (HBM).

The pins of the device are to be able to withstand
minimum 2000V for the HBM.

3.2 Latch-up

The maximum sink or source current from any pin is
limited to 200mA to prevent latch-up.

4.0 ABSOLUTE MAXIMUM RATINGS

The absolute maximum ratings, as specified below,
are those ratings beyond which the device’s lifetime
may be impaired. The meeting of electrical specifica­tions is not implied when the device is subjected to
the absolute limits.

The following table identifies the device’s minimum
and maximum ratings and along with the operating­conditions they define the limits for testing the device

Mapper/De-mapperBlock (MAP)

The Mapper/De-mapper Block (MAP) performs the
bit packing and un-packing and constellation encod­er/decoder for a G.992.2 DSL modem. This block
also supports generation of Reverb and medley.

2/40

Table 1. ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER MINIMUM MAXIMUM UNITS

VDD3_3 3.3V Supply voltage w.r.t.VSS (0V) -0.5 4 V

VDD2_5 2.5V Supply voltage w.r.t.VSS (0V) -0.5 3.3 V

STLC1510

T

amb

V

IN,VOUT

V

IN5,VOUT5

I

IN,IOUT

P

D

Ambient temperature -40 85 °C

Voltage at any 3.3V standard input or output -0.5 VDD3_3 + 0.5 V

Voltage at any 5V compatible input or output

1

-0.8 6.3 V

Current at any input or outputs -20 20 mA

Power dissipation 0 0.75 W

Vesd Electrostatic Protection 2000 V

I latchup I/O Latch-up Current V < 0V, V > Vdd 200 mA

<1> -0.8V undershoots and 6.3V overshoots do not last longer than 4nS.

3/40

STLC1510

Figure 2. Ball Map.

STLC1510 Netlist

4/40

Table 2. Pad Description

Signal I/O Pad Type Description BGA

Clock Interface

STLC1510

REF_CLK I 5V TolCMOS input 17.168 MHzor 35.328 MHz reference

clock input.
RESETN I 5V TolCMOS input Hardware reset (active low) E13
D950_CMODE I 5V TolCMOS input ’1’ - Normal operation

’0’ - Reduced REF_CLK frequency in

bypass mode for chip test
PMode_1 I 5V TolCMOS input Power Mode Select G1
PMode_0 I 5V TolCMOS input Power Mode Select H1
CMode_1 I 5V TolCMOS input Clock Mode Select H2
CMode_0 I 5V TolCMOS input Clock Mode Select L1

STLC1511 AFE Interface

A_SCLK I 5V Tol CMOS input ADC/DAC sample frame clock H14
CK35M O 5V Tol3.3V TTL 2mA slew ltd

output
RxSIN_1 I 5V TolCMOS input ADC serial input data L14
RxSIN_0 I 5V TolCMOS input ADC serial input data K14
TxSOUT_1 O 5V Tol3.3V TTL 2mA slew ltd

output

35.328 MHz reference clock output. J14

DAC serial output data F14

1

K13

C13

TxSOUT_0 O 5V Tol3.3V TTL 2mA slew ltd

output
SPI_CLK O 5V Tol 3.3V TTL 2mA slew ltd

output
SPI_ENB O 5V Tol 3.3V TTL 2mA slew ltd

output
SPI_DTX O 5V Tol3.3V TTL 2mA slew ltd

output
SPI_DRX I 5V Tol CMOS input RX STLC1511 input Control Data L13
XTAL_CTRL O 5V Tol 3.3V TTL 2mA slew ltd

output

STLC1512 Line Driver Interface

LinDr_AGC1 O 5V Tol3.3V TTL 2mA slew ltd

output
LinDr_AGC2 O 5V Tol3.3V TTL 2mA slew ltd

output
LinDr_Peak O 5V Tol3.3V TTL 2mA slew ltd

output

DAC serial output data E14

STLC1511 control interface clock M14

TX/RX STLC1511 Enable Control
signal

TX STLC1511 Control Data N14

XTAL output control pin Not on

STLC1511 AGC Gain control 1 D13

STLC1511 AGC Gain control 2 D14

STLC1511 Peakcontrol

2

M13

BGA

C14

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STLC1510

Table 2. Pad Description

Signal I/O Pad Type Description BGA

Test Interface

TCK I 5V TolCMOS input JTAGTest Clock N9
TMS I 5V Tol CMOS input JTAGTest Mode Select N7
TDI I 5V Tol CMOS input JTAGTestData Input P8
TDO O 5V Tol3.3V TTL2mA slew ltd

output
TRSTN I 5V Tol CMOS input dedicated TAPreset (active low) P9

Network Interface (UTOPIA / Serial Clock & Data)

TxClk I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
TxClav O 5V Tol3.3V TTL2mA slew ltd

output
TxBP O 5V Tol 3.3V TTL 2mA slew ltd

output
TxEnb I 5V Tol.CMOS input Tx Enable. A6
TxSOC I 5V TolCMOS input Tx start of Cell C2
UTxData_7 I 5V TolCMOS input Utopia2 Transmitdata bit 7 G2
UTxData_6 I 5V TolCMOS input Utopia2 Transmitdata bit 6 F2
UTxData_5 I 5V TolCMOS input Utopia2 Transmitdata bit 5 F1
UTxData_4 I 5V TolCMOS input Utopia2 Transmitdata bit 4 E1
UTxData_3 I 5V TolCMOS input Utopia2 Transmitdata bit 3 E2
UTxData_2 I 5V TolCMOS input Utopia2 Transmitdata bit 2 D2

JTAG Test Data Output N8

Input Utopia2 Tx clock or output PSIF
Tx clock.

Tx cell available signal. B5

Tx back pressure signal. B4

A4

UTxData_1 I 5V TolCMOS input Utopia2 Transmitdata bit 1 D1
UTxData_0 I 5V TolCMOS input Utopia2 Transmitdata bit 0; also CDIF

input data
TxAddr_4 I 5V TolCMOS input Utopia2 TransmitAddress B1
TxAddr_3 I 5V TolCMOS input Utopia2 TransmitAddress A1
TxAddr_2 I 5V TolCMOS input Utopia2 TransmitAddress A2
TxAddr_1 I 5V TolCMOS input Utopia2 TransmitAddress A3
TxAddr_0 I 5V TolCMOS input Utopia2 TransmitAddress B2
TxParity I 5V Tol.CMOS input Odd parity bit of the data on

UTxData[7:0].
RxClk I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output

6/40

Input Utopia2 Rxclock or output PSIF

Rx clock.

C1

B3

N6

Table 2. Pad Description

Signal I/O Pad Type Description BGA

STLC1510

RxClav O 5V Tol3.3V TTL 2mA slew ltd

output
RxEnb I 5V Tol.CMOS input Rx Enable. N4
RxSOC O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_7 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_6 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_5 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_4 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_3 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_2 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_1 O 5V Tol 3.3V TTL 2mA slew ltd

output
URxData_0 O 5V Tol 3.3V TTL 2mA slew ltd

output

Rx cell available signal. P5

Rx start of Cell P4

Utopia2 Receive data bit 7 N3

Utopia2 Receive data bit 6 P3

Utopia2 Receive data bit 5 P2

Utopia2 Receive data bit 4 N2

Utopia2 Receive data bit 3 M2

Utopia2 Receive data bit 2 P1

Utopia2 Receive data bit 1 N1

Utopia2 Receive data bit 0; also CDIF
output data

M1

RxAddr_4 I 5V Tol.CMOS input Utopia2 Receive Address L2
RxAddr_3 I 5V Tol.CMOS input Utopia2 Receive Address K2
RxAddr_2 I 5V Tol.CMOS input Utopia2 Receive Address K1
RxAddr_1 I 5V Tol.CMOS input Utopia2 Receive Address J2
RxAddr_0 I 5V Tol.CMOS input Utopia2 Receive Address J1
RxParity O 5V Tol 3.3V TTL 2mA slew ltd

output

HPI

HPI_Data_7 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_6 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_5 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_4 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_3 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output

Odd parity bit of the data on
URxData[7:0].

HPI Port Data B14

HPI Port Data A14

HPI Port Data B13

HPI Port Data A13

HPI Port Data B12

N5

7/40

STLC1510

Table 2. Pad Description

Signal I/O Pad Type Description BGA

HPI_Data_2 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_1 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Data_0 I/O 5V TolCMOS input/ 5V Tol3.3V

TTL 2mA slew ltd output
HPI_Addr_2 I 5V Tol.CMOS input HPI Port Address B7
HPI_Addr_1 I 5V Tol.CMOS input HPI Port Address A7
HPI_Addr_0 I 5V Tol.CMOS input HPI Port Address B8
HPI_CLK I 5V Tol.CMOS input HPI Clock Input B9
HPI_RWN I 5V Tol.CMOS input HPI Port Read/WriteN B10
HPI_CSN I 5V Tol.CMOS input HPI Port Chip Select A8
HPI_ASN I 5V Tol.CMOS input HPI Port Address Strobe Input A10
ARM2HP_INT O 5V Tol3.3V TTL 2mA slew ltd

output

Misc

VCODC I Analog Input VCO control voltage for stand alone

HPI Port Data A12

HPI Port Data A11

HPI Port Data B11

Active-low ARM7 To Host Processor
Interrupt

PLL testing

3

A9

P6

REF_OUT O 5V Tol3.3V TTL 2mA slew ltd

output
INF_OUT O 5V Tol3.3V TTL2mA slew ltd

output

EN_D950_EMU I 5V TolCMOS input EN_D950_EMU=0; D950 core held in

ARM_MODE I 5V Tol CMOS input ARM_MODE=0; Connects external

GPIO_7 I/O 5V TolCMOS input /5V Tol3.3V

TTL 2mA slew ltd output
GPIO_6 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output
GPIO_5 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output

PLL REF signal at input to phase
detector

PLL INF signal at input to phase
detector

reset by ARM7, GPIO pin #1,2,3 and
4 are normal mode
EN_D950_EMU=1; D950 core is not
held inreset by ARM7, GPIO pins
#1,2,3 and 4 are dedicated to the
D950 emulator

TAP pins directly to ARM_TAP
ARM_MODE=1; ARM_TAP in daisy
chain configuration after MTAP(i.e.
same as ALPHA configuration)

General Purpose I/O Ports N13

General Purpose I/O Ports P14

General Purpose I/O Ports P13

J13

H13

P7

P10

8/40

Table 2. Pad Description

Signal I/O Pad Type Description BGA

STLC1510

GPIO_4 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output
GPIO_3 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output
GPIO_2 I/O 5V TolCMOS input /5V Tol3.3V

TTL 2mA slew ltd output
GPIO_1 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output
GPIO_0 I/O 5V TolCMOS input / 5V Tol 3.3V

TTL 2mA slew ltd output

Power Supply

VDD3_3_8 P 3.3 volt supply pad 3.3V I/O power supply D3
VDD3_3_7 P 3.3 volt supply pad 3.3V I/O power supply C5
VDD3_3_6 P 3.3 volt supply pad 3.3V I/O power supply C3
VDD3_3_5 P 3.3 volt supply pad 3.3V I/O power supply C4
VDD3_3_4 P 3.3 volt supply pad 3.3V I/O power supply L12
VDD3_3_3 P 3.3 volt supply pad 3.3V I/O power supply M12
VDD3_3_2 P 3.3 volt supply pad 3.3V I/O power supply K12

General Purpose I/O Ports/
D950_IDLE

General Purpose I/O Ports/
D950_SNAP

General Purpose I/O Ports/
D950_INCYCLE

General Purpose I/O Ports/
D950_NERQ

General Purpose I/O Ports/LCLK N10

N12

P12

N11

P11

VDD3_3_1 P 3.3 volt supply pad 3.3V I/O power supply M11
VDD2_5_8 P 2.5 volt supply pad 2.5V ASIC core power supply M3
VDD2_5_7 P 2.5 volt supply pad 2.5V ASIC core power supply L3
VDD2_5_6 P 2.5 volt supply pad 2.5V ASIC core power supply K3
VDD2_5_5 P 2.5 volt supply pad 2.5V ASIC core power supply C10
VDD2_5_4 P 2.5 volt supply pad 2.5V ASIC core power supply C11
VDD2_5_3 P 2.5 volt supply pad 2.5V ASIC core power supply C12
VDD2_5_2 P 2.5 volt supply pad 2.5V ASIC core power supply D12
VDD2_5_1 P 2.5 volt supply pad 2.5V ASIC core power supply M4
VSS_20 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_19 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_18 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_17 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

C9

J3

J12

H12

9/40

STLC1510

Table 2. Pad Description

Signal I/O Pad Type Description BGA

VSS_16 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_15 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_14 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_13 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_12 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_11 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_10 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_9 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_8 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_7 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

VSS_6 P common ground supply pad Ground return for VDD3_3 and

VDD2_5

M6

M5

H3

M7

G3

F3

E3

M9

C6

C7

C8

VSS_5 P common ground supply pad Ground return for VDD3_3 and

M10

VDD2_5

VSS_4 P common ground supply pad Ground return for VDD3_3 and

E12

VDD2_5

VSS_3 P common ground supply pad Ground return for VDD3_3 and

F12

VDD2_5

VSS_2 P common ground supply pad Ground return for VDD3_3 and

M8

VDD2_5

VSS_1 P common ground supply pad Ground return for VDD3_3 and

G12

VDD2_5
VDD_PLL P 2.5 volt supply pad 2.5V supply forPLL G14
VSS_PLL P ground pad Ground return for PLL F13
Guard_PLL P ground pad Ground Voltage reference for PLL G13

<1> 212 MHz in PLL bypass mode
<2> This pad is configured as a pseudo open drain connection and can only pull the output low, or go high impedance
<3> Add pullup to this pin on board. This pad is configured as a pseudo open drain connection and can only pull the output low, or go high

impedance

10/40

STLC1510

5.0 MAIN BLOCK DESCRIPTION

The following sections describe the sequence of
functions performed by the chip

5.1 Network Interface and Controller (NIF)

The Network Interface and Controller block (NIF) is
responsible for transferring data between the
STLC1510 and the ATM network. The NIF has two
interfaces to the backplane: an 8-bit Utopia Level 2
Physical Interface (U2PHY) and a clock and data se­rial interface (CDIF). It communicates with the rest of
the STLC1510 via the LambaBus. Figure 3. shows a
functional/data path block diagram of the NIF (this di­agram does not include all glue logic between the
major functional blocks). 37 external pins are re­quired for the U2PHY and CDIF interfaces (19 for the
Tx direction, 18 for Rx). Pins are shared between the
two interfaces, as they will not both be active at the
same time.

5.1.1 Features

■

Utopia Level 2 8-bit parallel interface.

■ Up to 9 ATM cells (477 bytes) of rate adaptation

buffering for the Utopia Level 2 TX interface.
The amount of buffering is programmable via a
memory-mapped register.

■

Up to 2 ATM cells (106 bytes) of rate adaptation
buffering for the Utopia Level 2 RX interface.
The amount of buffering is programmable via a
memory-mapped register.

■

ATM Transconvergance (TC) layer cell
processor with 16-bit data path: performs
scrambling/descrambling, HEC calculation, cell
delineation with error detection (no error
correction) and cell rate decoupling by idle cell
insertion/detection.

■ Clock and Data serial interface.

■ Implemented as a hardware module on the

Lamba bus with an 8-bit data interface and 16­bit control interface.

■ 4 ATM cells (212 bytes) of rate adaptation

buffering in each direction (TX and RX) for
interfacing to the Lamba bus.

■

Pads partial or runt cells (ATM cells of length
less than 53 bytes) to 53 bytes in the TX
direction to prevent loss of synchronization at
theCPE.

5.1.2 External Interface (Pins)

The STLC1510 connects to the ATM network via 37
external pins. These are illustrated in Figure 3. Note
that the pins TxClk and RxClk are bidirectional and,
along with UTxData[0] and URxData[0], are shared
between the CDIF and U2PHY

5.1.3 Clock and data serial Interface (CDIF)

The STLC1510 can communicate serially to an ATM
network through the CDIF. Two serial data lines,one
for the Tx path (CO to CPE), the other for the Rx path
(CPE to CO), and two respective clocks realize the
exchange of information and control signals between
the STLC1510 and the network.

The CDIF of the STLC1510 has the following at­tributes:

■

Synchronizes to the ATM network.

■

Provides Tx and Rx clocks to the ATM network.

Transfers data between the ATM network and the
STLC1510’s Lamba Bus

■

Accepts idle ATM cells inserted by the ATM
network in the Tx direction. These idle cells are
used by the ATM network to adapt to the clock
provided to it by the STLC1510.

■

Generates clock gapping in the Tx direction.
This serves two purposes: it is a flow control
mechanism to theATM network chip, andit can
be used for the byte alignment. In the byte­alignment role, a clockgap longer thana pre-set
threshold indicates that the most significant bit
of a byte should be transmitted on the next
rising clock edge. This is useful for aligning data
bytes to the overhead bits inserted by the
STLC1510. In the flow control role, incoming
data is not sampled when the clock is off. The
threshold used to distinguish between byte
alignment and flow control clock gapping is
software programmable and has a range offrom
0 to 65535 clock cycles (a 16 bit register stores
the value).

■

Generates clock gapping in the Rx direction.
This serves asa flow-control mechanism; when
there is no data available for transmission to the
backplane, the clock is shutoff, ensuring that no
invalid data bits are sampled by the backplane.

11/40

STLC1510

Figure 3. NIF Off-Chip Signals

TxC lk

UTxData[0]

UTxData[7:1]

TxAddr[4:0]

TxParity

TxEnb

TxSOC

TxClav

TxBP

CDIF

TX

URxData[0]

8

5

U2PHY

TX

URxData[7:1]

RxClk

RxEnb

RxSOC

RxAddr[4:0]

RxClav

RxParity

8

5

CDIF

RX

U2PHY

RX

The following tasks are performed by the ATM net­work (in accordance with ITU-T Recommendation
I.432.1), and therefore do not have to be implement­ed in the STLC1510 when using the CDIF:

■

HCS generation (Tx).

■

Payload scrambling (Tx).

■

Optionally, enables clear channel mode, in
which HCS generation and payload scrambling
are disabled (Tx).

■

HCS cell delineation (Rx).

■ Payload descrambling (Rx).

■

Idle cell filtering (Rx).

■

Header error detection to recover valid ATM
cells (header correction is not implemented)
(Rx).

■

Optionally, enables clear channel mode, in
which every 53 x 8 = 424 bits are collected by
the receiver and sent to the backplane (Rx).

5.1.4 UTOPIA Level 2 Interface and Controller

The Universal Test and Operations Physical Inter­face forATM (UTOPIA) provides a standard that links
ATM layer orvarious management entities with a va­riety of physical (PHY) layers.

The UTOPIA IF has the following features:

■

provides clock decoupling mechanism.

■ throttles data flow from the ATM layer.

■

indicates to the ATM layer when the modem is
ready to receive data.

■ signals tothe ATM layer the presence of valid

data for transmission.

■

Recognizes the address when the modem is
selected for communication.

■ Supports octet-level and/or cell-level

handshaking.

■

UTOPIA Level 2 supports a multi-PHY
operation for up to n PHY devices where,

■

n=< 8 at ATM layers intended for 155 Mbps;

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