STL8NH3LL
N-CHANNEL 30 V - 0.012 Ω - 8 A PowerFLAT™
ULTRA LOW GATE CHARGE STripFET™ MOSFET
PRELIMINARY DATA
Table 1: Ge neral Features
TYPE V
STL8NH3LL 30 V < 0.015 Ω 8 A
■ TYPICAL R
■ IMPROVED DIE-TO-FOOTPRINT RATIO
■ VERY LOW PROFILE PACKAGE (1mm MAX)
■ VERY LOW THERMAL RESISTANCE
■ VERY LOW GATE CHARGE
■ LOW THRESHOLD DEVICE
DS
DSS
(on) = 0.012 Ω @ 10V
R
DS(on)
ID (1)
DESCRIPTION
This application specific MOSFET is the lastest
generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The Chip-scaled PowerFLAT™ package allows a significant b oard space saving, still
boosting the performance.
APPLICATIONS
■ CONTROL FET IN BUCK CONVERTER
Figure 1: Package
PowerFLAT™(3.3x3.3)
(Chip Scale Package)
Figure 2: Internal Schematic Diagram
TOP VIEW
Table 2: Order Codes
Part Number Marking Package Packaging
STL8NH3LL L8NH3LL PowerFLAT™ (3.3x3.3) TAPE & REEL
Rev 2
October 2004
This is prel i m i nary information on a new product fores een to be developed. Detai l s are subject to change wit hout notice
1/7
STL8NH3LL
Table 3: Absolute Maximum ratings
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
(1) Drain Current (continuous) at TC= 25°C (Steady State)
I
D
ID (2) Drain Current (continuous) at TC= 100°C (Steady State)
I
DM
P
TOT
P
TOT
T
stg
T
Drain-source Voltage (VGS= 0)
Drain-gate Voltage (RGS= 20 kΩ)
Gate- source Voltage ± 16 V
(3)
Drain Current (pulsed) 32 A
(1) Total Dissipation at TC= 25°C
(2) Total Dissipation at TC= 25°C (Steady State)
Derating Factor (2) 0.4 W/°C
Storage Temperature
Max. Operating Junction Temperature
j
30 V
30 V
8A
5A
50 W
1.56 W
– 55 to 150 °C
Table 4: Thermal Data
Rthj-Case Thermal Resistance Junction-Case Max 2.5 °C/W
Rthj-a (4) Thermal Operating Junction-ambient 80 °C/W
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 5: On /Off
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source Breakdown
ID = 250 µA, VGS = 0 30 V
Voltage
I
DSS
I
GSS
V
GS(th)
R
DS(on
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
Resistance
V
= Max Rating
DS
V
= Max Rating, TC = 125°C
DS
V
= ± 16 V ± 100 nA
GS
V
= VGS, ID = 250 µA 1 V
DS
= 10 V, ID = 4 A
V
GS
VGS = 4.5 V, ID = 4 A
0.012
0.0135
1
10
0.015
0.017
Table 6: Dynamic
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(5) Forward Transconductance VDS = 15V, ID= 4A TBD S
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 285 pF
Reverse Transfer
Capacitance
V
= 25V, f= 1 MHz, VGS= 0
DS
965 pF
38 pF
µA
µA
Ω
Ω
2/7
STL8NH3LL
ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Switching On
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 32 ns
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Table 8: Switching
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off-Delay Time
Fall Time
Table 9: Source Drain Diode
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (5)
t
rr
Q
rr
I
RRM
(1) The val ue is rated acco rding R
(2) The val ue is rated acco rding R
(3) Pulse width limited by safe operating area.
(4) When m ounted on minimum footprint
(5) Pulsed: Pulse duration = 300 µ s, duty cycle 1.5 %
Source-drain Current
(3)
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
thj-c
thj-a
= 15 V, ID= 4 A
DD
R
=4.7Ω, VGS = 4.5V
G
(see Figure 3)
= 15V, ID= 8 A, VGS= 4.5 V
V
DD
(see Figure 5)
VDD= 15 V, ID= 4 A,
=4.7Ω, VGS= 4.5 V
R
G
(see Figure 3)
ISD = 8 A, VGS = 0
= 8 A, di/dt = 100 A/µs
I
SD
VDD = 20V, Tj = 150°C
(see Figure 4)
15 ns
9
12 nC
3.7
3
18
8.5
8
32
1.3 V
24
17.4
1.45
nC
nC
ns
ns
A
A
ns
nC
A
3/7
STL8NH3LL
Figure 3: Switching Times Test Circuit For Resistive Load
Figure 4: Test Circuit For Diode Recovery Times
Figure 5: Gate Charge Test Circuit
4/7
PowerFLAT™ (3.3x3.3) MECHANICAL DATA
STL8NH3LL
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 0.80 0.90 1.00 0.031 0.035 0.039
A1 0.02 0.05 0.0007 0.0019
A3 0.20 0.007
b 0.23 0.30 0.38 0.009 0.011 0.015
C 0.328 0.012
C1 0.12 0.004
D 3.30 0.13
D2 2.50 2.65 2.75 0.098 0.104 0.108
E 3.30 0.13
E2 1.25 1.40 1.50 0.049 0.055 0.059
F 1.325 0.052
F1 0.975 0.038
e 0.65 0.025
L 0.30 0.50 0.011 0.019
mm. inch
5/7
STL8NH3LL
Table 10: Revision History
Date Revision Description of Change s
21-July-2004 1 First Release.
05-Oct-2004 2 Values changed
6/7
STL8NH3LL
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third par ties wh ich m ay res ul t from i ts use. N o lic ense i s gran ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
7/7
Loading...