ST STiH223 User Manual

ST STiH223 User Manual

STiH223

HD cable STB processor with integrated demodulator and low power standby controller

Data brief

Features

ST40 applications CPU with 256 KB L2 cache

16-bit LMI supporting DDR2/DDR3

Decoding of H264, MPEG2, VC-1 and AVS HD video streams

3DTV decoding and display compatible with HDMI 1.4a

Extensive connectivity (2 × USB 2.0 ports; Ethernet MII/RMII/TMII port; SD/MMC card port; eSATA port; PCI-e)

Secure boot from SLC NAND Flash or Serial NOR Flash; eMMC booting option

Low-power process and architecture

Integrated low power standby controller

High-quality video resizing and de-interlacing

Integrated Ethernet PHY

Targets two layer PCBs for cost-effective zapper STB applications

Integrates ITU-T J.83 annex B demodulation and FEC

Description

The STiH223 uses the latest process technology to provide a cost-effective, feature rich, highly integrated SoC for set-top boxes (STBs). It is targeted at the advanced decoding STB market across American and Asian cable networks that utilize the ITU-T J.83 annex B physical layer. It is suitable both for operator (with advanced security) and retail markets.

The STiH223 provides a solution for operators and manufacturers to specify a range of costeffective, high performance STBs, including basic zappers, interactive STBs, and DVR STBs with content delivery possible using broadcast or broadband networks or both (hybrid STBs).

The STiH223 integrates a high performance cable receiver, supporting reception, channel demodulation, and forward error correction (FEC) and is fully compliant with the ITU-T J.83 annex B standard.

 

 

Resets

Analog out

 

 

 

 

 

Clocks

PCM I/O

STB peripherals I/O

 

JTAG

Modes

S/PDIF out

external interrupts

 

 

 

 

 

 

 

 

System

 

 

 

 

 

 

 

 

CPU/FPU

Clock Gen

Audio I/O

Peripherals

 

 

 

System

 

 

interfaces

 

 

 

SLC NAND Flash

 

 

 

services

 

 

 

 

 

 

 

 

 

 

Dual FDMA

 

 

 

 

 

 

Serial Flash

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L2 cache

Audio decoder

 

DDR3 LMI

 

 

 

CI-Plus cards

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR2/DDR3

 

 

 

 

 

STBus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transport

Video decoder

Display

Video I/O

 

 

 

Dual USB

 

 

 

Security

 

 

 

 

 

 

 

 

 

 

 

 

 

Low power

 

 

 

 

 

 

eSATA/PCI-e

 

 

 

 

 

 

 

 

 

 

 

standby

 

 

 

 

 

 

 

 

 

 

controller

 

 

 

 

 

 

Ethernet

 

 

ITU-T J.83 annex B

 

 

Connectivity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SD-MMC/SDIO

 

 

demodulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transport streams

Transport IF in

 

Analog video

 

 

 

 

stream

 

 

 

 

 

Parallel/serial in/out

 

HDMI

 

 

 

 

March 2012

Doc ID 22935 Rev 1

1/4

For further information contact your local STMicroelectronics sales office.

www.st.com

Introduction

STiH223

 

 

1 Introduction

The STiH223 offers current users of ST’s growing family of advanced decoding ICs enhancements in performance and features, enabling operators to offer consumers new multimedia-rich services and viewing experiences, including new 3DTV features. Faster DDR3 memory is also supported, and the applications CPU benefits from an L2 cache. The STiH223 keeps pace with the latest advanced security requirements of the main CA vendors, and an integrated standby controller enables the STiH223 to target stringent low power regulations.

Features

 

Benefits

 

 

 

ST40 applications CPU, with 32KI and 32KD L1 caches and 256K L2 cache.

Integrated low power standby controller within its own power island.

Latest generation of ST's Delta video decoder coupled with a High Quality Video Display Pipeline (HQVDP).

High performance processing for applications and middleware.

Secure hibernation to, and fast resume from, very low power passive standby mode, targeting STB standby power < 0.5 W.

Decoding of advanced high definition standards (MPEG2, H264, VC-1, AVS) plus the performance and flexibility for web-based content decoding such as Flash®, DivX™, MJPEG and Real®, without impacting applications CPU performance.

Dual USB 2.0 hosts, eSATA, Ethernet MAC with MII/RMII/TMII interfaces, PCI-e, SD-MMC/SDIO interface.

Extensive high speed connectivity for the widest range of STB peripherals, such as Flash drives, external HDDs, Ethernet, home network controllers (such as MoCA®, Wi-Fi), DOCSIS® modem and memory cards.

NOCS1.0/1.1/1.2/3.0, NSK2.0 and DVB-CSA3 ready.

Integrated ITU-T J.83 annex B demodulation/FEC.

Ball compatible with other STiH2xx family variants.

Fully compliant with the latest advanced security requirements of CA vendors.

Highly integrated STB solution, reducing component count and manufacturing BOM.

Single platform versatility across all networks (satellite, cable, terrestrial, IP).

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Doc ID 22935 Rev 1

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