ST STA350BW User Manual

Download

STA350BW

2.1-channel high-efficiency digital audio system

Features

■ Wide-range supply voltage

– 5 V to 26 V (operating range) – 30 V (absolute maximum rating)

■ Four power output configurations

– 2 channels of ternary PWM (stereo mode)

(2 x 50 W into 6 Ω at 25 V)

– 3 channels - left, right using binary and LFE

using ternary PWM (2.1 mode) (2 x 18 W + 1x40W into 2x4 Ω, 1 x 8 Ω at 25 V)

– 2 channels of ternary PWM (2 x 50 W) +

stereo lineout ternary

– 1 channel of ternary PWM as mono-BTL

(1 x 90 W into 3 Ω at 24.5 V)

■ FFX

■ Selectable 32 to 192 kHz input sample rates

■ I

■ Digital gain/attenuation +42 dB to -80 dB with

™

100 dB SNR and dynamic range

C control with selectable device address

0.125 dB/step resolution

■ Soft-volume update with programmable ratio

■ Individual channel and master gain/attenuation

■ Two independent DRCs configurable as a

dual-band anti-clipper (B

DRC) or independent

limiters/compressors

■ EQ-DRC for DRC based on filtered signals

■ Dedicated LFE processing for bass boosting

with 0.125 dB/step resolution

■ Audio presets:

– 15 preset crossover filters – 5 preset anti-clipping modes – Preset nighttime listening mode

■ Individual channel and master soft/hard mute

■ Independent channel volume and DSP bypass

(a)

Sound Terminal

Datasheet − production data

PowerSSO-36

with exposed pad down (EPD)

■ Automatic zero-detect mute

■ Automatic invalid input-detect mute

■ I

S input data interface

■ Input and output channel mapping

■ Up to 8 user-programmable biquads per

channel

■ 3 coefficient banks for EQ presets storing with

fast recall via I

■ Extended coefficient dynamic up to -4..4 for

C interface

easy implementation of high shelf filters

■ Bass/treble tones and de-emphasis control

■ Selectable high-pass filter for DC blocking

■ Advanced AM interference frequency

switching and noise suppression modes

■ Selectable high or low bandwidth

noise-shaping topologies

■ Selectable clock input ratio

■ 96 kHz internal processing sample rate with

quantization error noise shaping for very low cutoff frequency filters

■ Thermal overload and short-circuit protection

embedded

■ Video apps: 576 x Fs input mode supported

■ Fully compatible with STA339BW and

STA339BWS

a. Music output power with THD = 10%, using ST’s recommended board, see Section 4:

Characterization curves for more details.

April 2012 Doc ID 018572 Rev 3 1/86

This is information on a product in full production.

www.st.com

Contents STA350BW

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15

3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16

4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Mono parallel BTL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/86 Doc ID 018572 Rev 3

STA350BW Contents

6.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

7.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.1 FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.2 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.3 Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . 40

7.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 41

7.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.4.8 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.5.3 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.4 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.5 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.6 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 43

Doc ID 018572 Rev 3 3/86

Contents STA350BW

7.5.7 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.5.8 Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.5 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.6 IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.6.7 External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.7 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 51

7.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.8 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 53

7.8.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.8.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.8.3 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.8.4 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.9 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 55

7.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.10 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 57

7.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.11.5 Limiter 1 extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 61

4/86 Doc ID 018572 Rev 3

STA350BW Contents

7.11.6 Limiter 1 extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 61

7.11.7 Limiter 2 extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 62

7.11.8 Limiter 2 extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 62

7.12 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 62

7.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.12.19 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.12.20 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.12.21 Overcurrent post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.13 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 69

7.14 Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 69

7.15 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 70

7.16 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.17 EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 71

7.18 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 72

7.18.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.18.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.18.3 Extended post-scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18.4 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18.5 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Doc ID 018572 Rev 3 5/86

Contents STA350BW

7.19 EQ soft-volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 75

7.20 DRC RMS filter coefficients (addr 0x39-0x3E) . . . . . . . . . . . . . . . . . . . . . 76

7.21 Extra volume resolution configuration registers (address 0x3F) . . . . . . . 77

7.22 Quantization error noise correction (address 0x48) . . . . . . . . . . . . . . . . . 78

7.23 Extended coefficient range up to -4...4 (address 0x49, 0x4A) . . . . . . . . . 79

7.24 Miscellaneous registers (address 0x4B, 0x4C) . . . . . . . . . . . . . . . . . . . . 80

7.24.1 Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7) . . . . . . 80

7.24.2 Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B, bit D6) 80

7.24.3 Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5) . . . . . . . 80

7.24.4 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2) . . . . . . . . 81

7.24.5 Power-down delay selector (PNDLSL[2:0]) bits

(address 0x4C, bit D4, D3, D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6/86 Doc ID 018572 Rev 3

STA350BW List of tables

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 13. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 15. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 16. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 17. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 37

Table 19. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 20. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 22. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 23. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 24. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 26. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 27. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 28. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 29. Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 30. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 31. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 32. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 33. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 34. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 35. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 36. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 37. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 38. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 39. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 40. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 41. Soft-volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 42. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 43. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 44. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 45. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 46. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 47. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 48. IC power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Doc ID 018572 Rev 3 7/86

List of tables STA350BW

Table 49. External amplifier power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 50. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 51. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 52. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 53

Table 54. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 55. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 56. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 57. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 58. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 59. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 60. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 61. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 62. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 63. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 64. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 65. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 66. Limiter attack threshold as a function of LxAT bits (AC-mode). . . . . . . . . . . . . . . . . . . . . . 60

Table 67. Limiter release threshold as a function of LxRT bits (AC-mode) . . . . . . . . . . . . . . . . . . . . 60

Table 68. Limiter attack threshold as a function of LxAT bits (DRC -mode). . . . . . . . . . . . . . . . . . . . 61

Table 69. Limiter release threshold as a as a function of LxRT bits (DRC-mode) . . . . . . . . . . . . . . . 61

Table 70. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 68

Table 71. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 72. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 73. Anti-clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 74. Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 75. Biquad filter settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 76. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 77. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8/86 Doc ID 018572 Rev 3

STA350BW List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Demonstration board, 2.0 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Mono parallel BTL schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. THD+N vs. output power (V Figure 7. THD+N vs. output power (V Figure 8. Output power vs. V Figure 9. Output power vs. V

(load = 6 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

(load = 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Efficiency vs. output power (V Figure 11. Efficiency vs. output power (V Figure 12. THD+N vs. output power (V Figure 13. Output power vs. V

(load = 3 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 14. Efficiency vs. output power (V Figure 15. Efficiency vs. output power (V

Figure 16. Left and right processing - part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 17. Processing - part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 18. Write mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 20. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 22. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 24. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 25. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 26. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 27. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 29. B

DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 30. EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 31. Extra resolution volume scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 32. Biquad filter structure with quantization error noise-shaping . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 33. Double-layer PCB with 2 copper ground areas and 24 via holes . . . . . . . . . . . . . . . . . . . 82

Figure 34. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 35. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

= 25 V, load = 6 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

= 18 V, load = 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

= 25 V, load = 6 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

= 25 V, load = 8 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

= 25 V, load = 3 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

= 26 V, load = 3 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

= 18 V, load = 3 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Doc ID 018572 Rev 3 9/86

Description STA350BW

1 Description

The STA350BW is an integrated solution of digital audio processing, digital amplifier control, and FFX-power output stage, thereby creating a high-power single-chip FFX

™

solution

comprising high-quality, high-efficiency, and all-digital amplification.

The STA350BW is based on an FFX (fully flexible amplification) processor, a proprietary technology from STMicroelectronics. FFX is the evolution and the enlargement of ST’s ternary technology: the new processor can be configured to work in ternary, binary, binary differential and phase-shift PWM modulation schemes.

The STA350BW contains the ternary, binary and binary differential implementations, a subset of the full capability of the FFX processor.

The STA350BW is part of the Sound Terminal

family that provides full digital audio streaming to the speaker, offering cost effectiveness, low power dissipation and sound enrichment.

The STA350BW power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes. 2.1 channels can be provided by two half-bridges and a single full-bridge, providing up to 2 x 18 W + 1 x 40 W of music output power, by using standard 4 and 8 Ω speakers. Two channels can be provided by two fullbridges, providing up to 2 x 50 W of music power, by using standard 6 Ω speaker or 2 x 40 W by using 8 Ω speakers at 25 V. The IC can also be configured as 2.1 channels with 2 x 40 W provided by the device and external power for FFX power drive. If configured as mono-BTL, the latter is capable of providing up to 1 x 90 W on a standard 3 Ω load or 1 x 75 W by using a 4 Ω, setting the supply voltage at 25 V. Please refer to the package thermal characteristics and application suggestions for more details.

Also provided in the STA350BW are a full assortment of digital processing features. This includes up to 8 programmable biquads (EQ) per channel. Special digital signal processing techniques are available in order to manage low-frequency quantization noise in case of very low frequency cutoff filter thresholds. The coefficient range -4..4 allows the easy implementation of high shelf filters. Available presets allow the advantage of earlier time-tomarket by substantially reducing the amount of software development needed for certain functions. This includes audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. Dual-band DRC dynamically equalizes the system to provide speaker linear frequency response regardless of output power level. This feature independently processes the two bands, controlling dynamically the output power level in each band and so providing better sound clarity.

The serial audio data input interface accepts all possible formats, including the popular I

S format. Three channels of FFX processing are provided. This high-quality conversion from PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic range.

10/86 Doc ID 018572 Rev 3

STA350BW Description

1.1 Block diagram

Figure 1. Block diagram

I2S

in t er face

Vo lu me

contr ol

PLL

FFX

I2C

Power control

Protection

cur re nt/the rm al

Log ic

Regulators

Bias

PowerDigita l DSP

Channel

Chann el

Ch anne l

Chann el

AM045167v1

Doc ID 018572 Rev 3 11/86

Pin connections STA350BW

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B/FFX3B

OUT3A/FFX3A

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN/OUT4A

EAPD/OUT4B

AM045168v1

2.2 Pin description

Table 1. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at Vcc-3.3 V

5 I/O VCC_REG Internal Vcc reference

6 O OUT2B Output half-bridge 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half-bridge 2A

10 O OUT1B Output half-bridge 1B

12/86 Doc ID 018572 Rev 3

C select address (pull-down)

STA350BW Pin connections

Table 1. Pin description (continued)

Pin Type Name Description

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half-bridge 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Parallel mode command

17 O OUT3B/FFX3B PWM out CH3B / external bridge driver

18 O OUT3A/FFX3A PWM out CH3A / external bridge driver

19 O EAPD/OUT4B Power-down for external bridge / PWM out CH4B

20 I/O TWARN/OUT4A

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

Thermal warning from external bridge (pull-up when input) / PWM out CH4A

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

28 I BICKI I

29 I LRCKI I

30 I SDI I

S serial clock

S left/right clock

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

33 I/O SDA I

34 I SCL I

C serial data

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

Doc ID 018572 Rev 3 13/86

Electrical specifications STA350BW

3 Electrical specifications

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

VDD_DIG Digital supply voltage -0.3 4 V

VDD_PLL PLL supply voltage -0.3 4

Power supply voltage (VCCxA, VCCxB) -0.3 30 V

Operating junction temperature -20 150 °C

Storage temperature -40 150 °C

stg

Warning: Stresses beyond those listed in Tabl e 2 above may cause

permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating conditions” are not implied. Exposure to AMR conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions may rise beyond the maximum operating conditions for a short time when no or very low current is sunk (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

3.2 Thermal data

Table 3. Thermal data

Symbol Parameter Min Typ Max Unit

th j-case

th-sdj

th-w

th-sdh

th j-amb

1. See Section 8: Package thermal characteristics on page 82 for details.

14/86 Doc ID 018572 Rev 3

Thermal resistance junction-case (thermal pad) 1.5 °C/W

Thermal shutdown junction temperature 150 °C

Thermal warning temperature 130 °C

Thermal shutdown hysteresis 20 °C

Thermal resistance junction-ambient

(1)

STA350BW Electrical specifications

3.3 Recommended operating conditions

Table 4. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

Power supply voltage (VCCxA, VCCxB) 5 26 V

VDD_DIG Digital supply voltage 2.7 3.3 3.6 V

VDD_PLL PLL supply voltage 2.7 3.3 3.6 V

Ambient temperature -20 +85 °C

amb

3.4 Electrical specifications for the digital section

Table 5. Electrical specifications - digital section

Symbol Parameter Conditions Min Typ Max Unit

Low-level input current without

pull-up/down device

High-level input current without

pull-up/down device

Low-level input voltage

High-level input voltage

Low-level output voltage Iol=2 mA

High-level output voltage Ioh=2 mA

Pull-up/down current 25 66 125 µA

Equivalent pull-up/down

resistance

Vi = 0 V 1 5 µA

Vi = VDD_DIG = 3.6 V

0.8 *

VDD_DIG

0.8 *

VDD_DIG

15µA

0.2 *

VDD_DIG

0.4 *

VDD_DIG

50 kΩ

Doc ID 018572 Rev 3 15/86

Electrical specifications STA350BW

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC=24V, f=1kHz, f

Table 6. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

= 384 kHz, T

= 25° C and RL = 8 Ω, unless otherwise specified.

amb

Continuous output power, BTL, ternary mode

THD = 1% 27

THD = 10% 36

THD = 1% 12

THD = 10% 15.5

= 1.5 A 180 250 mΩ

dsON

Continuous output power SE, binary

RL = 4 Ω

mode,

Power Pchannel/Nchannel MOSFET (total bridge)

Idss Power Pchannel/Nchannel leakage VCC = 20 V 10 μA

LDT

HDT

Low current dead time (static) Resistive load

High current dead time (dynamic) I load

Rise time Resistive load

Fall time Resistive load

Supply voltage operating voltage 5 26 V

(1)

8 15 ns

= 1.5 A 15 30 ns

(1)

10 18 ns

Supply current from Vcc in power-down PWRDN = 0 1 μA

PCM input signal

vcc

Supply current from Vcc in operation

= -60 dBfs, Switching frequency

52 60 mA

= 384 kHz, No LC filters

vdd

Supply current FFX processing (reference only)

Ilim Overcurrent limit

Internal clock =

49.152 MHz

(2)

55 70 mA

3.0 3.8 4.0 A

Isc Short-circuit protection Hi-Z output 4.0 5.0 A

UVL Undervoltage protection 4.3 V

OVP Overvoltage protection 29 V

min

Output minimum pulse width No load 100 ns

DR Dynamic range 100 dB

Signal-to-noise ratio, ternary mode A-Weighted 100 dB

SNR

Signal-to-noise ratio binary mode 90 dB

FFX stereo mode,

THD+N Total harmonic distortion + noise

Po = 1 W

0.09 %

f=1kHz

16/86 Doc ID 018572 Rev 3

STA350BW Electrical specifications

Table 6. Electrical specifications - power section (continued)

Symbol Parameter Conditions Min Typ Max Unit

FFX stereo mode, <5 kHz

TA L K

Crosstalk

PSRR Power Supply Rejection Ratio

Peak efficiency, FFX mode

Peak efficiency, binary modes

1. Refer to Figure 3: Test circuit.

2. Limit current if the register (OCRB Section 7.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled refer to the Isc.

One channel driven at 1 W

Other channel measured

FFX stereo mode, <5 kHz

VRipple01V RMS Audio input = dither

only

Po = 2 x 25 W into 8 Ω

Po = 2 x 10W into 4Ω + 1 x 20W into 8 Ω

80 dB

Figure 3. Test circuit

Low cu rrent dea d tim e = M A X (tr,tf)

D u ty cycle = 50%

INx Y

GND

+VCC

OUTxY

tr tf

R= 8

vdc = VCC/2

VCC

0.9*VCC

VCC/2

0.1*VCC

AM045169v1

Doc ID 018572 Rev 3 17/86

Characterization curves STA350BW

4 Characterization curves

The following characterization curves were made using the STA350BW demonstration board with 2.0 channels (refer to the schematic in Figure 6) under the following test conditions:

= 25 V, f = 1 kHz, fSW = 384 kHz, Tamb = 25 °C and RL = 6 Ω, unless otherwise

specified.

Figure 4. Demonstration board, 2.0 channels

18/86 Doc ID 018572 Rev 3

AM045290v1

STA350BW Characterization curves

Figure 5. Mono parallel BTL schematic

AM045170v1

Doc ID 018572 Rev 3 19/86

Characterization curves STA350BW

Figure 6. THD+N vs. output power (VCC = 25 V, load = 6 Ω)

0.5

0.2

0.1

0.05

0.02

0.01 1m 1002m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50

Figure 7. THD+N vs. output power (V

Vcc=25V , Load = 6Ω, Freq= 1KHz

= 18 V, load = 8 Ω)

AM045171v1

0.5

0.2

0.1

0.05

0.02

0.01 1m 502m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20

Vcc=18V , Load = 8Ω,

Freq= 1KHz

AM045172v1

20/86 Doc ID 018572 Rev 3

STA350BW Characterization curves

Figure 8. Output power vs. V

+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24

Load= 6 Ω, Freq=1KHz

Figure 9. Output power vs. V

(load = 6 Ω)

(load = 8 Ω)

THD = 10%

Vdc

THD = 1%

AM045173v1

Load= 8 Ω, Freq=1KHz

THD = 10%

THD = 1%

+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24

Vdc

AM045174v1

Doc ID 018572 Rev 3 21/86

Characterization curves STA350BW

Figure 10. Efficiency vs. output power (VCC = 25 V, load = 6 Ω)

+0.9

+0.8

+0.7

+0.6

η %

+0.5

+0.4

Vcc= 25V, Load= 6 Ω, Freq=1KHz

+0.3

+0.2

+0.1

5 5510 15 20 25 30 35 40 45 50

Figure 11. Efficiency vs. output power (V

+0.9

+0.8

+0.7

+0.6

η %

+0.5

+0.4

Vcc= 25V, Load= 8 Ω, Freq=1KHz

+0.3

+0.2

+0.1

5 4510 15 20 25 30 35 40

= 25 V, load = 8 Ω)

AM045175v1

AM045176v1

22/86 Doc ID 018572 Rev 3

STA350BW Characterization curves

4.1 Mono parallel BTL characteristics

Figure 12. THD+N vs. output power (VCC = 25 V, load = 3 Ω)

Vcc=25V Load= 3 Ω,

0.5

0.2

0.1

0.05

0.02

0.01 1m 1002m 5m 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50

Figure 13. Output power vs. V

110

100

Load= 3 Ω, Freq=1KHz

(load = 3 Ω)

Freq=1KHz

THD=10%

AM045177v1

+6 +26+8 +10 +12 +14 +16 +18 +20 +22 +24

Vdc

THD=1%

AM045178v1

Doc ID 018572 Rev 3 23/86

Characterization curves STA350BW

Figure 14. Efficiency vs. output power (VCC = 26 V, load = 3 Ω)

+0.9

+0.8

+0.7

+0.6

+0.5

η %

+0.4

+0.3

Vcc= 26V Load= 3 Ω, Freq=1KHz

+0.2

+0.1

10 11020 30 40 50 60 70 80 90 100

Figure 15. Efficiency vs. output power (V

+0.9

+0.8

+0.7

+0.6

+0.5

η %

+0.4

+0.3

Vcc=18V Load= 3 Ω, Freq=1KHz

+0.2

+0.1

5 5010 15 20 25 30 35 40 45

= 18 V, load = 3 Ω)

AM045179v1

AM045180v1

24/86 Doc ID 018572 Rev 3

STA350BW Processing data paths

5 Processing data paths

Figure 16 and 17 illustrate the data processing paths inside the STA350BW.

The whole processing chain is composed of two consecutive sections. In the first one dualchannel processing is implemented, as described below, and then each channel is fed into the post-mixing block allowing to generate either a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the dual-band DRC block (2.0 output configuration with crossover filters used to define the cutoff frequency of the two bands).

The first section begins with a 2x oversampling FIR filter allowing for 2*Fs audio processing. Then a selectable high-pass filter removes the DC level (enabled if HFB=0).

The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).

By default 4 independent filters per channel are enabled, plus the pre-configured DeEmphasis, Bass and Treble controls (BQL=0, BQ5=0, BQ6=0, BQ7=0).

If the coefficient sets are linked (BQL=1) it’s then possible to use De-Emphasis, Bass and Treble filter in a user-defined configuration (provided the relevant BQx bits are set). In other words both channels will use the same processing coefficients and can have up to 7 filters each. Note that if BQL=0 the BQx bits are ignored and the 5th, 6th and 7th filters are configured as, respectively, De-Emphasis, Bass and Treble controls.

Moreover the common 8th filter, from the subsequent processing section, can be available on both channels (provided the pre-defined crossover frequencies are not used, XO[3:0]=0, and the dual-band DRC is not used).

In the second section mixing and crossover filters are available. If B (Figure 17), they are fully user-programmable and allow generating a third channel (2.1 outputs). Alternatively, in B

DRC mode, those blocks will be used to split the sub-band and

DRC is not enabled

define the cutoff frequencies of the two bands. A prescaler and a final post scaler allow full control over the signal dynamic respectively before and after the filtering stages. A mixer function is also available.

Figure 16. Left and right processing - part 1

Sampling

frequency=Fs

From

From I2S input

I2S input interface

interface

FIR

over

FIR

sampling

over

FIR

over

FIR

sampling

over

Sampling

frequency=2xFs

PreScale

Hi-Pass

Filter

If HPB=0

Hi-Pass

Filter

If HPB=0

Biquad#1Biquad#2Biquad#3Biquad

User Defined Filters

If DSPB=0 and C1EQBP=0

Biquad#1Biquad#2Biquad#3Biquad

User Defined Filters

If DSPB=0 and C2EQBP=0

If BQ5=1

and BQL=1

Biquad

De-Emph.

If DEMP=0

If BQ5=1

and BQL=1

Biquad

De-Emph.

If DEMP=0

IF BQ7=1

If BQ6=1

and BQL=1

Biquad

Bass Treble

If C1TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut

If BQ6=1

IF BQ7=1

and BQL=1

Biquad

Bass Treble

If C2TCB=0 BTC: Bass Boost/Cut TTC: Treble Boost/Cut

AM045181v1

Doc ID 018572 Rev 3 25/86

Processing data paths STA350BW

Figure 17. Processing - part 2

Dual-band DRC enabled

C1Mx1

C1Mx1=

0x7fffff

C1Mx2

C1Mx2= 0x00000

C2Mx1

C2Mx1= 0x000000

C2Mx2

C2Mx2= 0x7fffff

C3Mx1

C3Mx1= 0x40000

C3Mx2

C3Mx2= 0x400000

User-Defined Mix Coefficients

Dual-band DRC disabled

C1Mx1

C1Mx2

Hi-Pass XO

B2DRC

Filter

Hi-pass

Hi-Pass XO

B2DRC Hi-pass

Crossover Frequency determined by XO Setting User Defined If XO=0000

User Defined If XO=0000

filter

Filter

filter

Channel ½

Hi-Pass XO

Biquad#5

Filter

--------------

Hi-pass XO

filter

CH3

Volume

CH1

Volume

CH2

Volume

CH3

Volume

DRC2

DRC1

Vol

Vol And

And

Limiter

Vol

And

Limiter

DRC2

Post scale

Post scale Post scale

Post scale

C2Mx1

C2Mx2

C3Mx1

C3Mx2

User-Defined Mix Coefficients

Channel ½

Hi-Pass XO

Biquad#5

Filter

--------------

Hi-pass XO

filter

Channel 3

Lo-Pass XO

Biquad

Filter

--------------

Low-pass XO

filter

Crossover Frequency determined by XO Setting User Defined If XO=0000

User Defined If XO=0000

26/86 Doc ID 018572 Rev 3

Vol

Vol And

And

Limiter

Vol

Vol And

And

Limiter

Post scale

B2DRC Disabled

AM045182v1

STA350BW I2C bus specification

6 I2C bus specification

The STA350BW supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides data to the serial clock for synchronization. The STA350BW is always a slave device in all of its communications. It supports up to 400 kb/sec rate (fast-mode bit rate). The STA350BW I interface works properly only in the case that the master clock generated by the PLL has a frequency 10 times higher compared to the frequency of the applied SCL signal.

6.1 Communication protocol

6.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. An SDA transition while the clock is high is used to identify a START or STOP condition.

C is a slave-only interface. The I2C

6.1.2 Start condition

START is identified by a high-to-low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.

6.1.3 Stop condition

STOP is identified by a low-to-high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between the STA350BW and the bus master.

6.1.4 Data input

During data input the STA350BW samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

6.2 Device addressing

To start communication between the master and the STA350BW, the master must initiate a start condition. Following this, the master sends 8 bits (MSB first) corresponding to the device select address and read or write mode to the SDA line.

The seven most significant bits are the device address identifiers, corresponding to the I bus definition. In the STA350BW the I the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

C interface has two device addresses depending on

The eighth bit (LSB) identifies the read or write operation RW, this bit is set to 1 in read mode and to 0 for write mode. After a START condition the STA350BW identifies on the bus the device address and if a match is found, it acknowledges the identification on the SDA

Doc ID 018572 Rev 3 27/86

I2C bus specification STA350BW

bus during the 9th bit time. The byte following the device identification byte is the internal space address.

6.3 Write operation

Following the START condition the master sends a device select code with the RW bit set to 0. The STA350BW acknowledges this and then writes the byte of the internal address. After receiving the internal byte address the STA350BW again responds with an acknowledgement.

6.3.1 Byte write

In the byte write mode the master sends one data byte which is acknowledged by the STA350BW. The master then terminates the transfer by generating a STOP condition.

6.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.

6.4 Read operation

6.4.1 Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA350BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

6.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA350BW. The master acknowledges each data byte read and then generates a STOP condition, terminating the transfer.

6.4.3 Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA350BW acknowledges this and then the master writes the internal address byte. After receiving the internal byte address, the STA350BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA350BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

6.4.4 Random address multi-byte read

28/86 Doc ID 018572 Rev 3

STA350BW I2C bus specification

6.4.5 Write mode sequence

Figure 18. Write mode sequence

BYTE

WRITE

MULTIBYTE

WRITE

START RW

START

DEV-ADDR

6.4.6 Read mode sequence

Figure 19. Read mode sequence

ACK

RW=

RW= HIGH

HIGH

ACK

CURRENT

ADDRESS

READ

RANDOM

RANDOM ADDRESS

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

DEV-ADDR

START RW

DEV-ADDR

START

DEV-ADDR

START

DEV-ADDR

START RW

ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

NO ACK

STOP

ACK

DATA

ACK

DEV-ADDR

WRTRATS

DATA IN

ACK

DATA

ACK

NO ACK

ACK

STOP

DATA

DATA IN

ACK

STOP

AM045183v1

ACK NO ACK

DATA

AM045184v1

STOP

Doc ID 018572 Rev 3 29/86

7 Register description

Table 7. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

0x01 CONFB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

0x02 CONFC OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x03 CONFD SME ZDE DRC BQL PSL DSPB DEMP HPB

0x04 CONFE SVE ZCE DCCV PWMS AME NSBW MPC MPCV

0x05 CONFF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

0x06 MUTE/LOC LOC1 LOC0 Reserved Reserved C3M C2M C1M MMUTE

0x07 MVOL MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

0x08 C1VOL C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

0x09 C2VOL C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

0x0A C3VOL C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

0x0B AUTO1 Reserved Reserved AMGC1 AMGC0 Reserved Reserved Reserved Reserved

0x0C AUTO2 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

0x0D AUTO3 Reserved

0x0E C1CFG C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

0x0F C2CFG C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

0x10 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

0x11 TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0x12 L1AR L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x13 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x14 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x15 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0x16 CFADDR Reserved Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

0x17 B1CF1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0x18 B1CF2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

0x19 B1CF3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

0x1A B2CF1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0x1B B2CF2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0x1C B2CF3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

0x1D A1CF1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

0x1E A1CF2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0x1F A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

0x20 A2CF1

0x21 A2CF2

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

30/86 Doc ID 018572 Rev 3

STA350BW Register description

Table 7. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x22 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

0x23 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x24 B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

0x25 B0CF3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

0x26 CFUD Reserved RA R1 WA W1

0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0x2D STATUS PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN

0x2E Reserved Reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT

0x2F Reserved Reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND

0x30 Reserved Reserved R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD

0x31 EQCFG XOB Reserved Reserved AMGC3 AMGC2 Reserved SEL1 SEL0

0x32 EATH1 EATHEN1 EATH1[6] EATH1[5] EATH1[4] EATH1[3] EATH1[2] EATH1[1] EATH1[0]

0x33 ERTH1 ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

0x34 EATH2 EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0]

0x35 ERTH2 ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

0x36 CONFX MDRC[1] MDRC[0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

0x37 SVCA Reserved Reserved SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0]

0x38 SVCB Reserved Reserved SVDWE SVDW[4] SVDW[3] SVDW[2] SVDW[1] SVDW[0]

0x39 RMS0A R_C0[23] R_C0[22] R_C0[21] R_C0[20] R_C0[19] R_C0[18] R_C0[17] R_C0[16]

0x3A RMS0B R_C0[15] R_C0[14] R_C0[13] R_C0[12] R_C0[11] R_C0[10] R_C0[9] R_C0[8]

0x3B RMS0C R_C0[7] R_C0[6] R_C0[5] R_C0[4] R_C0[3] R_C0[2] R_C0[1] R_C0[0]

0x3C RMS1A R_C1[23] R_C1[22] R_C1[21] R_C1[20] R_C1[19] R_C1[18] R_C1[17] R_C1[16]

0x3D RMS1B R_C1[15] R_C1[14] R_C1[13] R_C1[12] R_C1[11] R_C1[10] R_C1[9] R_C1[8]

0x3E RMS1C R_C1[7] R_C1[6] R_C1[5] R_C1[4] R_C1[3] R_C1[2] R_C1[1] R_C1[0]

0x3F EVOLRES VRESEN VRESTG C3VR[1] C3VR[0] C2VR[1] C2VR[0] C1VR[1] C1VR[0]

0x40 Reserved

0x41 Reserved

0x42 Reserved

0x43 Reserved

0x44 Reserved

0x45 Reserved

0x46 Reserved

Doc ID 018572 Rev 3 31/86

Table 7. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x47 Reserved

0x48 NSHAPE NSHXEN NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN

0x49 CXT[B4B1] CXTB4[1] CXTB4[0] CXTB3[1] CXTB3[0] CXTB2[1] CXTB2[0] CXTB1[1] CXTB1[0]

0x4A CXT[B7B5] Reserved Reserved CXTB7[1] CXTB7[0] CXTB6[1] CXTB6[0] CXTB5[1] CXTB5[0]

0x4B MISC1 RPDNEN NSHHPEN BRIDGOFF Reserved Reserved CPWMEN Reserved Reserved

0x4C MISC2 Reserved Reserved Reserved PNDLSL[2] PNDLSL[1] PNDLSL[0] Reserved Reserved

0x4D Reserved

0x4E Reserved

0x4F Reserved

0x50 Reserved

0x51 Reserved

0x52 Reserved

0x53 Reserved

0x54 Reserved

NSHB1E N

0x55 Reserved

0x56 Reserved

32/86 Doc ID 018572 Rev 3

STA350BW Register description

7.1 Configuration register A (addr 0x00)

D7 D6 D5 D4 D3 D2 D1 D0

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

01100011

7.1.1 Master clock select

Table 8. Master clock select

Bit R/W RST Name Description

0R/W 1 MCS0

1R/W 1 MCS1

Selects the ratio between the input I frequency and the input clock.

S sample

2R/W 0 MCS2

The STA350BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

● 32.768 MHz for 32 kHz

● 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

● 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (f

The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally.

Table 9. Input sampling rates

Input sample rate

fs (kHz)

IR MCS[2:0]

101 100 011 010 001 000

32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

Doc ID 018572 Rev 3 33/86

7.1.2 Interpolation ratio select

Table 10. Internal interpolation ratio

Bit R/W RST Name Description

4:3 R/W 00 IR [1:0]

Selects internal interpolation ratio based on input I sample frequency

The STA350BW has variable interpolation (oversampling) settings such that internal processing and FFX output rates remain consistent. The first processing block interpolates by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits.

Table 11. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1st stage interpolation ratio

32 00 2 times oversampling

44.1 00 2 times oversampling

48 00 2 times oversampling

88.2 01 Pass-through

96 01 Pass-through

176.4 10 2 times downsampling

192 10 2 times downsampling

7.1.3 Thermal warning recovery bypass

Table 12. Thermal warning recovery bypass

Bit R/W RST Name Description

5R/W 1 TWRB

0: Thermal warning recovery enabled 1: Thermal warning recovery disabled

If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative.

If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset.

7.1.4 Thermal warning adjustment bypass

Table 13. Thermal warning adjustment bypass

Bit R/W RST Name Description

6R/W 1 TWAB

0: Thermal warning adjustment enabled 1: Thermal warning adjustment disabled

34/86 Doc ID 018572 Rev 3

STA350BW Register description

The on-chip STA350BW power output block provides feedback to the digital controller using inputs to the power control block. Input TWARN is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block forces a -3 dB output limit (determined by TWOCL in the coefficient RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0.

7.1.5 Fault detect recovery bypass

Table 14. Fault detect recovery bypass

Bit R/W RST Name Description

7R/W 0 FDRB

0: fault detect recovery enabled 1: fault detect recovery disabled

The on-chip STA350BW power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29-0x2A), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1.

7.2 Configuration register B (addr 0x01)

D7 D6 D5 D4 D3 D2 D1 D0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

10000000

7.2.1 Serial audio input interface format

Table 15. Serial audio input interface

Bit R/W RST Name Description

0 R/W 0 SAI0

1 R/W 0 SAI1

2 R/W 0 SAI2

3 R/W 0 SAI3

Doc ID 018572 Rev 3 35/86

Determines the interface format of the input serial digital audio interface.

7.2.2 Serial data interface

The STA350BW audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. The STA350BW always acts as the slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 and 2 SDI12.

The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format. The default serial data format is I that follow.

7.2.3 Serial data first bit

Table 16. Serial data first bit

SAIFB Format

0 MSB-first

1 LSB-first

Table 17. Support serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB Interface format

32 * fs

48 * fs

S, MSB-first. Available formats are shown in the tables

0000 0 I

S 15-bit data

0001 0 Left/right-justified 16-bit data

0000 0 I

S 16 to 23-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

0000 0 I2S 16 to 24-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

64 * fs

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

36/86 Doc ID 018572 Rev 3

STA350BW Register description

Table 18. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI SAI [3:0] SAIFB Interface format

32 * fs

1100 1 I

1110 1 Left/right-justified 16-bit data

0100 1 I

1000 1 I

1100 1 LSB first I

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

48 * fs

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

S 15-bit data

S 23-bit data

S 20-bit data

S 18-bit data

S 16-bit data

0000 1 I2S 24-bit data

0100 1 I

1000 1 I

1100 1 LSB first I

S 20-bit data

S 18-bit data

S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

64 * fs

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

To make the STA350BW work properly, the serial audio interface LRCKI clock must be synchronous to the PLL output clock. It means that:

■ the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,

where N depends on the settings in Table 11 on page 34

■ the PLL must be locked.

If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the STA350BW will immediately mute the I

S PCM data out (provided to the processing block)

and it will freeze any active processing task.

Doc ID 018572 Rev 3 37/86

To avoid any audio side effects (like pop noise), it is strongly recommended to soft-mute any audio streams flowing into the STA350BW data path before the desynchronization event happens. At the same time any processing related to the I

C configuration should be issued

only after the serial audio interface and the internal PLL are synchronous again.

Note: Any mute or volume change causes some delay in the completion of the I

C operation due to the soft-volume feature. The soft-volume phase change must be finished before any clock desynchronization.

7.2.4 Delay serial clock enable

Table 19. Delay serial clock enable

Bit R/W RST Name Description

0: No serial clock delay

5R/W 0 DSCKE

1: Serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices

7.2.5 Channel input mapping

Table 20. Channel input mapping

Bit R/W RST Name Description

6R/W 0 C1IM

7R/W 1 C2IM

0: Processing channel 1 receives Left I 1: Processing channel 1 receives Right I

0: Processing channel 2 receives Left I 1: Processing channel 2 receives Right I2S Input

S Input

Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I

S input channel to its corresponding processing

channel.

38/86 Doc ID 018572 Rev 3

STA350BW Register description

7.3 Configuration register C (addr 0x02)

D7 D6 D5 D4 D3 D2 D1 D0

OCRB CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

1 011111

7.3.1 FFX power output mode

Table 21. FFX power output mode

Bit R/W RST Name Description

0R/W 1 OM0

Selects configuration of FFX output.

1R/W 1 OM1

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

Table 22. Output modes

OM[1,0] Output stage mode

00 Drop compensation

01 Discrete output stage - tapered compensation

10 Full power mode

11 Variable drop compensation (CSZx bits)

7.3.2 FFX compensating pulse size register

Table 23. FFX compensating pulse size bits

Bit R/W RST Name Description

2R/W 1 CSZ0

3R/W 1 CSZ1

4R/W 1 CSZ2

5R/W 0 CSZ3

When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock ticks.

Table 6:

Table 24. Compensating pulse size

CSZ[3:0] Compensating pulse size

0000 0 ns (0 tick) compensating pulse size

0001 20 ns (1 tick) clock period compensating pulse size

……

1111 300 ns (15 tick) clock period compensating pulse size

Doc ID 018572 Rev 3 39/86

7.3.3 Overcurrent warning detect adjustment bypass

Table 25. Overcurrent warning bypass

Bit R/W RST Name Description

7 R/W 1 OCRB

0: Overcurrent warning adjustment enabled 1: Overcurrent warning adjustment disabled

The OCWARN input is used to indicate an overcurrent warning condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains in this state until a reset occurs. The level of adjustment can be changed via the TWOCL (thermal warning/over current limit) setting which is address 0x37 of the user-defined coefficient RAM.

7.4 Configuration register D (addr 0x03)

D7 D6 D5 D4 D3 D2 D1 D0

SME ZDE DRC BQL PSL DSPB DEMP HPB

01000000

7.4.1 High-pass filter bypass

Table 26. High-pass filter bypass

Bit R/W RST Name Description

0R/W 0 HPB

Setting of one bypasses internal AC coupling digital high-pass filter

The STA350BW features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC signals can cause speaker damage. When HPB = 0, this filter is enabled.

7.4.2 De-emphasis

Table 27. De-emphasis

Bit R/W RST Name Description

1R/W 0 DEMP

40/86 Doc ID 018572 Rev 3

0: No de-emphasis 1: Enable de-emphasis on all channels

STA350BW Register description

7.4.3 DSP bypass

Table 28. DSP bypass

Bit R/W RST Name Description

2 R/W 0 DSPB

Setting the DSPB bit to 1 bypasses the EQ function of the STA350BW.

7.4.4 Post-scale link

Table 29. Post-scale link

Bit R/W RST Name Description

3 R/W 0 PSL

Post-scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and to update the values faster.

7.4.5 Biquad coefficient link

Table 30. Biquad coefficient link

Bit R/W RST Name Description

4R/W 0 BQL

0: Normal operation 1: Bypass of biquad and bass/treble functions

0: Each channel uses individual post-scale value 1: Each channel uses channel 1 post-scale value

0: Each channel uses coefficient values 1: Each channel uses channel 1 coefficient values

For ease of use, all channels can use the biquad coefficients loaded into the Channel-1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once.

7.4.6 Dynamic range compression/anti-clipping bit

Table 31. Dynamic range compression/anti-clipping bit

Bit R/W RST Name Description

5 R/W 0 DRC

Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level.

Doc ID 018572 Rev 3 41/86

0: Limiters act in anti-clipping mode 1: Limiters act in dynamic range compression mode

7.4.7 Zero-detect mute enable

Table 32. Zero-detect mute enable

Bit R/W RST Name Description

6 R/W 1 ZDE Setting of 1 enables the automatic zero-detect mute

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled.

7.4.8 Submix mode enable

Table 33. Submix mode enable

Bit R/W RST Name Description

7R/W 0 SME

0: Sub Mix into Left/Right disabled 1: Sub Mix into Left/Right enabled

7.5 Configuration register E (addr 0x04)

D7 D6 D5 D4 D3 D2 D1 D0

SVE ZCE DCCV PWMS AME NSBW MPC MPCV

11000010

7.5.1 Max power correction variable

Table 34. Max power correction variable

Bit R/W RST Name Description

0R/W 0 MPCV

7.5.2 Max power correction

Table 35. Max power correction

Bit R/W RST Name Description

0: Use standard MPC coefficient 1: Use MPCC bits for MPC coefficient

1R/W 1 MPC

Setting of 1 enables power bridge correction for THD reduction near maximum power output.

Setting the MPC bit turns on special processing that corrects the STA350BW power device at high power. This mode should lower the THD+N of a full FFX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the lineout channels.

42/86 Doc ID 018572 Rev 3

STA350BW Register description

7.5.3 Noise-shaper bandwidth selection

Table 36. Noise-shaper bandwidth selection

Bit R/W RST Name Description

2 R/W 0 NSBW

7.5.4 AM mode enable

Table 37. AM mode enable

Bit R/W RST Name Description

3R/W 0 AME

The STA350BW features an FFX processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when FFX is operating in a device with an AM tuner active. The SNR of the FFX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio.

7.5.5 PWM speed mode

Table 38. PWM speed mode

Bit R/W RST Name Description

4R/W 0 PWMS

1: Third order NS 0: Fourth order NS

0: Normal FFX operation 1: AM reduction mode FFX operation

0: Normal speed (384 kHz) all channels 1: Odd speed (341.3 kHz) all channels

7.5.6 Distortion compensation variable enable

Table 39. Distortion compensation variable enable

Bit R/W RST Name Description

5R/W 0 DCCV

0: Use preset DC coefficient 1: Use DCC coefficient

7.5.7 Zero-crossing volume enable

Table 40. Zero-crossing volume enable

Bit R/W RST Name Description

6R/W 1 ZCE

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings, no clicks are audible.

Doc ID 018572 Rev 3 43/86

1: Volume adjustments only occur at digital zero-crossings 0: Volume adjustments occur immediately

7.5.8 Soft-volume update enable

Table 41. Soft-volume update enable

Bit R/W RST Name Description

7R/W 1 SVE

1: Volume adjustments ramp according to SVR settings 0: Volume adjustments occur immediately

7.6 Configuration register F (addr 0x05)

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

01011100

7.6.1 Output configuration

Table 42. Output configuration

Bit R/W RST Name Description

0 R/W 0 OCFG0 1 R/W 0 OCFG1

Selects the output configuration

Table 43. Output configuration engine selection

OCFG[1:0] Output configuration Config pin

2-channel (full-bridge) power, 2-channel data-out: 1A/1B → 1A/1B

2A/2B → 2A/2B LineOut1 → 3A/3B LineOut2 → 4A/4B Line Out Configuration determined by LOC register

2(half-bridge).1(full-bridge) on-board power: 1A → 1A Binary 0 °

2A → 1B Binary 90° 3A/3B → 2A/2B Binary 45° 1A/B → 3A/B Binary 0° 2A/B → 4A/B Binary 90°

2 Channel (Full-Bridge) Power, 1 Channel FFX: 1A/1B → 1A/1B

2A/2B → 2A/2B 3A/3B → 3A/3B EAPDEXT and TWARNEXT Active

1 Channel Mono-Parallel: 3A → 1A/1B w/ C3BO 45°

3B → 2A/2B w/ C3BO 45° 1A/1B → 3A/3B 2A/2B → 4A/4B

Note: To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

44/86 Doc ID 018572 Rev 3

STA350BW Register description

Figure 20. OCFG = 00 (default value)

OUT1A

Half

Bridge

Channel 1

LPF

Channel 1

Channel 2

LineOut1

LineOut2

Half

Bridge

Half

Bridge

Half

Bridge

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

AM045185v1

Figure 21. OCFG = 01

Half

Bridge

OUT1A

Channel 1

Figure 22. OCFG = 10

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

EAPD

Power

Device

OUT1B

OUT2A

OUT2B

Channel 1

Channel 2

Channel 3

Channel 2

Channel 3

AM045186v1

AM045187v1

Doc ID 018572 Rev 3 45/86

Figure 23. OCFG = 11

OUT1A

Half

Bridge

OUT1B

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

OUT1B

OUT2A

Channel 1

Channel 2

Channel 3

AM045188v1

Half

Bridge

Half

Bridge

Half

Bridge

The STA350BW can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The PWM slot defines the maximum extension for the PWM rising and falling edge, that is, the rising edge as well as the falling edge cannot range outside the PWM slot boundaries.

Figure 24. Output mapping scheme

FFX1A

FFX1 B

FFX2 A

FFX ™

modulator

FFX 2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

REMAP

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

Power

Power Bridge

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage.

46/86 Doc ID 018572 Rev 3

AM045189v1

STA350BW Register description

2.0 channels, two full bridges (OCFG = 00)

● FFX1A -> OUT1A

● FFX1B -> OUT1B

● FFX2A -> OUT2A

● FFX2B -> OUT2B

● FFX3A -> OUT3A

● FFX3B -> OUT3B

● FFX4A -> OUT4A

● FFX4B -> OUT4B

● FFX1A/1B configured as ternary

● FFX2A/2B configured as ternary

● FFX3A/3B configured as lineout ternary

● FFX4A/4B configured as lineout ternary

On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 25.

Figure 25. 2.0 channels (OCFG = 00) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

AM045190v1

Doc ID 018572 Rev 3 47/86

2.1 channels, two half-bridges + one full-bridge (OCFG = 01)

● FFX1A -> OUT1A

● FFX2A -> OUT1B

● FFX3A -> OUT2A

● FFX3B -> OUT2B

● FFX1A -> OUT3A

● FFX1B -> OUT3B

● FFX2A -> OUT4A

● FFX2B -> OUT4B

● FFX1A/1B configured as binary

● FFX2A/2B configured as binary

● FFX3A/3B configured as binary

● FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4 channels the channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 26.

Figure 26. 2.1 channels (OCFG = 01) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

AM045191v1

48/86 Doc ID 018572 Rev 3

STA350BW Register description

2.1 channels, two full-bridge + one external full-bridge (OCFG = 10)

● FFX1A -> OUT1A

● FFX1B -> OUT1B

● FFX2A -> OUT2A

● FFX2B -> OUT2B

● FFX3A -> OUT3A

● FFX3B -> OUT3B

● EAPD -> OUT4A

● TWARN -> OUT4B

● FFX1A/1B configured as ternary

● FFX2A/2B configured as ternary

● FFX3A/3B configured as ternary

● FFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the external bridge control signals are muxed.

In this configuration the PWM slot phase is the following as shown in Figure 27.

Figure 27. 2.1 channels (OCFG = 10) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

AM045192v1

Doc ID 018572 Rev 3 49/86

7.6.2 Invalid input detect mute enable

Table 44. Invalid input detect mute enable

Bit R/W RST Name Description

2 R/W 1 IDE Setting of 1 enables the automatic invalid input detect mute

Setting the IDE bit enables this function, which looks at the input I2S data and automatically mutes if the signals are perceived as invalid.

7.6.3 Binary output mode clock loss detection

Table 45. Binary output mode clock loss detection

Bit R/W RST Name Description

3 R/W 1 BCLE Binary output mode clock loss detection enable

The BCLE bit detects loss of input MCLK in binary mode and will output 50% duty cycle.

7.6.4 LRCK double trigger protection

Table 46. LRCK double trigger protection

Bit R/W RST Name Description

4 R/W 1 LDTE LRCLK double trigger protection enable

The LDTE bit actively prevents double triggering of the LRCLK.

7.6.5 Auto EAPD on clock loss

Table 47. Auto EAPD on clock loss

Bit R/W RST Name Description

5 R/W 0 ECLE Auto EAPD on clock loss

When active, the ECLE bit issues a power device power-down signal (EAPD) on clock loss detection.

7.6.6 IC power-down

Table 48. IC power-down

Bit R/W RST Name Description

7R/W 1 PWDN

0: IC power-down low-power condition 1: IC normal operation

The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

50/86 Doc ID 018572 Rev 3

STA350BW Register description

to power down the power-stage, then the master clock to all internal hardware except the

C block is gated. This places the IC in a very low power consumption state.

7.6.7 External amplifier power-down

Table 49. External amplifier power-down

Bit R/W RST Name Description

7 R/W 0 EAPD

0: External power stage power down active 1: Normal operation

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This register also controls the FFX4B/EAPD output pin when OCFG = 10.

7.7 Volume control registers (addr 0x06 - 0x0A)

7.7.1 Mute/line output configuration register

D7 D6 D5 D4 D3 D2 D1 D0

LOC1 LOC0 Reserved Reserved C3M C2M C1M MMUTE

00000000

Table 50. Line output configuration

LOC[1:0] Line output configuration

00 Line output fixed - no volume, no EQ

01 Line output variable - CH3 volume effects line output, no EQ

10 Line output variable with EQ - CH3 volume effects line output

Line output is only active when OCFG = 00. In this case LOC determines the line output configuration. The source of the line output is always the channel 1 and 2 inputs.

7.7.2 Master volume register

D7 D6 D5 D4 D3 D2 D1 D0

MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

11111111

7.7.3 Channel 1 volume

D7 D6 D5 D4 D3 D2 D1 D0

C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

01100000

Doc ID 018572 Rev 3 51/86

7.7.4 Channel 2 volume

D7 D6 D5 D4 D3 D2 D1 D0

C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

01100000

7.7.5 Channel 3 / line output volume

D7 D6 D5 D4 D3 D2 D1 D0

C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

01100000

The volume structure of the STA350BW consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB.

As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB.

The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz).

A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted.

All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E

(addr 0x04)) on a per channel basis as this creates the smoothest possible volume

transitions. When ZCE = 0, volume updates occur immediately.

Table 51. Master volume offset as a function of MV[7:0]

MV[7:0] Volume offset from channel value

00000000 (0x00) 0 dB

00000001 (0x01) -0.5 dB

00000010 (0x02) -1 dB

……

01001100 (0x4C) -38 dB

……

11111110 (0xFE) -127.5 dB

11111111 (0xFF) Hard master mute

52/86 Doc ID 018572 Rev 3

STA350BW Register description

Table 52. Channel volume as a function of CxV[7:0]

CxV[7:0] Volume

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

……

01011111 (0x5F) +0.5 dB

01100000 (0x60) 0 dB

01100001 (0x61) -0.5 dB

……

11010111 (0xD7) -59.5 dB

11011000 (0xD8) -60 dB

11011001 (0xD9) -61 dB

11011010 (0xDA) -62 dB

……

11101100 (0xEC) -80 dB

11101101 (0xED) Hard channel mute

……

11111111 (0xFF) Hard channel mute

7.8 Audio preset registers (addr 0x0B and 0x0C)

7.8.1 Audio preset register 1 (addr 0x0B)

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved AMGC[1] AMGC[0] Reserved Reserved Reserved Reserved

00000000

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 71.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2]. When this value is 00, then bits AMGC[1:0] are defined below in Tabl e 5 3.

Table 53. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0] Mode

00 User-programmable GC

01 AC no clipping 2.1

10 AC limited clipping (10%) 2.1

11 DRC nighttime listening mode 2.1

Doc ID 018572 Rev 3 53/86

7.8.2 Audio preset register 2 (addr 0x0C)

D7 D6 D5 D4 D3 D2 D1 D0

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

00000000

7.8.3 AM interference frequency switching

Table 54. AM interference frequency switching bits

Bit R/W RST Name Description

Audio preset AM enable

0 R/W 0 AMAME

Table 55. Audio preset AM switching frequency selection

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

7.8.4 Bass management crossover

Table 56. Bass management crossover

Bit R/W RST Name Description

4R/W 0 XO0

5R/W 0 XO1

6R/W 0 XO2

7R/W 0 XO3

Table 57. Bass management crossover frequency

XO[3:0] Crossover frequency

0000 User-defined

0001 80 Hz

0010 100 Hz

Selects the bass-management crossover frequency. A 1st-order hign-pass filter (channels 1 and 2) or a 2nd-order low-pass filter (channel 3) at the selected frequency is performed.

0011 120 Hz

54/86 Doc ID 018572 Rev 3

STA350BW Register description

Table 57. Bass management crossover frequency (continued)

XO[3:0] Crossover frequency

0100 140 Hz

0101 160 Hz

0110 180 Hz

0111 200 Hz

1000 220 Hz

1001 240 Hz

1010 260 Hz

1011 280 Hz

1100 300 Hz

1101 320 Hz

1110 340 Hz

1111 360 Hz

7.9 Channel configuration registers (addr 0x0E - 0x10)

D7 D6 D5 D4 D3 D2 D1 D0

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB C1EQBP C1TCB

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VPB C2EQBP C2TCB

01000000

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved Reserved

10000000

7.9.1 Tone control bypass

Tone control (bass/treble) can be bypassed on a per-channel basis for channels 1 and 2.

Table 58. Tone control bypass

CxTCB Mode

0 Perform tone control on channel x - normal operation

1 Bypass tone control on channel x

7.9.2 EQ bypass

EQ control can be bypassed on a per-channel basis for channels 1 and 2. If EQ control is bypassed on a given channel, the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel.

Doc ID 018572 Rev 3 55/86

Table 59. EQ bypass

CxEQBP Mode

0 Perform EQ on channel x - normal operation

1 Bypass EQ on channel x

7.9.3 Volume bypass

Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.

7.9.4 Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel is considered the positive output and output B is the negative inverse.

Table 60. Binary output enable registers

CxBO Mode

0 FFX 3-state output - normal operation

1 Binary output

7.9.5 Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select bits.

Table 61. Channel limiter mapping as a function of CxLS bits

CxLS[1:0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

7.9.6 Output mapping

Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs.

Table 62. Channel output mapping as a function of CxOM bits

CxOM[1:0] Channel x output source from

00 Channel1

01 Channel 2

10 Channel 3

56/86 Doc ID 018572 Rev 3

STA350BW Register description

7.10 Tone control register (addr 0x11)

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

7.10.1 Tone control

Table 63. Tone control boost/cut as a function of BTC and TTC bits

BTC[3:0]/TTC[3:0] Boost/Cut

0000 -12 dB

0001 -12 dB

……

0111 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1101 +12 dB

1110 +12 dB

1111 +12 dB

7.11 Dynamic control registers (addr 0x12 - 0x15)

7.11.1 Limiter 1 attack/release rate

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

7.11.2 Limiter 1 attack/release threshold

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

7.11.3 Limiter 2 attack/release rate

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

Doc ID 018572 Rev 3 57/86

7.11.4 Limiter 2 attack/release threshold

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

The STA350BW includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration register E (addr 0x04) on page 42. Each channel can be mapped to either limiter or not mapped, meaning that the channel will clip when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is mapped to it, selects the maximum absolute value of all these channels, performs the limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels in unison.

The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set to 0 else the thresholds are determined by EATHx[6:0] . It is recommended in anti-clipping mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of an FFX amplifier. Since gain can be added digitally within the STA350BW, it is possible to exceed 0 dBfs or any other LxAT setting. When this occurs, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain reduction occurs on a peak-detect algorithm. Setting the EATHx[7] bits to 1 selects the anti-clipping mode.

The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set to 0, else the thresholds are determined by ERTHx[6:0]. Setting the ERTHx[7] bits to 1 automatically selects the anti-clipping mode. The release of the limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume/limiter block is passed through an RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past its set value and, therefore, the release only occurs if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as overlimiting can reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode, the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold.

58/86 Doc ID 018572 Rev 3

STA350BW Register description

Figure 28. Basic limiter and volume flow diagram

LIMITER

GAIN / VOLUME

INPUT OUTPUT

GAIN

Table 64. Limiter attack rate as a function

ATTENUATION

Table 65. Limiter release rate as a

of LxA bits

LxA[3:0] Attack rate dB/ms LxR[3:0] Release rate dB/ms

RMS

SATURATION

function of LxR bits

AM045193v1

0000 3.1584

0001 2.7072 0001 0.1370

Fast

0000 0.5116

0010 2.2560 0010 0.0744

0011 1.8048 0011 0.0499

0100 1.3536 0100 0.0360

0101 0.9024 0101 0.0299

0110 0.4512 0110 0.0264

0111 0.2256 0111 0.0208

1000 0.1504 1000 0.0198

1001 0.1123 1001 0.0172

1010 0.0902 1010 0.0147

1011 0.0752 1011 0.0137

1100 0.0645 1100 0.0134

1101 0.0564 1101 0.0117

1110 0.0501 1110 0.0110

Slow

1111 0.0451 1111 0.0104

Fast

Slow

Doc ID 018572 Rev 3 59/86

Anti-clipping mode

Table 66. Limiter attack threshold as a

function of LxAT bits (AC-mode)

LxAT[3:0] AC (dB relative to fs) LxRT[3:0] AC (dB relative to fs)

0000 -12 0000 -∞

0001 -10 0001 -29 dB

0010 -8 0010 -20 dB

0011 -6 0011 -16 dB

0100 -4 0100 -14 dB

0101 -2 0101 -12 dB

0110 0 0110 -10 dB

0111 +2 0111 -8 dB

1000 +3 1000 -7 dB

1001 +4 1001 -6 dB

1010 +5 1010 -5 dB

Table 67. Limiter release threshold as a

function of LxRT bits (ACmode)

1011 +6 1011 -4 dB

1100 +7 1100 -3 dB

1101 +8 1101 -2 dB

1110 +9 1110 -1 dB

1111 +10 1111 -0 dB

60/86 Doc ID 018572 Rev 3

STA350BW Register description

Dynamic range compression mode

Table 68. Limiter attack threshold as a

function of LxAT bits (DRC mode)

Table 69. Limiter release threshold as a

as a function of LxRT bits (DRC-mode)

LxAT[3:0] DRC (dB relative to Volume) LxRT[3:0]

DRC (db relative to Volume +

0000 -31 0000 -∞

0001 -29 0001 -38 dB

0010 -27 0010 -36 dB

0011 -25 0011 -33 dB

0100 -23 0100 -31 dB

0101 -21 0101 -30 dB

0110 -19

0110 -28 dB

0111 -17 0111 -26 dB

1000 -16 1000 -24 dB

1001 -15 1001 -22 dB

1010 -14 1010 -20 dB

1011 -13 1011 -18 dB

1100 -12 1100 -15 dB

1101 -10 1101 -12 dB

1110 -7 1110 -9 dB

1111 -4 1111 -6 dB

LxAT)

7.11.5 Limiter 1 extended attack threshold (addr 0x32)

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN1 EATH1[6] EATH1[5] EATH1[4] EATH1[3] EATH1[2] EATH1[1] EATH1[0]

TBDTBDTBDTBDTBDTBDTBDTBD

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH1 / 4

7.11.6 Limiter 1 extended release threshold (addr 0x33)

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

TBDTBDTBDTBDTBDTBDTBDTBD

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH1 / 4

Doc ID 018572 Rev 3 61/86

7.11.7 Limiter 2 extended attack threshold (addr 0x34)

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN2 EATH2[6] EATH2[5] EATH2[4] EATH2[3] EATH2[2] EATH2[1] EATH2[0]

TBDTBDTBDTBDTBDTBDTBDTBD

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH2 / 4

7.11.8 Limiter 2 extended release threshold (addr 0x35)

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

TBDTBDTBDTBDTBDTBDTBDTBD

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH2 / 4

Note: Attack/release threshold step is 0.125 dB in the range -12 dB to 0 dB.

7.12 User-defined coefficient control registers (addr 0x16 - 0x26)

7.12.1 Coefficient address register

D7 D6 D5 D4 D3 D2 D1 D0

CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

000000

7.12.2 Coefficient b1 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

7.12.3 Coefficient b1 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

7.12.4 Coefficient b1 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

62/86 Doc ID 018572 Rev 3

STA350BW Register description

7.12.5 Coefficient b2 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

7.12.6 Coefficient b2 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

7.12.7 Coefficient b2 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

7.12.8 Coefficient a1 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

7.12.9 Coefficient a1 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

7.12.10 Coefficient a1 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

00000000

7.12.11 Coefficient a2 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

Doc ID 018572 Rev 3 63/86

7.12.12 Coefficient a2 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

00000000

7.12.13 Coefficient a2 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

00000000

7.12.14 Coefficient b0 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

7.12.15 Coefficient b0 data register bits 15:8

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

7.12.16 Coefficient b0 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

7.12.17 Coefficient write/read control register

D7 D6 D5 D4 D3 D2 D1 D0

Reserved RA R1 WA W1

0 0000

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled internally in the STA350BW via RAM. Access to this RAM is available to the user via an I register interface. A collection of I coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM.

C registers are dedicated to this function. One contains a

Three different RAM banks are embedded in the STA350BW. The three banks are managed in paging mode using EQCFG register bits. They can be used to store different EQ settings. For speaker frequency compensation, a sampling frequency independent EQ must be implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and downloading them into the three RAM banks, it is possible to select the suitable RAM block depending on the incoming frequency with a simple I

64/86 Doc ID 018572 Rev 3

C write operation in register 0x31.

STA350BW Register description

For example, in case of different input sources (different sampling rates), the three different sets of coefficients can be downloaded once at startup, and during normal play it is possible to switch among the three RAM blocks allowing faster operation, without any additional download from the microcontroller.

To write the coefficients in a particular RAM bank, this bank must be selected first, writing bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.

Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to the coefficients stored in the active RAM block.

Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.

Reading a coefficient from RAM

1. Select the RAM block with register 0x31 bit 1, bit 0.

2. Write 6 bits of address to I

3. Write 1 to R1 bit in I

4. Read top 8 bits of coefficient in I

5. Read middle 8 bits of coefficient in I

6. Read bottom 8 bits of coefficient in I

C register 0x16.

C address 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

Reading a set of coefficients from RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I

3. Write 1 to RA bit in I

4. Read top 8 bits of coefficient in I

5. Read middle 8 bits of coefficient in I

6. Read bottom 8 bits of coefficient in I

7. Read top 8 bits of coefficient b2 in I

8. Read middle 8 bits of coefficient b2 in I

9. Read bottom 8 bits of coefficient b2 in I

10. Read top 8 bits of coefficient a1 in I

11. Read middle 8 bits of coefficient a1 in I

12. Read bottom 8 bits of coefficient a1 in I

13. Read top 8 bits of coefficient a2 in I

14. Read middle 8 bits of coefficient a2 in I

15. Read bottom 8 bits of coefficient a2 in I

16. Read top 8 bits of coefficient b0 in I

17. Read middle 8 bits of coefficient b0 in I

18. Read bottom 8 bits of coefficient b0 in I

C register 0x16.

C address 0x26.

C address 0x17.

C address 0x18.

C address 0x19.

C address 0x1A.

C address 0x1B.

C address 0x1C.

C address 0x1D.

C address 0x1E.

C address 0x1F.

C address 0x20.

C address 0x21.

C address 0x22.

C address 0x23.

C address 0x24.

C address 0x25.

Doc ID 018572 Rev 3 65/86

Writing a single coefficient to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I

3. Write top 8 bits of coefficient in I

4. Write middle 8 bits of coefficient in I

5. Write bottom 8 bits of coefficient in I

6. Write 1 to the W1 bit in I

C register 0x16.

C address 0x17.

C address 0x18.

C address 0x19.

C address 0x26.

Writing a set of coefficients to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of starting address to I

3. Write top 8 bits of coefficient b1 in I

4. Write middle 8 bits of coefficient b1 in I

5. Write bottom 8 bits of coefficient b1 in I

6. Write top 8 bits of coefficient b2 in I

7. Write middle 8 bits of coefficient b2 in I

8. Write bottom 8 bits of coefficient b2 in I

9. Write top 8 bits of coefficient a1 in I

10. Write middle 8 bits of coefficient a1 in I

11. Write bottom 8 bits of coefficient a1 in I

12. Write top 8 bits of coefficient a2 in I

13. Write middle 8 bits of coefficient a2 in I

14. Write bottom 8 bits of coefficient a2 in I

15. Write top 8 bits of coefficient b0 in I

16. Write middle 8 bits of coefficient b0 in I

17. Write bottom 8 bits of coefficient b0 in I

18. Write 1 to the WA bit in I

C address 0x26.

C register 0x16.

C address 0x17.

C address 0x18.

C address 0x19.

C address 0x1A.

C address 0x1B.

C address 0x1C.

C address 0x1D.

C address 0x1E.

C address 0x1F.

C address 0x20.

C address 0x21.

C address 0x22.

C address 0x23.

C address 0x24.

C address 0x25.

The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the STA350BW generates the RAM addresses as offsets from this base value to write the complete set of coefficient data.

66/86 Doc ID 018572 Rev 3

STA350BW Register description

7.12.18 User-defined EQ

The STA350BW can be programmed for four EQ filters (biquads) per each of the two input channels. The biquads use the following equation:

Y[n] = 2 * (b

= b

/ 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]

* X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]

where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808).

Coefficients stored in the user-defined coefficient RAM are referenced in the following manner:

CxHy0 = b

CxHy1 = b

/ 2

CxHy2 = -a1 / 2

CxHy3 = -a

CxHy4 = b0 / 2

where x represents the channel and the y the biquad number. For example, C2H41 is the b coefficient in the fourth biquad for channel 2.

Additionally, the STA350BW can be programmed for a high-pass filter (processing channels 1 and 2) and a low-pass filter (processing channel 3) to be used for bassmanagement crossover when the XO setting is 000 (user-defined). Both of these filters when defined by the user (rather than using the preset crossover filters) are second order filters that use the biquad equation given above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in Tab le 7 0 .

By default, all user-defined filters are pass-through where all coefficients are set to 0, except the b

/2 coefficient which is set to 0x400000 (representing 0.5).

7.12.19 Pre-scale

The STA350BW provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I coefficients and the bass-management. All channels can use the channel-1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 0x7FFFFF.

7.12.20 Post-scale

The STA350BW provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor for this multiplication is loaded into RAM using the same I biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped microcontroller to perform power-supply error correction. All channels can use the channel-1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 0x7FFFFF. When line output is being used, channel-3 post-scale will affect both channels 3 and 4.

C registers as the biquad

C registers as the

Doc ID 018572 Rev 3 67/86

7.12.21 Overcurrent post-scale

The STA350BW provides a simple mechanism for reacting to overcurrent detection in the power block. When the ocwarn input is asserted, the overcurrent post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3 dB of output attenuation when ocwarn is asserted.

The amount of attenuation to be applied in this situation can be adjusted by modifying the Overcurrent Post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, the overcurrent post-scale factor is set to applied, it remains until the device is reset.

Table 70. RAM block for biquads, mixing, scaling and bass management

Index (decimal) Index (hex) Coefficient Default

0x5A9DF7. Once the overcurrent attenuation is

0 0x00

1 0x01 C1H11(b2) 0x000000

2 0x02 C1H12(a1/2) 0x000000

3 0x03 C1H13(a2) 0x000000

4 0x04 C1H14(b0/2) 0x400000

5 0x05 Channel 1 - Biquad 2 C1H20 0x000000

…… … … …

19 0x13 Channel 1 - Biquad 4 C1H44 0x400000

20 0x14

21 0x15 C2H11 0x000000

…… … … …

39 0x27 Channel 2 - Biquad 4 C2H44 0x400000

40 0x28

41 0x29 C12H1(b2) 0x000000

42 0x2A C12H2(a1/2) 0x000000

43 0x2B C12H3(a2) 0x000000

44 0x2C C12H4(b0/2) 0x400000

45 0x2D

46 0x2E C3H1(b2) 0x000000

47 0x2F C3H2(a1/2) 0x000000

48 0x30 C3H3(a2) 0x000000

49 0x31 C3H4(b0/2) 0x400000

50 0x32 Channel 1 - Pre-Scale C1PreS 0x7FFFFF

51 0x33 Channel 2 - Pre-Scale C2PreS 0x7FFFFF

Channel 1 - Biquad 1

Channel 2 - Biquad 1

Channel 1/2 - Biquad 5

for XO = 000

Hi-pass 2

Channel 3 - Biquad

Low-pass 2

Order filter

for XO≠000

for XO = 000

Order filter

for XO≠000

C1H10(b1/2) 0x000000

C2H10 0x000000

C12H0(b1/2) 0x000000

C3H0(b1/2) 0x000000

52 0x34 Channel 1 - Post-Scale C1PstS 0x7FFFFF

53 0x35 Channel 2 - Post-Scale C2PstS 0x7FFFFF

68/86 Doc ID 018572 Rev 3

STA350BW Register description

Table 70. RAM block for biquads, mixing, scaling and bass management (continued)

Index (decimal) Index (hex) Coefficient Default

54 0x36 Channel 3 - Post-Scale C3PstS 0x7FFFFF

55 0x37 TWARN/OC - Limit TWOCL 0x5A9DF7

56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF

57 0x39 Channel 1 - Mix 2 C1MX2 0x000000

58 0x3A Channel 2 - Mix 1 C2MX1 0x000000

59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF

60 0x3C Channel 3 - Mix 1 C3MX1 0x400000

61 0x3D Channel 3 - Mix 2 C3MX2 0x400000

62 0x3E UNUSED

63 0x3F UNUSED

7.13 Variable max power correction registers (addr 0x27 - 0x28)

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

D7 D6 D5 D4 D3 D2 D1 D0

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

00011010

11000000

The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1.

7.14 Variable distortion compensation registers (addr 0x29 0x2A)

D7 D6 D5 D4 D3 D2 D1 D0

DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

D7 D6 D5 D4 D3 D2 D1 D0

DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

1111001 1

00110011

The DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1.

Doc ID 018572 Rev 3 69/86

7.15 Fault detect recovery constant registers (addr 0x2B - 0x2C)

D7 D6 D5 D4 D3 D2 D1 D0

FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

00001100

The FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the TRISTATE output is immediately asserted low and held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms.

7.16 Device status register (addr 0x2D)

D7 D6 D5 D4 D3 D2 D1 D0

PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN

This read-only register provides fault and thermal-warning status information from the power control block. Logic value 1 for faults or warning means normal state. Logic 0 means a fault or warning detected on power bridge. The PLLUL = 1 means that the PLL is not locked.

Table 71. Status register bits

Bit R/W RST Name Description

7 R - PLLUL

6R - FAULT

5R - UVFAULT

4R - OVFAULT

PLL locked

1: PLL not locked

0: fault detected on power bridge 1: normal operation

0: VCCxX internally detected < undervoltage threshold

0: VCCxX internally detected > overvoltage threshold

3 R - OCFAULT 0: overcurrent fault detected

2 R - OCWARN 0: overcurrent warning

1R - TFAULT

0R - TWARN

0: thermal fault, junction temperature over limit detection

0: thermal warning, junction temperature is close to the fault condition

70/86 Doc ID 018572 Rev 3

STA350BW Register description

7.17 EQ coefficients and DRC configuration register (addr 0x31)

D7 D6 D5 D4 D3 D2 D1 D0

XOB Reserved Reserved AMGC[3] AMGC[2] Reserved SEL[1] SEL[0]

00000000

Table 72. EQ RAM select

SEL[1:0] EQ RAM bank selected

00/11 Bank 0 activated

01 Bank 1 activated

10 Bank 2 activated

Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Ta b le 7 3 below.

Table 73. Anti-clipping and DRC preset

AMGC[3:2] Anti clipping and DRC preset selected

00 DRC/Anti-clipping behavior described in Ta bl e 5 3 on page 53 (default).

01 DRC/Anti-clipping behavior is described Table 74 on page 71

10/11 Reserved, do not use

When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Tabl e 74 .

Table 74. Anti-clipping selection for AMGC[3:2] = 01

AMGC[1:0] Mode

00 AC0, stereo anticlipping 0 dB limiter

01 AC1, stereo anticlipping +1.25 dB limiter

10 AC2, stereo anticlipping +2 dB limiter

11 Reserved do not use

The AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the minimum any audio artifacts introduced by typical anti-clipping/DRC algorithms. More detailed information is available in the applications notes “Configurable output power rate using STA335BW” and “STA335BWS vs STA335BW”.

The XOB bit can be used to bypass the crossover filters. Logic 1 means that the function is not active. In this case, the high-pass crossover filter works as a pass-through on the data path (b0 = 1, all the other coefficients at logic 0) while the low-pass filter is configured to have zero signal on channel-3 data processing (all the coefficients are at logic 0).

Doc ID 018572 Rev 3 71/86

7.18 Extended configuration register (addr 0x36)

D7 D6 D5 D4 D3 D2 D1 D0

Mdrc[1] Mdrc[0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

00000000

The extended configuration register provides access to B2DRC and biquad 5, 6 and 7.

7.18.1 Dual-band DRC

The STA350BW device provide a dual-band DRC (B2DRC) on the left and right channels data path, as depicted in Figure 29. Dual-band DRC is activated by setting MDRC[1:0] = 1x.

DRC scheme

Pass XO

B2DRC

Filter

Hi-pass

filter

Pass XO

Pass XO B2DRC

B2DRC

Filter

Hi-pass

filter

CH1

Volume

CH3

Volume

CH2

Volume

CH3

Volume

VolAndLimiter

DRC1

VolAndLimiter

DRC2

DRC1

VolAndLimiter

DRC2

AM045194v1

Figure 29. B

The low frequency information (LFE) is extracted from left and right channels, removing the high frequencies using a programmable Biquad filter, and then computing the difference with the original signal. Limiter 1 (DRC1) is then used to control Left/Right high-frequency amplitude of the components, while limiter 2 (DRC2) is used to control the low-frequency components (see Chapter 7.11).

The cutoff frequency of the high-pass filters can be user-defined, XO[3:0] = 0, or selected from the pre-defined values.

DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE channels amplitude (see Chapter 7.11) as well as their volume control. To be noted that, in this configuration, the dedicated channel 3 volume control can actually act as a bass boost enhancer as well (0.5 dB/step resolution).

The processed LFE channel is then recombined with the L and R channels in order to reconstruct the 2.0 output signal.

Sub-band decomposition

The sub-band decomposition for B2DRC can be configured specifying the cutoff frequency. The cutoff frequency can be programmed in two ways, using XO bits in register 0x0C, or using the “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).

72/86 Doc ID 018572 Rev 3

STA350BW Register description

For the user programmable mode, use the formulas below to compute the high-pass filters:

b0 = (1 + alpha) / 2 a0 = 1

b1 = -(1 + alpha) / 2 a1 = -alpha

b2 = 0 a2 = 0

where alpha = (1-sin(ω0))/cos(ω0), and ω0 is the cutoff frequency.

A first-order filter is suggested to guarantee that for every ω filter obtained as the difference (as shown in Figure 29) will have a symmetric (relative to HP filter) frequency response, and the corresponding recombination after the DRC has low ripple. Second-order filters can be used as well, but in this case the filter shape must be carefully chosen to provide good low-pass response and minimum ripple recombination. For second-order filters it is not possible to give a closed formula to get the best coefficients, but empirical adjustment should be done.

DRC settings

The DRC blocks used by B2DRC are the same as those described in Chapter 7.11. B2DRC configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are configured by registers 0x12 and 0x14.

Band downmixing

The low-frequency band is down-mixed to the left and right channels at the B2DRC output. Channel volume can be used to weight the bands recombination to fine-tune the overall frequency response.

7.18.2 EQ DRC mode

Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path (side chain). Using EQDRC the peak detector input can be shaped in frequency using the programmable biquad. For example if a +2 dB bass boost is applied (using a low shelf filter for example), the effect is that the EQDRC output will limit bass frequencies to -2 dB below the selected attack threshold.

the corresponding low-pass

Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a compressed sine wave at the output will be TH - X, where TH is the selected attack threshold.

Note: EQDRC works only if the biquad frequency response magnitude is ≥ 0dB for every

frequency.

Doc ID 018572 Rev 3 73/86

Figure 30. EQDRC scheme

EQDRC

ATTENUATION

Channel In

BIQUAD

BIQUADBIQUAD

BIQUAD

BIQUADBIQUAD

PEAK

DETECTOR

Standard DRC

PEAK

DETECTOR

ATTENUATION

CLACULATOR

ATTENUATION

CLACULATOR

ATTENUATION

AM045195v1

7.18.3 Extended post-scale range

PS48DB Mode

0 Post-scale value is applied as defined in coefficient RAM

Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied to the coefficient RAM value, so post-scale can act as a gain too.

7.18.4 Extended attack rate

The attack rate shown in Ta bl e 6 4 can be extended to provide up to an 8 dB/ms attack rate on both limiters.

XAR1 Mode

0 Limiter1 attack rate is configured using Ta b le 6 4

1 Limiter1 attack rate is 8 dB/ms

XAR2 Mode

0 Limiter2 attack rate is configured using Ta b le 6 4

1 Limiter2 attack rate is 8 dB/ms

Post-scale value is applied with +48 dB offset with respect to the coefficient RAM value

74/86 Doc ID 018572 Rev 3

STA350BW Register description

7.18.5 Extended BIQUAD selector

De-emphasis filter as well as bass and treble controls can be configured as user-defined filters when the equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is set to 1.

BQ5 Mode

0 Pre-set de-emphasis filter selected

1 User-defined biquad 5 coefficients are selected

BQ6 Mode

0 Pre-set bass filter selected as per Ta bl e 6 3

1 User-defined biquad 6 coefficients are selected

BQ7 Mode

0 Pre-set treble filter selected as per Ta bl e 6 3

1 User-defined biquad 7 coefficients are selected

When filters from 5th to 7th are configured as user-programmable, the corresponding coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A0x2E (BQ7) as in Ta bl e 7 0.

Note: BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for

BQ6 and BQ7).

7.19 EQ soft-volume configuration registers (addr 0x37 - 0x38)

D7 D6 D5 D4 D3 D2 D1 D0

SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

SVDWE SVDW4] SVDW[3] SVDW[2] SVDW[1] SVDW[0]

00000000

The soft-volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to override the default behavior allowing different volume change rates.

It is also possible to independently define the fade-in (volume is increased) and fade-out (volume is decreased) rates according to the desired behavior.

SVUPE Mode

0 When volume is increased, use the default rate

1 When volume is increased, use the rates defined by SVUP[4:0]

Doc ID 018572 Rev 3 75/86

When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the following formula:

Fade-in rate = 48 / (N + 1) dB/ms

where N is the SVUP[4:0] value.

SVDWE Mode

0 When volume is decreased, use the default rate

1 When volume is decreased, use the rates defined by SVDW[4:0]

When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the following formula:

Fade-in rate = 48 / (N + 1) dB/ms

where N is the SVDW[4:0] value.

Note: For fade-out rates greater than 6 dB/msec it is suggested to disable the CPWMEN bit

(Section 7.24.4 ) and ZCE bit (Section 7.5.7) in order to avoid any audible pop noise.

7.20 DRC RMS filter coefficients (addr 0x39-0x3E)

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[23] R_C0[22] R_C0[21] R_C0[20] R_C0[19] R_C0[18] R_C0[17] R_C0[16]

00000001

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[15] R_C0[14] R_C0[13] R_C0[12] R_C0[11] R_C0[10] R_C0[9] R_C0[8]

11101110

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[7] R_C0[6] R_C0[5] R_C0[4] R_C0[3] R_C0[2] R_C0[1] R_C0[0]

11111111

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[23] R_C1[22] R_C1[21] R_C1[20] R_C1[19] R_C1[18] R_C1[17] R_C1[16]

01111110

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[15] R_C1[14] R_C1[13] R_C1[12] R_C1[11] R_C1[10] R_C1[9] R_C1[8]

11000000

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[7] R_C1[6] R_C1[5] R_C1[4] R_C1[3] R_C1[2] R_C1[1] R_C1[0]

00100110

Signal level detection in DRC algorithm is computed using the following formula:

y(t) = c0 * abs(x(t)) + c1 * y(t-1)

where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.

76/86 Doc ID 018572 Rev 3

STA350BW Register description

7.21 Extra volume resolution configuration registers (address 0x3F)

D7 D6 D5 D4 D3 D2 D1 D0

VRESEN VRESTG C3VR[1] C3VR[0] C2VR[1] C2VR[0] C1VR[1] C1VR[0]

00000000

The extra volume resolution allows fine volume tuning by steps of 0.125dB.

The feature is enabled when VRESEN=1 , as depicted in Figure 31. The overall channel volume in this case will be CxVol+CxVR (in dB). On top of the total volume range from

-80 dB to +48 dB, this extra volume resolution works in a volume range from -80 dB to +42 dB. For volumes greater than +42 dB, this function must not be selected.

Figure 31. Extra resolution volume scheme

Audio Data In

CxVOL

Soft

Volume

Audio Data Out

VRESTG

VRESEN

MVOL or CxVOL’event

CxVR

If VRESEN = 0 the channel volume will be defined only by the CxVol registers.

Fine-tuning steps can be set according to the following table for channels 1, 2, 3:

CxVR Mode

00 0 dB

01 -0.125dB

10 -0.25dB

11 -0.375dB

AM045196v1

Doc ID 018572 Rev 3 77/86

Two different behaviors can be configured by the VRESTG bit:

● If VRESTG=’0’ the CxVR contribution will be applied immediately after the

corresponding I

● If VRESTG=’1’ the CxVR bits will be effective on channel volume only after the

C bits are written.

corresponding CxVol register or master volume register is written (even to the previous values).

VRESEN VRESTG Mode

0 0 Extra Volume Resolution disabled

0 1 Extra Volume Resolution disabled

1 0 Volume fine-tuning enabled and applied immediately.

Volume fine-tuning enabled and applied when master or channel volume is updated

7.22 Quantization error noise correction (address 0x48)

D7 D6 D5 D4 D3 D2 D1 D0

NSHXEN NSHB7EN NSHB6EN NSHB5EN NSHB4EN NSHB3EN NSHB2EN NSHB1EN

00000000

A special feature inside the digital processing block is available. In case of poles positioned at very low frequencies, biquad filters can generate some audible quantization noise or unwanted DC level. In order to avoid this kind of effect, a quantization noise-shaping capability can be used. The filter structure including this special feature, relative to each biquad, is shown in Figure 32.

By default, this capability is not activated to maintain backward compatibility with all the previous Sound Terminal products. The new feature can be enabled independently for each biquad using the I

C registers. The D7 bit, when set, is responsible for activating this function on the crossover filter while the other bits address any specific biquads according to the previous table. Channels 1 and 2 share the same settings. Bit D7 is effective also for channel 3 if the relative OCFG is used.

78/86 Doc ID 018572 Rev 3

STA350BW Register description

Figure 32. Biquad filter structure with quantization error noise-shaping

-1

In(t)

-1

Out(t)

-1

AM045197v1

7.23 Extended coefficient range up to -4...4 (address 0x49, 0x4A)

D7 D6 D5 D4 D3 D2 D1 D0

CXTB4[1] CXTB4[0] CXTB3[1] CXTB3[0] CX_B2[1] CXTB2[0] CXTB1[1] CXTB1[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved CXTB7[1] CXTB7[0] CXTB6[1] CXTB6[0] CXTB5[1] CXTB5[0]

0 0 00000 0

Biquads from 1 to 7 have in the STA350BW the possibility to extend the coefficient range from [-1,1) to [-4..4). This allows the realization of high shelf filters that may require a coefficients dynamic greater in absolute value than 1.

Three ranges are available, [-1;1) [-2;2) [-4;4). By default the extended range is not activated to maintain backward compatibility with all the previous Sound Terminal products.

Each biquad has its independent setting according to the following table:

Table 75. Biquad filter settings

CEXT_Bx[1] CEXT_Bx[0]

1 1 Reserved

Doc ID 018572 Rev 3 79/86

[-1;1)

[-2;2)

[-4;4)

In this case the user can decide, for each filter stage, the right coefficients range. Note that for a given biquad the same range will be applied to Left and Right (Channel 1 and Channel

2).

The crossover biquad does not have the availability of this feature, maintaining the [-1;1) range unchanged.

7.24 Miscellaneous registers (address 0x4B, 0x4C)

D7 D6 D5 D4 D3 D2 D1 D0

RPDNEN NSHHPEN BRIDGOFF Reserved Reserved CPWMEN Reserved Reserved

0 0 00010 0

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved Reserved PNDLSL[2] PNDLSL[1] PNDLSL[0] Reserved Reserved

00000000

7.24.1 Rate powerdown enable (RPDNEN) bit (address 0x4B, bit D7)

In the STA350BW, by default, the power-down pin and I2C power-down act on mute commands to perform the fadeout. This default can be changed so that the fadeout can be started using the master volume. The RPDNEN bit, when set, activates this feature.

7.24.2 Noise-shaping on DC cut filter enable (NSHHPEN) bit (address 0x4B, bit D6)

Following the description in Section 7.22, this bit, when set, enables the noise-shaping technique on the DC cutoff filter. Channels 1 and 2 share the same settings.

7.24.3 Bridge immediate off (BRIDGOFF) bit (address 0x4B, bit D5)

A fadeout procedure is started in the STA350BW once the PWDN function is enabled. Independently from the fadeout time, after 13 million clock cycles (PLL internal frequency) the bridge is put in powerdown (tristate mode). There is also the possibility to change this behavior so that the power bridge will be switched off immediately after the PWDN pin is tied to ground, without therefore waiting for the 13 million clock cycles. The BRIDGOFF bit, when set, activates this function. Obviously the immediate power-down will generate a pop noise at the output. therefore this procedure must be used only in case pop noise is not relevant in the application. Note that this feature works only for hardware PWDN assertion and not for a powerdown applied through the I different number of clock cycles.

C interface. Refer to Section 7.24.5 in order to program a

80/86 Doc ID 018572 Rev 3

STA350BW Register description

7.24.4 Channel PWM enable (CPWMEN) bit (address 0x4B, bit D2)

This bit, when set, activates a mute output in case the volume will reach a value lower than

-76 dBFS.

7.24.5 Power-down delay selector (PNDLSL[2:0]) bits (address 0x4C, bit D4, D3, D2)

As per Section 7.24.3, the assertion of PWDN activates a counter that, by default, after 13 million clock cycles puts the power bridge in tristate mode, independently from the fadeout time. Using these registers it is possible to program this counter according to the following table:

PNDLSL[2] PNDLSL[1] PNDLSL[2] Fade out time

11 1

0 Default time (13M clock cycles)

1 Default time divided by 2

0 Default time divided by 4

1 Default time divided by 8

0 Default time divided by 16

1 Default time divided by 32

0 Default time divided by 64

Default time divided by 128

Doc ID 018572 Rev 3 81/86

Package thermal characteristics STA350BW

8 Package thermal characteristics

Using a four-layer PCB the thermal resistance junction-to-ambient with 2 copper ground areas of 6 x 4 cm

and with 24 via holes (see Figure 33) is 17 °C/W in natural air convection.

The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.

Thus, the maximum estimated dissipated power for the STA350BW is:

2 x 40 W @ 8 Ω, 25.5 V Pd max ~ 8 W

2 x 17 W + 1 x 35 W @ 4 Ω, 8 Ω, 25 V Pd max < 7 W

Figure 33. Double-layer PCB with 2 copper ground areas and 24 via holes

AM045200v1

Figure 34 shows the power derating curve for the PowerSSO-36 slug-down package on

PCBs with copper areas of 5 x 4 cm

and 6 x 4cm2.

Figure 34. PowerSSO-36 power derating curve

Pd (W)

Copper Area 6x4 cm

Copper Area 5x4 cm

and 20 via holes

020406080 100 120 140 160

and 20 via holes

and 24 via holes

Tamb ( °C)

STA350BW

Power-SSO36

AM045201v1

82/86 Doc ID 018572 Rev 3

STA350BW Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Table 76. PowerSSO-36 EPD dimensions

Dimensions in mm Dimensions in inches

Symbol

Min Typ Max Min Typ Max

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0.00 - 0.10 0.00 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e- 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F- 2.3 - - 0.091 -

G - - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h - - 0.40 - - 0.016

k 0 - 8 degrees 0 - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 6.50 - 7.10 0.256 - 0.280

Doc ID 018572 Rev 3 83/86

Figure 35. PowerSSO-36 EPD outline drawing

Doc ID 018572 Rev 3 84/86

STA350BW Package mechanical data

h x 45°

STA350BW Revision history

10 Revision history

Table 77. Document revision history

Date Revision Changes

11-Mar-2011 1 Initial release.

20-Apr-2011 2

13-Apr-2012 3

Updated Figure 4: Demonstration board, 2.0 channels Added Figure 5: Mono parallel BTL schematic

Updated min. and typ. values for Isc in Table 6: Electrical

specifications - power section

Doc ID 018572 Rev 3 85/86

STA350BW

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

86/86 Doc ID 018572 Rev 3

ST STA350BW User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Description

1.1 Block diagram

Figure 1. Block diagram

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

2.2 Pin description

Table 1. Pin description

3 Electrical specifications

3.1 Absolute maximum ratings

Table 2. Absolute maximum ratings

3.2 Thermal data

Table 3. Thermal data

3.3 Recommended operating conditions

Table 4. Recommended operating conditions

3.4 Electrical specifications for the digital section

Table 5. Electrical specifications - digital section

3.5 Electrical specifications for the power section

Table 6. Electrical specifications - power section

Figure 3. Test circuit

4 Characterization curves

Figure 4. Demonstration board, 2.0 channels

Figure 5. Mono parallel BTL schematic

4.1 Mono parallel BTL characteristics

5 Processing data paths

Figure 16. Left and right processing - part 1

Figure 17. Processing - part 2

6 I2C bus specification

6.1 Communication protocol

6.1.1 Data transition or change

6.1.2 Start condition

6.1.3 Stop condition

6.1.4 Data input

6.2 Device addressing

6.3 Write operation

6.3.1 Byte write

6.3.2 Multi-byte write

6.4 Read operation

6.4.1 Current address byte read

6.4.2 Current address multi-byte read

6.4.3 Random address byte read

6.4.4 Random address multi-byte read

6.4.5 Write mode sequence

Figure 18. Write mode sequence

6.4.6 Read mode sequence

Figure 19. Read mode sequence

7 Register description

Table 7. Register summary

7.1 Configuration register A (addr 0x00)

7.1.1 Master clock select

Table 8. Master clock select

Table 9. Input sampling rates

7.1.2 Interpolation ratio select

Table 10. Internal interpolation ratio

Table 11. IR bit settings as a function of input sample rate

7.1.3 Thermal warning recovery bypass

Table 12. Thermal warning recovery bypass

7.1.4 Thermal warning adjustment bypass

Table 13. Thermal warning adjustment bypass

7.1.5 Fault detect recovery bypass

Table 14. Fault detect recovery bypass

7.2 Configuration register B (addr 0x01)

7.2.1 Serial audio input interface format

Table 15. Serial audio input interface

7.2.2 Serial data interface

7.2.3 Serial data first bit

Table 16. Serial data first bit

Table 17. Support serial audio input formats for MSB-first (SAIFB = 0)

Table 18. Supported serial audio input formats for LSB-first (SAIFB = 1)

7.2.4 Delay serial clock enable

Table 19. Delay serial clock enable

7.2.5 Channel input mapping

Table 20. Channel input mapping

7.3 Configuration register C (addr 0x02)

7.3.1 FFX power output mode

Table 21. FFX power output mode