ST STA339BW User Manual
2.1-channel high-efficiency digital audio system
Features
Wide voltage supply range
– 5 V to 26 V (operating range)
– 30 V (absolute maximum rating)
3 power output configurations
– 2 channels of ternary PWM (stereo mode)
(2 x 20 W into 8 Ω at 18 V)
– 3 channels - left, right using binary and LFE
using ternary PWM (2.1 mode) (2 x 9 W +
1x20W into 2x4Ω, 1 x 8 Ω at 18 V)
– 2 channels of ternary PWM (2 x 20 W) +
stereo lineout ternary
2.1 channels of 24-bit FFX
dynamic range
Selectable 32 to 192 kHz input sample rates
2
I
C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB with
0.5 dB/step resolution
Soft volume update with programmable ratio
Individual channel and master gain/attenuation
Two independent DRC configurable as a
dual-band anti-clipper (B
independent limiters/compressors
EQ-DRC for DRC based on filtered signals
Dedicated LFE processing for bass boosting
with 0.5 dB/step resolution
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel and master soft/hard mute
Table 1. Device summary
®
100 dB SNR and
2
DRC) or as
STA339BW
PowerSSO-36 (slug down)
Independent channel volume and DSP bypass
Automatic zero-detect mute
Automatic invalid input-detect mute
2-channel I
Input and output channel mapping
Up to 8 user-programmable biquads per
channel with 28-bit resolution
3 coefficient banks for EQ presets storing with
fast recall via I
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Variable max power correction for lower
full-power THD
Selectable clock input ratio
96 kHz internal processing sample rate, 24 to
28-bit precision
Thermal overload and short-circuit protection
embedded
Video apps: 576 * f
Fully compatible with STA339BWS.
2
S input data interface
2
C interface
input mode supported
S
Order code Package Packaging
STA339BW PowerSSO-36 slug down Tube
STA339BWTR PowerSSO-36 slug down Tape and reel
August 2010 Doc ID 15251 Rev 5 1/77
www.st.com
77
Contents STA339BW
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15
3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16
3.6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7.1 Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5I
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.1 FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.2 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3.3 Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . 34
6.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 35
6.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.8 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5.3 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.5.4 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.5 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.6 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 37
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6.5.7 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.5.8 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 44
6.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.6.5 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.6.6 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.6.7 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.7 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 45
6.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.8 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 47
6.8.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.8.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.8.3 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.8.4 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.9 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 49
6.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.10 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.11 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 51
6.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.11.5 Limiter 1 Extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 55
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6.11.6 Limiter 1 Extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 55
6.11.7 Limiter 2 Extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 56
6.11.8 Limiter 2 Extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 56
6.12 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 56
6.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.19 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.20 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.12.21 Overcurrent postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.13 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 63
6.14 Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 63
6.15 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 64
6.16 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.17 EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 65
6.18 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 65
6.18.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.18.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.18.3 Extended post scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.18.4 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.18.5 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Contents STA339BW
6.19 EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 69
6.20 DRC RMS filter coefficients (addr 0x39 - 0x3E) . . . . . . . . . . . . . . . . . . . . 70
7 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Left and right processing part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Processing part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 16. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 17. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 20. B
Figure 21. EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. Double-layer PCB with 2 copper ground areas and 16 via holes . . . . . . . . . . . . . . . . . . . 73
Figure 25. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. PowerSSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2
DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Doc ID 15251 Rev 5 7/77
List of tables STA339BW
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 18. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Supported serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . 30
Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 31
Table 21. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 22. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 23. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 24. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 25. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 26. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 28. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 29. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 30. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 31. Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 32. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 33. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 34. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 35. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 36. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 37. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 38. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 39. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 40. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 41. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 42. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 43. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 44. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 45. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 46. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 47. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 48. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8/77 Doc ID 15251 Rev 5
STA339BW List of tables
Table 49. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 50. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 51. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 52. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 53. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 54. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 55. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 47
Table 56. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 57. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 58. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 59. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 60. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 61. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 62. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 63. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 64. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 65. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 66. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 67. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 68. Limiter attack threshold as a function of LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . 54
Table 69. Limiter release threshold as a function of LxRT bits (AC mode). . . . . . . . . . . . . . . . . . . . . 54
Table 70. Limiter attack threshold as a function of LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . 55
Table 71. Limiter release threshold as a as a function of LxRT bits (DRC mode) . . . . . . . . . . . . . . . 55
Table 72. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 62
Table 73. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 74. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 75. Anti-clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 76. Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 77. Post scale setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 78. Extended attack rate setup for limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 79. Extended attack rate setup for limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 80. De-emphasis filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 81. Bass filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 82. Treble filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 83. Soft volume (increasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 84. Soft volume (decreasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 85. PowerSSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Doc ID 15251 Rev 5 9/77
Description STA339BW
1 Description
The STA339BW is an integrated solution of digital audio processing, digital amplifier control,
and FFX-power output stage, thereby creating a high-power single-chip FFX
comprising high-quality, high-efficiency, all digital amplification.
STA339BW is based on FFX (fully flexible amplification) processor, a STMicroelectronics
proprietary technology. FFX is the evolution and the enlargement of the ST ternary
technology: the new processor can be configured to work in ternary, binary, binary
differential and phase shift PWM modulation schemes.
STA339BW contains the ternary, binary and binary differential implementations, a subset of
the full capability of the FFX processor.
The STA339BW is part of the Sound Terminal™ family that provides full digital audio
streaming to the speaker, offering cost effectiveness, low power dissipation and sound
enrichment.
The STA339BW power section consists of four independent half bridges. These can be
configured via digital control to operate in different modes. 2.1 channels can be provided by
two half bridges and a single full bridge, providing up to 2 x 9 W + 1 x 20 W of power output.
Two channels can be provided by two full bridges, providing up to 2 x 20 W of power. The IC
can also be configured as 2.1 channels with 2 x 20 W provided by the device and external
power for FFX power drive.
Also provided in the STA339BW are a full assortment of digital processing features. This
includes up to 8 programmable 28-bit biquads (EQ) per channel and bass/treble tone
control. Available presets enable a time-to-market advantage by substantially reducing the
amount of software development needed for certain functions. This includes audio preset
volume loudness, preset volume curves and preset EQ settings. There are also new
advanced AM radio interference reduction modes. Dual band DRC dynamically equalizes
the system to provide speaker linear frequency response regardless output power level.
This feature independently processes the two bands, controlling, dynamically, the output
power level in each band and so providing a better sound quality.
The serial audio data input interface accepts all possible formats, including the popular I
format. Three channels of FFX processing are provided. This high-quality conversion from
PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic
range.
®
solution
2
S
10/77 Doc ID 15251 Rev 5
STA339BW Description
1.1 Block diagram
Figure 1. Block diagram
I2S
interface
Vol um e
control
PLL
FFX
I2C
Powe r
control
Protection
current/thermal
Logic
Regulators
Bias
Channel
1A
Channel
1B
Channel
2A
Channel
2B
PowerDigital DSP
Doc ID 15251 Rev 5 11/77
Pin connections STA339BW
2 Pin connections
2.1 Connection diagram
Figure 2. Pin connection PowerSSO-36 (top view)
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD
CONFIG
OUT3B / FFX3B
OUT3A / FFX3A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
D05AU1638
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
GND_PLL
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
TWARN / OUT4A
EAPD / OUT4B
2.2 Pin description
Table 2. Pin description
Pin Type Name Description
1 GND GND_SUB Substrate ground
2I SA I
3 I TEST_MODE This pin must be connected to ground (pull-down)
4 I/O VSS Internal reference at V
5 I/O VCC_REG Internal V
6 O OUT2B Output half bridge 2B
7 GND GND2 Power negative supply
8 Power VCC2 Power positive supply
9 O OUT2A Output half bridge 2A
10 O OUT1B Output half bridge 1B
12/77 Doc ID 15251 Rev 5
2
C select address (pull-down)
reference
CC
CC
- 3.3 V
STA339BW Pin connections
Table 2. Pin description (continued)
Pin Type Name Description
11 Power VCC1 Power positive supply
12 GND GND1 Power negative supply
13 O OUT1A Output half bridge 1A
14 GND GND_REG Internal ground reference
15 Power VDD Internal 3.3 V reference voltage
16 I CONFIG Paralleled mode command
17 O OUT3B / FFX3B PWM out Ch3B / external bridge driver
18 O OUT3A / FFX3A PWM out Ch3A / external bridge driver
19 O EAPD / OUT4B Power down for external bridge / PWM out Ch4B
20 I/O TWARN / OUT4A
21 Power VDD_DIG Digital supply voltage
22 GND GND_DIG Digital ground
23 I PWRDN Power down (pull-up)
24 Power VDD_PLL Positive supply for PLL
Thermal warning from external bridge (pull-up when input)
/ PWM out Ch4A
25 I FILTER_PLL Connection to PLL filter
26 GND GND_PLL Negative supply for PLL
27 I XTI PLL input clock
2
28 I BICKI I
29 I LRCKI I
30 I SDI I
S serial clock
2
S left/right clock
2
S serial data channels 1 and 2
31 I RESET Reset (pull-up)
32 O INT_LINE Fault interrupt
2
33 I/O SDA I
34 I SCL I
C serial data
2
C serial clock
35 GND GND_DIG Digital ground
36 Power VDD_DIG Digital supply voltage
Doc ID 15251 Rev 5 13/77
Electrical specifications STA339BW
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
V
CC
VDD_DIG Digital supply voltage -0.3 - 4 V
VDD_PLL PLL supply voltage -0.3 - 4 V
Operating junction temperature -20 - 150 °C
T
op
Storage temperature -40 - 150 °C
T
stg
Power supply voltage (VCCxA, VCCxB) -0.3 - 30 V
Warning: Stresses beyond those listed in Tabl e 3 above may cause
permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any
other conditions beyond those indicated under
“Recommended operating conditions” are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, power supplies with nominal values rated within
the recommended operating conditions, may experience
some rising beyond the maximum operating conditions for a
short time when no or very low current is sinked (amplifier in
mute state). In this case the reliability of the device is
guaranteed, provided that the absolute maximum ratings are
not exceeded.
3.2 Thermal data
Table 4. Thermal data
Parameter Min Typ Max Unit
R
th j-case
R
th j-amb
T
th-sdj
T
th-w
T
th-sdh
1. See Section 8: Package thermal characteristics on page 73 for details.
14/77 Doc ID 15251 Rev 5
Thermal resistance junction-case (thermal pad) - - 1.5 °C/W
Thermal resistance junction-ambient
Thermal shut-down junction temperature - 150 - °C
Thermal warning temperature - 130 - °C
Thermal shut-down hysteresis - 20 - °C
(1)
---°C/W
STA339BW Electrical specifications
3.3 Recommended operating conditions
Table 5. Recommended operating condition
Symbol Parameter Min Typ Max Unit
V
CC
Power supply voltage (VCCxA, VCCxB) 5 - 26 V
VDD_DIG Digital supply voltage 2.7 3.3 3.6 V
VDD_PLL PLL supply voltage 2.7 3.3 3.6 V
Ambient temperature -20 - 70 °C
T
amb
3.4 Electrical specifications for the digital section
Table 6. Electrical specifications - digital section
Symbol Parameter Conditions Min Typ Max Unit
I
il
I
ih
V
il
V
ih
V
ol
V
oh
I
pu
R
pu
Low-level input current without
pull-up/down device
High-level input current without
pull-up/down device
Low-level input voltage - - -
High-level input voltage -
Low-level output voltage Iol = 2 mA - -
High-level output voltage Ioh = 2 mA
Pull-up/down current - 25 66 125 µA
Equivalent pull-up/down
resistance
Vi = 0 V -10 1 10 µA
Vi = VDD_DIG
= 3.6 V
-10 1 10 µA
0.8 *
VDD_DIG
0.8 *
VDD_DIG
--V
--V
--50-kΩ
0.2 *
VDD_DIG
0.4 *
VDD_DIG
V
V
Doc ID 15251 Rev 5 15/77
Electrical specifications STA339BW
3.5 Electrical specifications for the power section
The specifications given in this section are valid for the operating conditions: VCC=18V,
f=1kHz, f
Table 7. Electrical specifications - power section
Symbol Parameter Conditions Min Typ Max Unit
= 384 kHz, T
sw
= 25° C and RL = 8 Ω, unless otherwise specified.
amb
Output power BTL
W
THD = 10% - 20 -
Po
THD = 1% - 4 -
THD = 1% - 16 -
Output power SE
W
THD = 10% - 5 -
R
dsON
Power Pchannel/Nchannel MOSFET (total
bridge)
l
= 1.5 A - 180 250 mΩ
d
gP Power Pchannel RdsON matching ld = 1.5 A 95 - - %
gN Power Nchannel RdsON matching l
Idss Power Pchannel/Nchannel leakage V
I
LDT
I
HDT
t
r
t
f
V
CC
Low current dead time (static) Resistive load
High current dead time (dynamic) Iload = 1.5 A
Rise time Resistive load
Fall time Resistive load
Supply voltage operating voltage - 5 - 26 V
= 1.5 A 95 - - %
d
= 20 V - - 10 µA
CC
(1)
(1)
(1)
(1)
- 8 15 ns
- 15 30 ns
- 10 18 ns
- 10 18 ns
Supply current from VCC in power down PWRDN = 0 - 0.1 1 mA
PCM Input signal = -
I
vcc
Supply current from V
in operation
CC
60 dBfs,
Switching frequency
- 52 60 mA
= 384 kHz,
No LC filters
I
I
I
vdd
lim
sc
Supply current FFX processing (reference
only)
Overcurrent limit
Short circuit protection Hi-Z output 3.8 4.8 - A
Internal clock =
49.152 MHz
(2)
-5570mA
3.03.84.0A
UVL Undervoltage protection - - 3.5 4.3 V
t
min
Output minimum pulse width No load 20 30 60 ns
DR Dynamic range - - 100 - dB
SNR
Signal to noise ratio, ternary mode A-weighted - 100 - dB
Signal to noise ratio binary mode - - 90 - dB
FFX stereo mode,
<5 kHz
PSSR Power supply rejection ratio
V
RIPPLE
= 1 V RMS
Audio input =
dither only
16/77 Doc ID 15251 Rev 5
-80-dB
STA339BW Electrical specifications
Table 7. Electrical specifications - power section (continued)
Symbol Parameter Conditions Min Typ Max Unit
FFX stereo mode,
THD+N Total harmonic distortion + noise
X
TA LK
Crosstalk
Peak efficiency, FFX mode
η
Peak efficiency,binary modes
1. Refer to Figure 5: Test circuit 1.
2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled
refer to the Isc.
Po = 1 W
f=1kHz
FFX stereo mode,
<5 kHz
One channel driven
at 1 W
Other channel
measured
Po = 2 x 20 W
into 8 Ω
Po = 2 x 9 W into 4 Ω
+ 1 x 20 W into 8 Ω
-0.2-%
-80-dB
-90-
%
-87-
Doc ID 15251 Rev 5 17/77
Electrical specifications STA339BW
3.6 Power on/off sequence
Figure 3. Power-on sequence
VCC
VCC
VCC
VCC
VCC
VDD_Dig
VDD_Dig
VDD_Dig
VDD_Dig
VDD_Dig
XTI
XTI
XTI
XTI
XTI
Reset
Reset
Reset
Reset
Reset
2
2
2
2
2
C
C
C
C
C
I
I
I
I
I
PWDN
PWDN
PWDN
PWDN
PWDN
Note: no specific VCC and
VDD_DIG turn
is required
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
−
on sequence
TR
TR
TR
TR
TR
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
TC
TC
TC
TC
TC
CMD0 CMD1 CMD2
CMD0 CMD1 CMD2
CMD0 CMD1 CMD2
CMD0 CMD1 CMD2
CMD0 CMD1 CMD2
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I
Note: The definition of a stable clock is when f
Section 6.2.3 on page 30 gives information on setting up the I
Figure 4. Power-off sequence for pop-free turn-off
VCC
VCC
VDD_Dig
VDD_Dig
XTI
XTI
Soft Mute
Soft Mute
Reg. 0x07
Reg. 0x07
Data 0xFE
Data 0xFE
Soft EAPD
Soft EAPD
Reg. 0x05
Reg. 0x05
Bit 7 = 0
Bit 7 = 0
Don’t care
Don’t care
2
C program, sequence start: 1ms
- f
max
< 1 MHz.
min
FE
FE
2
S interface.
Note: no specific VCC and
VDD_DIG turn
is required
Don’t care
Don’t care
Don’t care
Don’t care
−
off sequence
Don’t care
Don’t care
Don’t care
Don’t care
18/77 Doc ID 15251 Rev 5
STA339BW Electrical specifications
3.7 Testing
3.7.1 Functional pin definition
Table 8. Functional pin definition
Pin name Number Logic value IC status
PWRDN 23
0 Low consumption
1 Normal operation
0
TWARN 20
1 Normal operation
0
EAPD 19
1 Normal operation
Figure 5. Test circuit 1
Low current dead time = MAX(DTr, DTf)
Duty cycle = 50%
INxY
A temperature warning is indicated by the external power
stage
Low consumption for power stage
All internal regulators are switched off
+Vcc
OUTxY
OUTxY
DTr DTf
Rload = 8
Ω
+
-
Vcc
(3/4)Vcc
(1/2)Vcc
(1/4)Vcc
t
vdc = Vcc/2
gnd
Figure 6. Test circuit 2
High current dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=A Duty cycle=B
DTin(A)
INxA
Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure
DTout(A)
Q1
OUTxA
Q3
Iout
Rload = 4 Ω
470nF
DTout(B) DTin(B)
10µ10µ
Iout
470nF470nF
Q2
OUTxB
Q4
D06AU1651_00
Doc ID 15251 Rev 5 19/77
INxB
Processing data paths STA339BW
4 Processing data paths
The whole processing chain is composed of two consecutive sections. In the first one
dual-channel processing is implemented, as described below. Then each channel is fed into
the post-mixing block where there is a choice of processing, either the dual-band DRC is
disabled or it is enabled. When B
output configuration and with cross-over filters enabled, is used. When B
the 2.0 output configuration with cross-over filters for defining the cutoff frequency of the two
bands is used.
The first section, Figure 7, begins with a 2x oversampling FIR filter allowing a 2 * fs audio
processing. Then a selectable high-pass filter removes the DC level (enabled if HFB = 0).
The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected
configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).
By default, four independent filters per channel are enabled, plus the preconfigured deemphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).
If the coefficient sets are linked (BQL = 1) then it is possible to use the de-emphasis, bass
and treble filter in a user defined configuration (provided the relevant BQx bits are set to 1).
In other words both channels use the same processing coefficients and can have up to 7
filters each. Note that if BQL = 0 the BQx bits are ignored and the 5th, 6th and 7th filters are
configured as de-emphasis, bass and treble controls, respectively.
2
DRC is disabled a third channel, typically used in 2.1
2
DRC is enabled
Moreover the common 8th filter, from the subsequent processing section, can be available
on both channels (provided the pre-defined cross-over frequencies are not used,
XO[3:0] = 0, and the dual-band DRC is not used).
In the second section, mixing and crossover filters are available. If B
(lower schematic in Figure 8) they are fully user-programmable and allow a third channel
(2.1 outputs) to be generated. Alternatively, in B
2
DRC mode (upper schematic in Figure 8),
2
DRC is not enabled
those blocks will be used to split the sub-band and define the cutoff frequencies of the two
bands. A prescaler and a final post scaler allow full control over the signal dynamics before
and after, respectively, the filtering stages. A mixer function is also available.
Figure 7. Left and right processing part 1
Sampling
Sampling
frequency = fs
frequency = fs
From
From
2
2
S input
S input
I
I
interface
interface
sampling
sampling
sampling
sampling
x2
x2
FIR
FIR
x2
x2
over
over
FIR
FIR
over
over
x2
x2
FIR
FIR
x2
x2
over
over
FIR
FIR
over
over
Sampling
Sampling
frequency = 2 * fs
frequency = 2 * fs
Hi-pass
Hi-pass
PreScale
Pre-scale
PreScale
Pre-scale
If HPB=0
If HPB=0
Hi-pass
Hi-pass
PreScale
Pre-scale
PreScale
Pre-scale
Pass
Pass
filter
filter
Filter
Filter
Pass
Pass
Filter
filter
Filter
filter
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
User-defined filters
User-defined filters
If DSPB=0 and C1EQBP=0
If DSPB=0 and C1EQBP=0
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
Biquad#1Biquad#2Biquad#3Biquad
#4
#4
#4
#4
#4
#4
#4
#4
If BQ5=1
If BQ5=1
and BQL=1
and BQL=1
Biquad
Biquad
#5
#5
De-Emph.
De-Emph.
If DEMP=0
If DEMP=0
If BQ5=1
If BQ5=1
and BQL=1
and BQL=1
Biquad
Biquad
#5
#5
De-Emph.
De-Emph.
If BQ6=1
IF BQ7=1
If BQ6=1
IF BQ7=1
and BQL=1
and BQL=1
and BQL=1
and BQL=1
Biquad
Biquad
Biquad
Biquad
#6
#6
Bass Treble
Bass Treble
If C1TCB=0
If C1TCB=0
BTC: bass boost/cut
BTC: bass boost/cut
TTC: treble bo ost/cut
TTC: treble bo ost/cut
If BQ6=1
IF BQ7=1
If BQ6=1
IF BQ7=1
and BQL=1
and BQL=1
and BQL=1
and BQL=1
Biquad
Biquad
Biquad
Biquad
#6
#6
Bass Treble
Bass Treble
#7
#7
L
L
L
L
#7
#7
L
L
R
R
If HPB=0
If HPB=0
User-defined filters
User-defined filters
If DSPB=0 and C2EQBP=0
If DSPB=0 and C2EQBP=0
20/77 Doc ID 15251 Rev 5
If DEMP=0
If DEMP=0
If C2TCB=0
If C2TCB=0
BTC: bass boost/cut
BTC: bass boost/cut
TTC: treble bo ost/cut
TTC: treble bo ost/cut
STA339BW Processing data paths
Figure 8. Processing part 2
Ch3
Dual-band DRC enabled
L
L
L
L
R
R
R
R
User-defined mix coeffici ents
User-defined mix coeffici ents
C1Mx1
C1Mx1 =
C1Mx1
C1Mx1 =
0x7FFFFF
0x7FFFFF
C1Mx2 =
C1Mx2 =
C1Mx2
C1Mx2
0x00000
0x00000
C2Mx1
C2Mx1
C2Mx1=
C2Mx1=
0x000000
0x000000
C2Mx2
C2Mx2 =
C2Mx2
C2Mx2 =
0x7FFFFF
0x7FFFFF
C3Mx1
C3Mx1 =
C3Mx1
C3Mx1 =
0x40000
0x40000
C3Mx2
C3Mx2 =
C3Mx2
C3Mx2 =
0x400000
0x400000
Hi-Pass XO
Hi-Pass XO
B2DRC
B2DRC
Filter
+
+
+
+
+
+
+
+
+
+
+
+
Filter
Hi-pass
Hi-pass
filter
filter
Hi-Pass XO
Hi-Pass XO
B2DRC
B2DRC
Filter
Filter
Hi-pass
Hi-pass
filter
filter
Crossover frequency det ermined by XO setting
Crossover frequency det ermined by XO setting
User-defined if XO = 0000
User-defined if XO = 0000
-
-++
+
-
-++
+
Ch3
Volume
Volume
Ch1
Ch1
Volume
Volume
Ch2
Ch2
Volume
Volume
Ch3
Ch3
Volume
Volume
DRC2
DRC2
Vol
Vol
And
And
DRC1
DRC1
Limiter
Limiter
DRC1
DRC1
DRC2
DRC2
+
+
+
+
B2DRC Enabled
B2DRC Enabled
Post scale
Post scale
Post-scale
Post-scale
Post scale
Post-scale
Post scale
Post-scale
Dual-band DRC disabled
C1Mx1
C1Mx1
C1Mx1
L
L
L
L
R
R
R
R
C1Mx1
+
+
+
+
C1Mx2
C1Mx2
C1Mx2
C1Mx2
Channel 1/2
Channel 1/2
Hi-Pass XO
Hi-Pass XO
Biquad #5
Biquad #5
Filter
Filter
--------------
--------------
Hi-pass XO
Hi-pass XO
filter
filter
Vol
Volume
Vol
Volume
And
and
And
and
Limiter
Limiter
Limiter
Limiter
Post scale
Post-scale
Post scale
Post-scale
C2Mx1
C2Mx1
C2Mx1
C2Mx1
+
+
+
+
C2Mx2
C2Mx2
C2Mx2
C2Mx2
C3Mx1
C3Mx1
C3Mx1
C3Mx1
+
+
+
+
C3Mx2
C3Mx2
C3Mx2
C3Mx2
User-defined mix coefficients
User-defined mix coefficients
Crossover f requency determined by XO setting
Crossover f requency determined by XO setting
User defined if XO = 0000
User defined if XO = 0000
Channel 1/2
Channel 1/2
Hi-Pass XO
Hi-Pass XO
Biquad #5
Biquad #5
Filter
Filter
--------------
--------------
Hi-pass XO
Hi-pass XO
filter
filter
Channel 3
Channel 3
Lo-Pass XO
Lo-Pass XO
Biquad
Biquad
Filter
Filter
--------------
--------------
Low-pass XO
Low-pass XO
filter
filter
Vol
Volume
Vol
Volume
And
and
And
and
Limiter
Limiter
Limiter
Limiter
Vol
Volume
Vol
Volume
And
and
And
and
Limiter
Limiter
Limiter
Limiter
Post scale
Post-scale
Post scale
Post-scale
Post scale
Post-scale
Post scale
Post-scale
B2DRC Disabled
B2DRC Disabled
Doc ID 15251 Rev 5 21/77
I2C bus specification STA339BW
5 I2C bus specification
The STA339BW supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA339BW is always a slave device in all of its communications. It can operate at up to
400 kb/s (fast-mode bit rate). The STA339BW I
5.1 Communication protocol
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
2
C interface is a slave only interface.
5.1.3 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA339BW and the bus master.
5.1.4 Data input
During the data input the STA339BW samples the SDA signal on the rising edge of clock
SCL. For correct device operation the SDA signal must be stable during the rising edge of
the clock and the data can change only when the SCL line is low.
5.2 Device addressing
To start communication between the master and the STA339BW, the master must initiate
with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)
corresponding to the device select address and read or write mode.
The seven most significant bits are the device address identifiers, corresponding to the I
bus definition. In the STA339BW the I
the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode
and to 0 for write mode. After a START condition the STA339BW identifies on the bus the
device address and if a match is found, acknowledges the identification on the SDA bus
during the 9th bit time. The byte following the device identification byte is the internal space
address.
2
C interface has two device addresses depending on
2
C
22/77 Doc ID 15251 Rev 5
STA339BW I2C bus specification
5.3 Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA339BW acknowledges this and the writes for the byte of internal address. After
receiving the internal byte address the STA339BW again responds with an
acknowledgement.
5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the
STA339BW. The master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
5.4 Read operation
5.4.1 Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA339BW acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
5.4.2 Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA339BW. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
5.4.3 Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA339BW acknowledges this and then the master writes the internal address
byte. After receiving, the internal byte address the STA339BW again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA339BW acknowledges this and then responds
by sending one byte of data. The master then terminates the transfer by generating a STOP
condition.
5.4.4 Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA339BW. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
Doc ID 15251 Rev 5 23/77
I2C bus specification STA339BW
A
A
A
A
A
5.4.5 Write mode sequence
Figure 9. Write mode sequence
BYTE
WRITE
DEV-ADDR
START
MULTIBYTE
WRITE
DEV-ADDR
START
5.4.6 Read mode sequence
Figure 10. Read mode sequence
RW=
HIGH
ACK
RW
ACK
RW
ACK
ACK
RW
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV-ADDR
START
DEV-ADDR
START
DEV-ADDR
START
DEV-ADDR
START
RW
RW
DATA
SUB-ADDR
DATA
SUB-ADDR
ACK
ACK
NO ACK
ACK
ACK
ACK
SUB-ADDR
SUB-ADDR
STOP
START RW
START RW
ACK
ACK
DEV-ADDR
DATA
DEV-ADDR
DATA IN
CK
STOP
DATA IN
CK
DATA IN
CK
STOP
ACK
ACK
ACK
DATA
DATA
DATA
NO ACK
NO ACK
CK
STOP
STOP
DATA
CK NO ACK
DATA
STOP
24/77 Doc ID 15251 Rev 5
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