– 2 channels of binary PWM (stereo mode)
– 2 channels of ternary PWM (stereo mode)
PowerSSO-36 with exposed pad down
2 channels of 24-bit DDX
100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
2
I
C control with selectable device address
Digital gain -80 dB to +48 dB in 0.5-dB steps
Software volume update
Individual channel and master gain/attenuation
Individual channel and master software and
®
hardware mute
Independent channel volume bypass
Automatic zero-detect mute
Automatic invalid input detect mute
2-channel I
Selectable clock input ratio
Input channel mapping
Automatic volume control for limiting maximum
2
S input data Interface
power
96-kHz internal processing sample rate, 24-bit
precision
Advanced AM interference frequency
switching and noise suppression modes
Thermal-overload and short-circuit protection
embedded
Video application: 576 * f
input mode support
S
Table 1.Device summary
Order codePackagePackaging
STA333WPowerSSO-36 EPDTube
STA333W13TRPowerSSO-36 EPDTape and reel
Applications
LCD
DVD
Cradle
Digital speaker
Wireless-speaker cradle
Description
The STA333W is an integrated circuit comprising
digital audio processing, digital amplifier control
and DDX
power, single-chip DDX
amplification with high quality and high efficiency.
The STA333W power section consists of four
independent half-bridges stages. These can be
configured via digital control to operate in different
modes. 2 channels can be provided by two full
bridges, providing up to 20 W + 20 W of power.
Also provided in the STA333W are new advanced
AM radio interference reduction modes. The serial
audio data input interface accepts all possible
formats, including the popular I
channels of DDX
The STA333W is part of the Sound Terminal™
family that provides full digital audio streaming to
the speaker offering cost effectiveness, low power
dissipation and sound enrichment.
Figure 15.FFT 0 dBfs (V
Figure 16.FFT -60 dBfs (V
Figure 17.THD vs. frequency (V
Figure 18.FFT 0 dBfs (V
Figure 19.FFT -60 dBfs (V
Figure 20.THD vs. frequency (V
Figure 21.Double-layer PCB with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44
0: power stage is switched off then the PLL is also
switched off (this operation take 13 million clock cycles)
1: normal operation
24PWRVDD_PLLPositive supply for PLL
25IFILTER_PLLConnection to PLL filter
26PWRGND_PLLNegative supply for PLL
27IXTIPLL input clock, 256 * f
28IBICKII2S serial clock
2
29ILRCKII
30ISDII
S left/right clock
2
S serial data channel
Reset:
31IRESET
0: reset state, power stage is switched off, all registers are
set to default value
1: normal operation
32OINT_LINEFault interrupt
33I/OSDAI
34ISCLI
2
C serial data, used as SDA_OUT
2
C serial clock
35PWRGND_DIGDigital ground
36PWRVDD_DIGDigital supply
--EP
Exposed pad for ground-plane heatsink, to be connected
to GND
, or 384 * f
S
S
Doc ID 13365 Rev 29/49
Pin descriptionSTA333W
2.3 Thermal data
Table 3.Thermal data
SymbolParameterMinTypMaxUnit
R
Th(j-case)
T
sd
T
w
T
hsd
Thermal resistance junction to case (thermal pad)-1.5 2.0°C/W
Thermal-shutdown junction temperature140150160°C
Thermal-warning temperature-130-°C
Thermal-shutdown hysteresis182022°C
10/49Doc ID 13365 Rev 2
STA333WElectrical specification
3 Electrical specification
3.1 Absolute maximum ratings
Table 4.Absolute maximum ratings
SymbolParameterMinTypMaxUnit
V
CC
V
DD
I
L
T
op
T
stg
Analog supply voltage (pins VCCx)--23V
Digital supply voltage (pins VDD_DIG)--4.0V
Logic input interface-0.3-4.0V
Operating junction temperature0-150°C
Storage temperature-40-150°C
Warning:Stresses beyond those listed in Table 4: Absolute maximum
ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in
Table 5: Recommended operating conditions are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, a power supply with nominal value rated within
the limits of the recommended operating conditions, may
experience some rising beyond the maximum operating
conditions for a short time when no or very low current is
being sinked (amplifier in mute state). In this case the
reliability of the device is guaranteed, provided that the
absolute maximum ratings are not exceeded.
3.2 Recommended operating conditions
Table 5.Recommended operating conditions
SymbolParameterMinTypMaxUnit
V
V
I
T
CC
DD
L
amb
Analog supply voltage (VCCx)4.5-20.0V
Digital supply voltage (VDD_DIG)2.73.33.6V
Logic input interface2.73.33.6V
Ambient temperature0-70°C
Doc ID 13365 Rev 211/49
Electrical specificationSTA333W
3.3 Electrical specifications - digital section
Table 6.Electrical characteristics for digital section
Symbol Parameter ConditionsMinTypMaxUnit
I
il
I
ih
V
il
V
ih
V
ol
V
oh
I
pu
R
pu
Input current, no pull-up or
pull-down resistor
Low-level input voltage---
High-level input voltage-
Low-level output voltageIol = 2 mA--
High-level output voltageIoh = 2 mA
Pull-up current-2566125µA
Equivalent pull-up
resistance
= 0 V--±10 µA
V
i
Vi = VDD = 3.6 V--±10µA
--50-kΩ
3.4 Electrical specifications - power section
The specifications in Ta bl e 7 below are given for the conditions VCC = 18 V, VDD = 3.3 V,
f
= 384 kHz, T
SW
Table 7.Electrical specifications for power section
SymbolParameterConditionsMinTypMaxUnit
= 25 °C and RL = 8 Ω, unless otherwise specified.
amb
0.8 *
--V
V
DD
0.8 *
--V
V
DD
0.2 *
V
DD
0.4 *
V
DD
V
V
PoOutput power BTL
THD = 1%-16-
THD = 10%-20-
R
l
dss
gP
gN
I
LDT
I
HDT
t
r
t
f
dsON
Power P-channel/N-channel
MOSFET (total bridge)
Power P-channel/N-channel
leakage
Power P-channel R
dsON
matching
Power N-channel R
dsON
matching
Low-current dead time
(static)
High-current dead time
(dynamic)
Rise time
Fall time
ld = 1 A-180250mΩ
V
= 18 V--10µA
CC
ld = 1 A95--%
ld = 1 A95--%
Resistive load,
refer to Figure 5
Refer to Figure 6- 1020ns
Resistive load,
refer to Figure 5
Resistive load,
refer to Figure 5
12/49Doc ID 13365 Rev 2
W
-510ns
-810ns
-810ns
STA333WElectrical specification
Table 7.Electrical specifications for power section (continued)
SymbolParameterConditionsMinTypMaxUnit
V
CC
I
VCC
Supply voltage -4.5-20V
Supply current from VCC in
power down
PWRDN = 03060200µA
PCM input signal = -60 dBfs
in
Supply current from V
operation
CC
Switching frequency =
384 kHz
- 3050mA
No LC filters
I
VDD_DIG
Supply current for DDX
processing (reference only)
Internal clock = 49.152 MHz103050mA
Supply current in standby-81125mA
I
LIM
I
SCP
V
UVP
t
min
THD+N
Overcurrent limitNon-linear output
Short-circuit protectionHigh-impedance output
Undervoltage protection
threshold
Output minimum pulse
width
Total harmonic distortion
and noise
--3.5 4.3V
No load203060ns
DXX stereo mode, Po = 1 W,
f = 1 kHz
(1)
2.23.54.3A
(2)
2.73.85.0A
-0.050.2%
DRDynamic range--100-dB
Signal to noise ratio in
ternary mode
A-weighted-100-
SNR
Signal to noise ratio in
binary mode
A-weighted-90-
DXX stereo mode, < 5 kHz,
PSRRPower supply rejection ratio
V
RIPPLE
= 1 V RMS
-80-dB
audio input = dither only
DXX stereo mode, < 5 kHz,
X
TA L K
Crosstalk
One channel driven at 1 W
-80-dB
the other channel measured
η
1. The I
The current limit is active when OCRB = 0 (see Table 23: Overcurrent warning detect adjustment bypass
on page 28. When OCRB = 1 then I
2. The I
configuration. The short-circuit current is applicable when OCRB = 1 (see Table 23: Overcurrent warning
detect adjustment bypass on page 28.
Peak efficiency
in DXX mode
data is for 1 channel of BTL configuration, thus, 2 * I
LIM
current limit data is for 1 channel of BTL configuration, thus, 2 * I
SCP
Po = 2 x 20 W into 8 Ω-90-%
drives the 2-channel BTL configuration.
LIM
applies.
SC
drives the 2-channel BTL
SCP
dB
Doc ID 13365 Rev 213/49
Electrical specificationSTA333W
3.5 Power-on/off sequences
The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn
on and turn off.
Figure 3.Power-on sequence
No specific VCC and VDD_DIG turn-on sequence is required
VCC
VCC
VCC
Don’t care
Don’t care
VDD_Dig
VDD_Dig
VDD_DIG
XTI
XTI
XTI
Reset
Reset
RESET
PWRDN
PWRDN
PWRDN
Bit EAPD
Soft EAPD
Soft EAPD
Register 0x05
Reg. 0x05
Reg. 0x05Bit 7 = 1
Bit 7 = 1
Don’t care
Don’t care
Don’t care
Don’t care
TR
TR
TC
TC
TR = mimimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I
Clock stable means: fmax - fmin < 1 MHz
Figure 4.Power-off sequence
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VCC
VCC
VDD_DIG
VDD_Dig
VDD_Dig
XTI
XTI
XTI
Mute
Soft Mute
Soft Mute
Register 0x07
Reg. 0x07
Reg. 0x07Data 0xFE
Data 0xFE
Bit EAPD
Soft EAPD
Soft EAPD
Register 0x05
Reg. 0x05
Reg. 0x05Bit7 = 0
Bit7 = 0
Don’t care
Don’t care
2
C program sequence start: 1 ms
FE
FE
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
14/49Doc ID 13365 Rev 2
STA333WElectrical specification
3.6 Testing
Figure 5.Test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
Duty cycle = 50%
INxY
M58
M57
gnd
OUTxY
R 8Ω
DTfDTr
+
V67 =
-
vdc = Vcc/2
D03AU1458
Figure 6.Current dead-time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=ADuty cycle=B
M58
DTin(A)
INA
M57
Q1
OUTA
Iout=4A
Lout = 1.5 A
Q3
DTout(A)
C69
470nF
Rload=8Ω
C71 470nF
M64
OUTB
Q2
M63
Q4
DTout(B)DTin(B)
L68 22µL67 22µ
Iout=4A
Lout = 1.5 A
C70
470nF
INB
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
Doc ID 13365 Rev 215/49
D03AU1517
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