ST STA333W User Manual
STA333W
2-channel high-efficiency digital audio system
Sound Terminal™
Features
Wide supply-voltage range (4.5 V - 20 V)
2 power output configurations
– 2 channels of binary PWM (stereo mode)
– 2 channels of ternary PWM (stereo mode)
PowerSSO-36 with exposed pad down
2 channels of 24-bit DDX
100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
2
I
C control with selectable device address
Digital gain -80 dB to +48 dB in 0.5-dB steps
Software volume update
Individual channel and master gain/attenuation
Individual channel and master software and
®
hardware mute
Independent channel volume bypass
Automatic zero-detect mute
Automatic invalid input detect mute
2-channel I
Selectable clock input ratio
Input channel mapping
Automatic volume control for limiting maximum
2
S input data Interface
power
96-kHz internal processing sample rate, 24-bit
precision
Advanced AM interference frequency
switching and noise suppression modes
Thermal-overload and short-circuit protection
embedded
Video application: 576 * f
input mode support
S
Table 1. Device summary
Order code Package Packaging
STA333W PowerSSO-36 EPD Tube
STA333W13TR PowerSSO-36 EPD Tape and reel
Applications
LCD
DVD
Cradle
Digital speaker
Wireless-speaker cradle
Description
The STA333W is an integrated circuit comprising
digital audio processing, digital amplifier control
and DDX
power, single-chip DDX
amplification with high quality and high efficiency.
The STA333W power section consists of four
independent half-bridges stages. These can be
configured via digital control to operate in different
modes. 2 channels can be provided by two full
bridges, providing up to 20 W + 20 W of power.
Also provided in the STA333W are new advanced
AM radio interference reduction modes. The serial
audio data input interface accepts all possible
formats, including the popular I
channels of DDX
The STA333W is part of the Sound Terminal™
family that provides full digital audio streaming to
the speaker offering cost effectiveness, low power
dissipation and sound enrichment.
®
power output stage to create a high-
®
®
processing are provided.
PowerSSO-36 package
with exposed
pad down (EPD)
solution for all-digital
2
S format. Three
January 2010 Doc ID 13365 Rev 2 1/49
www.st.com
49
Contents STA333W
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Power-on/off sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5I
2
C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/49 Doc ID 13365 Rev 2
STA333W Contents
5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 Volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 32
6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 32
6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2.3 Channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Automodes™ register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Channel configuration registers (addr 0x0E, 0x0F) . . . . . . . . . . . . . . . . . 35
6.5 Variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 35
6.6 Variable distortion compensation registers (addr 0x29, 0x2A) . . . . . . . . . 36
6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C) . . . . . . . . . . 36
6.8 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) . . . . . . . . . . . . . . . . . 37
6.10 Postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.11 Output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.11.1 Thermal and overcurrent warning output limit register . . . . . . . . . . . . . 38
7 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1 Applications scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 Characterization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Doc ID 13365 Rev 2 3/49
Contents STA333W
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/49 Doc ID 13365 Rev 2
STA333W List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. MCS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Thermal warning recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Thermal warning adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Fault detect recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. Support serial audio input formats for MSB first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. Supported serial audio input formats for LSB-First (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Channel input mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. DDX compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23. Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 24. Zero detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 26. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 27. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 28. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 31. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 32. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 33. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 35. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 36. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 37. Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 38. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 39. Master mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 40. Channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. Master volume offset as a function of MV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 42. Channel volume as a function of CxV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 43. AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 44. Automodes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 45. Status bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 46. Output limit values for thermal and overcurrent warnings. . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 47. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 48. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Doc ID 13365 Rev 2 5/49
List of figures STA333W
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connection (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Current dead-time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. I
Figure 8. Left justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Write-mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Read-mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Output power vs. supply voltage (THD = 1%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15. FFT 0 dBfs (V
Figure 16. FFT -60 dBfs (V
Figure 17. THD vs. frequency (V
Figure 18. FFT 0 dBfs (V
Figure 19. FFT -60 dBfs (V
Figure 20. THD vs. frequency (V
Figure 21. Double-layer PCB with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22. Power derating curve for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 23. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2
S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
CC
= 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CC
= 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CC
CC
= 12 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CC
= 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
= 18 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
CC
6/49 Doc ID 13365 Rev 2
STA333W Block diagram
1 Block diagram
Figure 1. Block diagram
I2S
interface
Vol ume
control
PLL
DDX
I2C
Powe r
control
Protection
current/thermal
Logic
Regulators
Bias
Channel
1A
Channel
1B
Channel
2A
Channel
2B
PowerDigital DSP
Doc ID 13365 Rev 2 7/49
Pin description STA333W
2 Pin description
2.1 Pin out
Figure 2. Pin connection (package top view)
GND_SUB
SA
TEST_MODE
VSS
VCC_REG
OUT2B
GND2
VCC2
OUT2A
OUT1B
VCC1
GND1
OUT1A
GND_REG
VDD_REG
CONFIG
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
EP
exposed pad (down)
Connect to ground
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
D05AU1638
VDD_DIG
GND_DIG
SCL
SDA
INT_LINE
RESET
SDI
LRCKI
BICKI
XTI
GND_PLL
FILTER_PLL
VDD_PLL
PWRDN
GND_DIG
VDD_DIG
N.C.
N.C.
2.2 Pin list
Table 2. Pin description
Number Type Name Description
1 PWR GND_SUB Substrate ground
2I SA I
3 I TEST_MODE This pin must be connected to ground
4 I/O VSS Internal reference at V
5 I/O VCC_REG Internal V
6 O OUT2B Output half bridge 2B
7 PWR GND2 Power negative supply
8 PWR VCC2 Power positive supply
9 O OUT2A Output half bridge 2A
8/49 Doc ID 13365 Rev 2
2
C select address
CC
reference
- 3.3 V
CC
STA333W Pin description
Table 2. Pin description (continued)
Number Type Name Description
10 O OUT1B Output half bridge 1B
11 PWR VCC1 Power positive supply
12 PWR GND1 Power negative supply
13 O OUT1A Output half bridge 1A
14 PWR GND_REG Internal ground reference
15 PWR VDD_REG Internal 3.3-V reference voltage
16 I CONFIG Paralleled mode command
17 - N.C. No internal connection
18 - N.C. No internal connection
19 - N.C. No internal connection
20 - N.C. No internal connection
21 PWR VDD_DIG Positive supply digital
22 PWR GND_DIG Digital ground
Power down:
23 I PWRDN
0: power stage is switched off then the PLL is also
switched off (this operation take 13 million clock cycles)
1: normal operation
24 PWR VDD_PLL Positive supply for PLL
25 I FILTER_PLL Connection to PLL filter
26 PWR GND_PLL Negative supply for PLL
27 I XTI PLL input clock, 256 * f
28 I BICKI I2S serial clock
2
29 I LRCKI I
30 I SDI I
S left/right clock
2
S serial data channel
Reset:
31 I RESET
0: reset state, power stage is switched off, all registers are
set to default value
1: normal operation
32 O INT_LINE Fault interrupt
33 I/O SDA I
34 I SCL I
2
C serial data, used as SDA_OUT
2
C serial clock
35 PWR GND_DIG Digital ground
36 PWR VDD_DIG Digital supply
--EP
Exposed pad for ground-plane heatsink, to be connected
to GND
, or 384 * f
S
S
Doc ID 13365 Rev 2 9/49
Pin description STA333W
2.3 Thermal data
Table 3. Thermal data
Symbol Parameter Min Typ Max Unit
R
Th(j-case)
T
sd
T
w
T
hsd
Thermal resistance junction to case (thermal pad) - 1.5 2.0 °C/W
Thermal-shutdown junction temperature 140 150 160 °C
Thermal-warning temperature - 130 - °C
Thermal-shutdown hysteresis 18 20 22 °C
10/49 Doc ID 13365 Rev 2
STA333W Electrical specification
3 Electrical specification
3.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
V
CC
V
DD
I
L
T
op
T
stg
Analog supply voltage (pins VCCx) - - 23 V
Digital supply voltage (pins VDD_DIG) - - 4.0 V
Logic input interface -0.3 - 4.0 V
Operating junction temperature 0 - 150 °C
Storage temperature -40 - 150 °C
Warning: Stresses beyond those listed in Table 4: Absolute maximum
ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated in
Table 5: Recommended operating conditions are not implied.
Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability. In the real
application, a power supply with nominal value rated within
the limits of the recommended operating conditions, may
experience some rising beyond the maximum operating
conditions for a short time when no or very low current is
being sinked (amplifier in mute state). In this case the
reliability of the device is guaranteed, provided that the
absolute maximum ratings are not exceeded.
3.2 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
V
V
I
T
CC
DD
L
amb
Analog supply voltage (VCCx) 4.5 - 20.0 V
Digital supply voltage (VDD_DIG) 2.7 3.3 3.6 V
Logic input interface 2.7 3.3 3.6 V
Ambient temperature 0 - 70 °C
Doc ID 13365 Rev 2 11/49
Electrical specification STA333W
3.3 Electrical specifications - digital section
Table 6. Electrical characteristics for digital section
Symbol Parameter Conditions Min Typ Max Unit
I
il
I
ih
V
il
V
ih
V
ol
V
oh
I
pu
R
pu
Input current, no pull-up or
pull-down resistor
Low-level input voltage - - -
High-level input voltage -
Low-level output voltage Iol = 2 mA - -
High-level output voltage Ioh = 2 mA
Pull-up current - 25 66 125 µA
Equivalent pull-up
resistance
= 0 V - - ±10 µA
V
i
Vi = VDD = 3.6 V - - ±10 µA
--50-kΩ
3.4 Electrical specifications - power section
The specifications in Ta bl e 7 below are given for the conditions VCC = 18 V, VDD = 3.3 V,
f
= 384 kHz, T
SW
Table 7. Electrical specifications for power section
Symbol Parameter Conditions Min Typ Max Unit
= 25 °C and RL = 8 Ω, unless otherwise specified.
amb
0.8 *
--V
V
DD
0.8 *
--V
V
DD
0.2 *
V
DD
0.4 *
V
DD
V
V
Po Output power BTL
THD = 1% - 16 -
THD = 10% - 20 -
R
l
dss
gP
gN
I
LDT
I
HDT
t
r
t
f
dsON
Power P-channel/N-channel
MOSFET (total bridge)
Power P-channel/N-channel
leakage
Power P-channel R
dsON
matching
Power N-channel R
dsON
matching
Low-current dead time
(static)
High-current dead time
(dynamic)
Rise time
Fall time
ld = 1 A - 180 250 mΩ
V
= 18 V --10µA
CC
ld = 1 A 95--%
ld = 1 A 95--%
Resistive load,
refer to Figure 5
Refer to Figure 6 - 1020ns
Resistive load,
refer to Figure 5
Resistive load,
refer to Figure 5
12/49 Doc ID 13365 Rev 2
W
- 5 10 ns
- 8 10 ns
- 8 10 ns
STA333W Electrical specification
Table 7. Electrical specifications for power section (continued)
Symbol Parameter Conditions Min Typ Max Unit
V
CC
I
VCC
Supply voltage - 4.5 - 20 V
Supply current from VCC in
power down
PWRDN = 0 30 60 200 µA
PCM input signal = -60 dBfs
in
Supply current from V
operation
CC
Switching frequency =
384 kHz
- 3050mA
No LC filters
I
VDD_DIG
Supply current for DDX
processing (reference only)
Internal clock = 49.152 MHz 10 30 50 mA
Supply current in standby - 8 11 25 mA
I
LIM
I
SCP
V
UVP
t
min
THD+N
Overcurrent limit Non-linear output
Short-circuit protection High-impedance output
Undervoltage protection
threshold
Output minimum pulse
width
Total harmonic distortion
and noise
- - 3.5 4.3 V
No load 20 30 60 ns
DXX stereo mode, Po = 1 W,
f = 1 kHz
(1)
2.23.54.3A
(2)
2.73.85.0A
- 0.05 0.2 %
DR Dynamic range - - 100 - dB
Signal to noise ratio in
ternary mode
A-weighted - 100 -
SNR
Signal to noise ratio in
binary mode
A-weighted - 90 -
DXX stereo mode, < 5 kHz,
PSRR Power supply rejection ratio
V
RIPPLE
= 1 V RMS
-80-dB
audio input = dither only
DXX stereo mode, < 5 kHz,
X
TA L K
Crosstalk
One channel driven at 1 W
-80-dB
the other channel measured
η
1. The I
The current limit is active when OCRB = 0 (see Table 23: Overcurrent warning detect adjustment bypass
on page 28. When OCRB = 1 then I
2. The I
configuration. The short-circuit current is applicable when OCRB = 1 (see Table 23: Overcurrent warning
detect adjustment bypass on page 28.
Peak efficiency
in DXX mode
data is for 1 channel of BTL configuration, thus, 2 * I
LIM
current limit data is for 1 channel of BTL configuration, thus, 2 * I
SCP
Po = 2 x 20 W into 8 Ω -90-%
drives the 2-channel BTL configuration.
LIM
applies.
SC
drives the 2-channel BTL
SCP
dB
Doc ID 13365 Rev 2 13/49
Electrical specification STA333W
3.5 Power-on/off sequences
The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn
on and turn off.
Figure 3. Power-on sequence
No specific VCC and VDD_DIG turn-on sequence is required
VCC
VCC
VCC
Don’t care
Don’t care
VDD_Dig
VDD_Dig
VDD_DIG
XTI
XTI
XTI
Reset
Reset
RESET
PWRDN
PWRDN
PWRDN
Bit EAPD
Soft EAPD
Soft EAPD
Register 0x05
Reg. 0x05
Reg. 0x05
Bit 7 = 1
Bit 7 = 1
Don’t care
Don’t care
Don’t care
Don’t care
TR
TR
TC
TC
TR = mimimum time between XTI master clock stable and reset removal: 1 ms
TC = minimum time between reset removal and I
Clock stable means: fmax - fmin < 1 MHz
Figure 4. Power-off sequence
No specific VCC and VDD_DIG turn-off sequence is required
VCC
VCC
VCC
VDD_DIG
VDD_Dig
VDD_Dig
XTI
XTI
XTI
Mute
Soft Mute
Soft Mute
Register 0x07
Reg. 0x07
Reg. 0x07
Data 0xFE
Data 0xFE
Bit EAPD
Soft EAPD
Soft EAPD
Register 0x05
Reg. 0x05
Reg. 0x05
Bit 7 = 0
Bit 7 = 0
Don’t care
Don’t care
2
C program sequence start: 1 ms
FE
FE
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
14/49 Doc ID 13365 Rev 2
STA333W Electrical specification
3.6 Testing
Figure 5. Test circuit
OUTxY
Vcc
(3/4)Vcc
Low current dead time = MAX(DTr,DTf)
(1/2)Vcc
(1/4)Vcc
+Vcc
t
Duty cycle = 50%
INxY
M58
M57
gnd
OUTxY
R 8Ω
DTfDTr
+
V67 =
-
vdc = Vcc/2
D03AU1458
Figure 6. Current dead-time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))
+V
CC
Duty cycle=A Duty cycle=B
M58
DTin(A)
INA
M57
Q1
OUTA
Iout=4A
Lout = 1.5 A
Q3
DTout(A)
C69
470nF
Rload=8Ω
C71 470nF
M64
OUTB
Q2
M63
Q4
DTout(B) DTin(B)
L68 22µL67 22µ
Iout=4A
Lout = 1.5 A
C70
470nF
INB
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
Doc ID 13365 Rev 2 15/49
D03AU1517
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