ST STA333ML User Manual

2-channel microless high-efficiency digital audio system

Features

■ Wide supply voltage range (4.5 - 20 V)

■ 2 x 20 W into 8 Ω at V

■ PowerSSO-36 exposed pad package

■ 2 channels of 24-bit DDX

100-dB SNR and dynamic range

■

■ Selectable 32 kHz to 48 kHz input sample

rates

■ Automatic zero-detect mute

■ Automatic invalid input detect mute

■ 2-channel I

■ Selectable clock input ratio (256 or 364 * fs)

■ Max power correction for lower full power

■ 96 kHz internal processing sample rate, 24-bit

2

S input data interface

precision

■ Embedded thermal overload and short-circuit

protection

■ Filterless configuration option

Applications

■ LCDs

■ DVDs

■ Cradles

■ Digital speakers

■ Wireless speaker cradles

= 18 V

CC

®

STA333ML

Sound Terminal

Datasheet − production data

PowerSSO-36

with exposed pad down (EPD)

Description

The STA333ML is a single die embedding digital audio processing and high-efficiency power amplification, capable of operating without the aid of an external microcontroller.

The STA333ML is part of the Sound Terminal family that provides full digital audio streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment.

The STA333ML combines a unique 24-bit DDX digital class-D ternary modulator together with an extremely low R The latter is capable of a total output power of 2 x 20 W with outstanding performance in terms of efficiency (>90%), THD, SNR and EMI.

The microless feature allows its use in low-cost applications (cradles, digital speakers, audio terminals) where no microcontroller is needed.

The serial audio data interface accepts the universally used I as the oversampling clock, gain, and I can be set using a minimal number of selection pins.

The STA333ML is self-protected against thermal overload, overcurrent, short-circuit and overvoltage conditions.

stereo power DMOS stage.

dsON

2

S format. Basic features, such

2

S format,

®

The fault condition is also signalled on an external pin (INT_LINE) for specific requirements.

Table 1. Device summary

Order code Package Packaging

STA333ML PowerSSO-36 EPD Tube

STA333ML13TR PowerSSO-36 EPD Tape and reel

March 2012 Doc ID 13177 Rev 6 1/21

This is information on a product in full production.

www.st.com

21

Contents STA333ML

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.4 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.5 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.6 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Fault-detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.4 Fade-in/out feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.5 Oversampling selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.6 Gain selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.7 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2 Internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 PLL filter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.4 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/21 Doc ID 13177 Rev 6

STA333ML Block diagram

1 Block diagram

Figure 1. Block diagram

Protection

I2S

interface

Vol um e

control

Powe r control

DDX

current/thermal

Logic

Regulators

Channel

1A

Channel

1B

Channel

2A

PLL

Channel

2B

Bias

Doc ID 13177 Rev 6 3/21

Pin description STA333ML

2 Pin description

Figure 2. Pin connections (top view)

GND_SUB

FMT

TEST_MODE

VSS_REG

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD_REG

CONFIG

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

EP, exposed pad (device ground)

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

VDD_DIG

GND_DIG

GAIN

ONSEL

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

N.C.

Table 2. Pin description

Pin Name Type Description

1 GND_SUB Gnd Substrate ground

Serial format:

2FMT In

3 TEST_MODE In This pin must be connected to GROUND

4 VSS_REG Analog Internal reference at V

5 VCC_REG Analog Internal V

6 OUT2B Out Output half bridge 2B

7 GND2 Gnd Power negative supply

8 VCC2 Power Power positive supply

9 OUT2A Out Output half bridge 2A

10 OUT1B Out Output half bridge 1B

4/21 Doc ID 13177 Rev 6

0: I 1: left justified

2

S format

reference

CC

- 3.3 V

CC

STA333ML Pin description

Table 2. Pin description (continued)

Pin Name Type Description

11 VCC1 Power Power positive supply

12 GND1 Gnd Power negative supply

13 OUT1A Out Output half-bridge 1A

14 GND_REG Analog Internal ground reference

15 VDD_REG Analog Internal 3.3 V reference voltage

16 CONFIG In Configuration mode, must be connected to ground

17 N.C. - Not connected

18 N.C. - Not connected

19 N.C. - Not connected

20 N.C. - Not connected

21 VDD_DIG Power Positive supply digital

22 GND_DIG Gnd Digital ground

Power-down:

23 PWRDN In

24 VDD_PLL Power Positive supply for PLL

25 FILTER_PLL In Connection to PLL filter

0: low-power mode 1: normal operation

26 GND_PLL Gnd Negative supply for PLL

27 XTI In PLL input clock, 256 * fs or 384 * fs

2

28 BICKI In I

29 LRCKI In I

30 SDI In I

S serial clock

2

S left/right clock

2

S serial data channel

31 RESET In Reset

32 INT_LINE Out Fault interrupt

Oversampling selector:

33 ONSEL In

0: 256 * fs 1: 384 * fs

Gain selector:

34 GAIN In

0: 0 dBFs 1: 24 dBFs

35 GND_DIG Gnd Digital ground

36 VDD_DIG Power Digital supply

-EP -

Exposed pad for PCB heatsink, to be connected to ground plane

Doc ID 13177 Rev 6 5/21

Electrical specifications STA333ML

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

V

CC

V

L

V

DD

T

op

T

stg

Power supply voltage (pins VCC1, VCC2) - - 23 V

Logic input interface -0.3 - 4 V

Digital supply (pin VDD_DIG) - - 4 V

Operating junction temperature 0 - 150 °C

Storage temperature -40 - 150 °C

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Min Typ Max Unit

R

Th(j-case)

T

sd

T

hsd

Thermal resistance junction to case (thermal pad) - 1.5 2 °C/W

Thermal shutdown junction temperature 140 - 150 °C

Thermal shutdown hysteresis 18 20 22 °C

3.3 Recommended operating condition

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

V

T

CC

L

DD

amb

Power supply voltage (pins VCC1, VCC2) 4.5 - 20.0 V

Logic input interface 2.7 3.3 3.6 V

Digital supply (pin VDD_DIG) 2.7 3.3 3.6 V

Ambient temperature 0 - 70 °C

6/21 Doc ID 13177 Rev 6

STA333ML Electrical specifications

3.4 Electrical specifications - digital section

Table 6. Electrical specifications for digital section

Symbol Parameter Conditions Min Typ Max Unit

I

il

I

ih

V

il

V

ih

V

ol

V

oh

I

pu

R

pu

Input current without bias device

Low-level input voltage - - -

High-level input voltage -

Low-level output voltage Iol = 2 mA - -

High-level output voltage Ioh = 2 mA

Pull-up/down current - -25 66 125 µA

Equivalent pull-up/down resistance

= 0 V -10 - 10 µA

V

i

Vi = VDD = 3.6 V -10 - 10 µA

0.8 * V

--50-kΩ

3.5 Electrical specifications - power section

The specifications given here are with the operating conditions: VCC = 18 V, VDD = 3.3 V, f

= 384 kHz, T

sw

Table 7. Electrical specifications for power section

Symbol Parameter Conditions Min Typ Max Unit

= 25 °C, RL =8Ω unless otherwise specified

amb

DD

0.2 * V

DD

V

--V

0.4 * V

DD

V

--V

Po Output power BTL

On resistance of power

R

dsON

P-channel/N-channel MOSFET (total bridge)

Power

l

dss

P-channel/N-channel leakage current

gP

gN

I

LDT

I

HDT

t

r

t

f

Power P-channel R

matching

dsON

Power N-channel

matching

R

dsON

Low current dead time (static)

High current dead time (dynamic)

Rise time Resistive load Figure 4 - 8 10 ns

Fall time Resistive load Figure 4 - 8 10 ns

THD = 1% - 16 -

W

THD = 10% - 20 -

l

= 1 A - 180 250 mΩ

d

- --10μA

= 1 A 95--%

l

d

= 1 A 95--%

l

d

Resistive load Figure 4 - 5 10 ns

Load = 1.5 A (Figure 5) - 10 20 ns

Doc ID 13177 Rev 6 7/21

Electrical specifications STA333ML

Table 7. Electrical specifications for power section (continued)

Symbol Parameter Conditions Min Typ Max Unit

Supply current from

in power down

V

CC

PWRDN = 0 0.03 0.06 0.2 mA

PCM Input signal =

I

vcc

Supply current from

in operation

V

CC

-60 dBFs. Switching frequency =

384 kHz

- 3050mA

No LC filters

I

vdd_dig

I

SCP

UVL

t

min

Supply current DDX processing (reference only)

Supply current in standby

short-circuit protection Hi-Z output 2.7 3.8 5.0 A

Undervoltage protection threshold

Output minimum pulse width

Internal clock =

49.152 MHz

10 30 50 mA

- 8 11 25 mA

--3.54.3V

No load 20 30 60 ns

DR Dynamic range - - 100 - dB

SNR Signal-to-noise ratio A-weighted - 100 - dB

THD+N

PSRR

Total harmonic distortion + noise

Power supply rejection ratio

Po = 1 W, f = 1 kHz - 0.05 0.2 %

DDX stereo, <5 kHz Vripple = 1 V RMS

-80-dB

Audio input = dither only

DDX stereo, <5 kHz

X

TA L K

Crosstalk

One chan. driven at 1 W

-80-dB

other channel measured

η

f

sw

Peak efficiency, DDX mode

PWM carrier frequency switching

Po = 2 x 20 W into

8 Ω -90-%

- - 384 - kHz

8/21 Doc ID 13177 Rev 6

STA333ML Electrical specifications

3.6 Power-on sequence

Figure 3. Power-on sequence

VCC

Don’t care

VDD_Dig

XTI

Reset

PWDN

TR = minimum time between XTI master clock stable and reset removal: 1 ms

Note 1: clock stable means: f Note 2: No specific V

Don’t care

TR

- f

max

and VDD turn-on sequence is required.

CC

< 1 MHz

min

3.7 Test circuits

Figure 4. Resistive load

Figure 5. Test circuit

Duty cycle=A

DTin(A)

INA

OUTxY

Low current dead time = MAX(DTr,DTf)

+Vcc

R 8Ω

Lout = 1.5 A

DTfDTr

+

-

OUTB

Iout=4AIout=4A

Duty cycle = 50%

INxY

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

M58

Q1

M57

Q3

DTout(A)

OUTA

Lout = 1.5 A

M58

M57

gnd

C69

470nF

OUTxY

+V

Rload=8Ω

C71 470nF

CC

L68 22µL67 22µ

C70

470nF

t

V67 =

vdc = Vcc/2

D03AU1458

Q2

Q4

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

Duty cycle=B

M64

)B(niTD)B(tuoTD

INB

M63

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

Doc ID 13177 Rev 6 9/21

D03AU1517

Functional description STA333ML

4 Functional description

4.1 Serial audio interface protocols

The STA333ML serial audio input interfaces with standard digital audio components and accepts serial data formats. The STA333ML always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30).

The available formats are given in Figure 6 and Figure 7. Pin FMT (pin 2) selects the format such that FMT = logical 0 gives the I

Figure 6. I

Lrclki

Bicki

Sdi

2

S

21

3

1

2

3

2

S format and FMT = logical 1 gives the left-justified.

n

-1

21

3

n

-1

Figure 7. Left-justified

Lrclki/ Lrclko

Biclki/ Biclko

Sdatai/ Sdatao

1

2

3

n

-1

1

10/21 Doc ID 13177 Rev 6

n

2

3

n

-1

STA333ML Functional description

4.2 Fault-detect recovery bypass

The on-chip power output block provides feedback to the digital controller using inputs to the power control block. The fault input is used to indicate a fault condition (either overcurrent or thermal). When fault is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists.

4.3 Zero-detect mute enable

If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so, the channel is muted.

4.4 Fade-in/out feature

The STA333ML has internal fade-in / fade-out feature when powered on or off, or after a fault condition.

4.5 Oversampling selector

Pin ONSEL (33) is used to configure the PLL to accept 256 * fs or 384 * fs master clock. Where fs is the I

ONSEL = logical 0 gives

ONSEL = logical 1 gives 384 * fs.

2

S LRCKI frequency:

256 * fs

4.6 Gain selector

Pin GAIN (34) is used to configure the STA333ML gain:

GAIN = logical 0 gives 0 dBFs

GAIN = logical 1 gives

24 dBFs.

4.7 Power-down function

Pin PWDN (23) is used to power down the STA333ML:

PWDN = logical 0 sets the power-down mode

PWDN = logical 1 gives normal operation.

If the power stage is switched off, then the PLL is also switched off.

It is possible to use the PWDN function as a mute function.

Doc ID 13177 Rev 6 11/21

Applications STA333ML

5 Applications

5.1 Applications schematic

Figure 8 on page 13 shows the schematic of a typical application for the STA333ML.

Concerning the power supplies, take care when designing the PCB layout. In particular, the

3.3-Ω resistors on the digital supplies (VDD_DIG) must be placed as close as possible to the device. This helps to prevent parasitic oscillation in the digital part of the device due to the inductive tracks of the PCB. The same rule applies for all the decoupling capacitors in order to limit any spikes on the supply pins.

12/21 Doc ID 13177 Rev 6

Figure 8. Application schematic

STA333ML Applications

Doc ID 13177 Rev 6 13/21

+3.3V

5

C6 100n

+3.3V

C4

100n

PWDN



100n

5

R4

2.2K C9

C7



680p

C8

4.7n

MCLK

BICLK

LRCLK

SDI

RESET

INT_LINE

OVERSAMPLING _S E L

GAIN_SEL

+3.3V

)250$7B6(/

C3

100n

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

N.C.

VDD_DIG

GND_DIG

PWDN

VDD_PLL

FILTER_PLL

GND_PLL

XTI

BICLK

LRCLK

SDI

RESET

INT_LINE

ONSEL

GAIN

GND_DIG

VDD_DIG

STA333ML

U1

N.C.

CONFIG

VDD

GND_REG

OUT1A

GND1

VCC1

OUT1B

OUT2A

VCC2

GND2

OUT2B

VCC_REG

VSS

TEST_MODE

FMT

GND_SUB

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

100n

VCC

C11

C2 100n

C1

100n

1u

C13

50V

C12

100n

C14

1u

50V

47u

C10

25V

+

L1

22uH

C15 330p

R5

22

L2

22uH

L4

22uH

R8

22

C21 330p

L3

22uH

C16 100n

C18 100n

C22 100n

C24 100n

6.2

R6

C17

100n

6.2

R7

C19

100n

6.2

R9

C23

100n

6.2

R10

C25

100n

C20 470n

C26 470n

C27 10n

C28 10n

C30 10n

C31 10n

J1-3

C29 10n

J1-4

J1-1

C32 10n

J1-2

Applications STA333ML

5.2 Internal voltage reference

An embedded voltage regulator produces the reference voltages for the DMOS bridge driver. It requires two 100 nF capacitors to keep the regulator stable. The capacitors should be place close to the pins.

Figure 9. Reference voltage block diagram

VCC

VCC_REG

100 nF

VSS_REG

VDD_REG

100 nF

GND_REG

Regulator

Driver P

Input level shifter

5.3 PLL filter schematic

It is recommended to use the below scheme and values for the PLL loop filter to achieve the best performances from the device in general application. Please note that the ground of this filter scheme has to be connected to the ground of the PLL without any resistive path. Concerning the component values, please take into account that the greater the filter bandwidth, the less the lock time, but the higher the PLL output jitter.

Figure 10. PLL application schematic

PLL_FILTER

2

S

I interface

Driver N

GND

2.2K

680p

14/21 Doc ID 13177 Rev 6

4.7n

0

STA333ML Applications

5.4 Typical output configuration

Figure 11 and Figure 12 show the typical output circuits used for the BTL stereo mode.

Figure 11. Output configuration for stereo BTL mode

22 µH

OUT1A

100 nF

OUT1B

OUT2A

OUT2B

22R

330 pF

22 µH

22R

330 pF

22 µH

6R2

100 nF

6R2

100 nF

470 nF

Left

100 nF

470 nF

Right

100 nF

Doc ID 13177 Rev 6 15/21

Applications STA333ML

Figure 12. Filterless output configuration

OUT1A

22R

Left

330 pF

OUT1B

OUT2A

22R

Right

330 pF

OUT2B

The filterless application is more critical in terms of EMI. It is quite important to follow the below suggestions:

● Tracks from amplifier to speaker should be as short as possible.

● Ferrite beads can be used (instead of coils) to improve EMI performance.

– Ferrite beads must have a low impedance in the audio band and high impedance

at high frequencies.

– Place ferrite beads as close as possible to the IC.

– Ferrite filters must reduce EMI above 1 MHz.

– FCC and CE authorities test radiated emission above 30 MHz.

The presence of snubber networks reduce the EMI. The snubber networks should be placed as close as possible to the IC.

16/21 Doc ID 13177 Rev 6

STA333ML Package thermal characteristics

6 Package thermal characteristics

Using a double layer PCB the thermal resistance junction to ambient with 2 copper ground areas of 3 x 3 cm

The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level.

The max estimated dissipated power for the is:

2 x 20 W into 8 Ω, at 18 V Pd max is approximately 4 W

Figure 13. Double layer PCB with 2 copper ground areas and 16 via holes

Figure 14 shows the power derating curve for the PowerSSO-36 package on a board with

two copper areas of 2 x 2 cm

Figure 14. PowerSSO-36 power derating curve

Pd (W)

2

and with 16 via holes (see Figure 13) is 24 °C/W in natural air convection.

2

and 3 x 3 cm2.

8

7

Copper Area 3x3 cm

6

5

4

3

Copper Area 2x2 cm

2

1

0

Copper Area 2x2 cm and via holes

and via holes

0 20 40 60 80 100 120 140 160

0

0 20 40 60 80 100 120 140 160

0

0 20 40 60 80 100 120 140 160

0

0 20 40 60 80 100 120 140 160

0

0 20 40 60 80 100 120 140 160

20 40 60 80 100 120 140 160

Copper Area 3x3 cm and via holes

and via holes

Tamb ( °C)

STA333ML

STA333BW

STA333ML

STA333BW

STA333ML

PowerSSO-36

PSSO36

Doc ID 13177 Rev 6 17/21

Package mechanical data STA333ML

7 Package mechanical data

Figure 15 shows the package outline and Ta bl e 8 gives the dimensions.

Figure 15. PowerSSO-36 EPD outline drawing

h x 45°

18/21 Doc ID 13177 Rev 6

STA333ML Package mechanical data

Table 8. PowerSSO-36 EPD dimensions

Dimensions in mm Dimensions in inches

Symbol

Min Typ Max Min Typ Max

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0.00 - 0.10 0.00 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G- - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h- - 0.40 - - 0.016

k 0 - 8 degrees 0 - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 4.90 - 7.10 0.193 - 0.280

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK®

®

is an ST trademark.

Doc ID 13177 Rev 6 19/21

Revision history STA333ML

8 Revision history

Table 9. Document revision history

Date Revision Changes

1-Feb-2007 1 Initial release

2-May-2008 2 Package information update

Added Table 6: Electrical specifications for digital section on page 7 Updated Table 7: Electrical specifications for power section on

page 7

4-Nov-2008 3

28-Jan-2010 4

Added Section 3.6: Power-on sequence on page 9 Updated Chapter 4: Functional description on page 10 Added Chapter 5: Applications on page 12 Updated Chapter 6: Package thermal characteristics on page 17.

Updated supply voltage range in Features on page 1 Added package exposed pad to Figure 2 and Table 2: Pin description

on page 4

Updated supply voltage range in Table 5: Recommended operating

condition on page 6

Updated exposed pad Y dimension in Table 8: PowerSSO-36 EPD

dimensions on page 19.

3-Feb-2010 5

05-Mar-2012 6

Updated junction temperature range in Table 3: Absolute maximum

ratings on page 6

Removed max estimated dissipated power example on page 17

Updated Figure 8: Application schematic on page 13 Updated Figure 10: PLL application schematic on page 14 Removed reference to application note in Section 5.4: Typical output

configuration

Minor textual updates

20/21 Doc ID 13177 Rev 6

STA333ML

Please Read Carefully:

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Doc ID 13177 Rev 6 21/21

ST STA333ML User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table 1. Device summary

1 Block diagram

Figure 1. Block diagram

2 Pin description

Figure 2. Pin connections (top view)

Table 2. Pin description

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

3.2 Thermal data

Table 4. Thermal data

3.3 Recommended operating condition

Table 5. Recommended operating condition

3.4 Electrical specifications - digital section

Table 6. Electrical specifications for digital section

3.5 Electrical specifications - power section

Table 7. Electrical specifications for power section

3.6 Power-on sequence

Figure 3. Power-on sequence

3.7 Test circuits

Figure 4. Resistive load

Figure 5. Test circuit

4 Functional description

4.1 Serial audio interface protocols

Figure 7. Left-justified

4.2 Fault-detect recovery bypass

4.3 Zero-detect mute enable

4.4 Fade-in/out feature

4.5 Oversampling selector

4.6 Gain selector

4.7 Power-down function

5 Applications

5.1 Applications schematic

Figure 8. Application schematic

5.2 Internal voltage reference

Figure 9. Reference voltage block diagram

5.3 PLL filter schematic

Figure 10. PLL application schematic

5.4 Typical output configuration

Figure 11. Output configuration for stereo BTL mode

Figure 12. Filterless output configuration

6 Package thermal characteristics

Figure 13. Double layer PCB with 2 copper ground areas and 16 via holes

Figure 14. PowerSSO-36 power derating curve

7 Package mechanical data

Figure 15. PowerSSO-36 EPD outline drawing

Table 8. PowerSSO-36 EPD dimensions

8 Revision history

Table 9. Document revision history