ST STA333BW User Manual

2.1-channel 40-watt high-efficiency digital audio system

Features

 Wide-range supply voltage, 4.5 V to 21.5 V

 Three power output configurations:

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + PWM output

– 2 channels of ternary PWM

(2 x 20 W into 8 Ω at 18 V) + ternary stereo line-out

– 2.1 channels of binary PWM (left, right,

LFE) (2 x 9 W into 4 Ω +1 x 20 W into 8 Ω at 18 V)

 FFX with 100-dB SNR and dynamic range

 Scalable FFX modulation index

 Selectable 32- to 192-kHz input sample rates

 I

C control with selectable device address

 Digital gain/attenuation +48 dB to -80 dB with

0.5-dB/step resolution

 Soft volume update with programmable ratio

 Individual channel and master gain/attenuation

 Dynamic range compression (DRC) or

anticlipping mode

 Audio presets:

– 15 preset crossover filters – 5 preset anticlipping modes – Preset night-time listening mode

 Individual channel soft/hard mute

 Independent channel volume and DSP bypass

 I

S input data interface

Table 1. Device summary

STA333BW

Sound Terminal®

PowerSSO-36 with exposed pad down (EPD)

 Input and output channel mapping

 Automatic invalid input-detect mute

 Up to 5 user-programmable biquads/channel

 Three coefficients banks for EQ presets storing

with fast recall via I

 Bass/treble tones and de-emphasis control

 Selectable high-pass filter for DC blocking

 Advanced AM interference frequency

switching and noise suppression modes

 Sub channel mix into left and right channels

 Selectable high- or low-bandwidth

noise-shaping topologies

 Selectable clock input ratio

 96-kHz internal processing sample rate

 Thermal overload and short-circuit protection

technology

 Video apps: 576 x f

 Pin and SW compatible with STA335BW,

STA339BW, STA339BWS, STA559BW and STA559BWS

C interface

input mode supported

Order code Package Packaging

STA333BW PowerSSO-36 EPD Tube

STA333BW13TR PowerSSO-36 EPD Tape and reel

January 2011 Doc ID 13773 Rev 3 1/67

www.st.com

Contents STA333BW

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 12

3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 13

3.6 Power-on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/67 Doc ID 13773 Rev 3

STA333BW Contents

6.1 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 40

6.2.1 Mute / line output configuration register (addr 0x06) . . . . . . . . . . . . . . . 41

6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . . 42

6.3 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 43

6.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6.4 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 45

6.5 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.6 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 47

6.6.1 Limiter 1 attack / release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . 47

6.6.2 Limiter 1 attack / release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 47

6.6.3 Limiter 2 attack / release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . 48

6.6.4 Limiter 2 attack / release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 48

6.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.7 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 53

6.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 53

6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 53

6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 53

6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 53

6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 54

6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 54

6.7.7 Coefficient read / write control register (addr 0x26) . . . . . . . . . . . . . . . . 54

6.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.8 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 59

6.9 Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 59

6.10 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 59

Doc ID 13773 Rev 3 3/67

Contents STA333BW

6.11 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1 Applications schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.2 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4/67 Doc ID 13773 Rev 3

STA333BW List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 4. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 5. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Left and right processing, section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Left and right processing, section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 12. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 15. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 19. Output configuration for stereo BTL mode (R

Figure 20. Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 21. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 22. PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

= 8 Ω) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Doc ID 13773 Rev 3 5/67

List of tables STA333BW

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. Support serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26

Table 20. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 22. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 23. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 24. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 25. Overcurrent warning bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 26. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 27. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 28. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 29. Postscale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 30. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 31. Dynamic range compression / anticlipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 32. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 33. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 34. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 35. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 36. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 37. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 38. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 39. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 40. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 41. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 42. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 43. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 44. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 45. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 46. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 47. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 48. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6/67 Doc ID 13773 Rev 3

STA333BW List of tables

Table 49. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 50. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 51. Master volume offset as a function of MVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 52. Channel volume as a function of CxVOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 53. Audio preset gain compression / limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . 43

Table 54. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 55. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 56. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 57. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 58. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 59. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 60. Volume bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 61. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 62. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 63. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 64. Tone control boost / cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 65. Limiter attack rate vs LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 66. Limiter release rate vs LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 67. Limiter attack threshold vs LxAT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 68. Limiter release threshold vs LxRT bits (AC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 69. Limiter attack threshold vs LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 70. Limiter release threshold vs LxRT bits (DRC mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 71. RAM block for biquads, mixing, scaling, bass management. . . . . . . . . . . . . . . . . . . . . . . . 56

Table 72. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 73. PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 74. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Doc ID 13773 Rev 3 7/67

Description STA333BW

1 Description

The STA333BW is an integrated solution of digital audio processing, digital amplifier controls and power output stages to create a high-power single-chip FFX digital amplifier with high-quality and high-efficiency. Three channels of FFX processing are provided. The FFX processor implements the ternary, binary and binary differential processing capabilities of the full FFX processor.

The STA333BW is part of the Sound Terminal streaming to the speakers and offers cost effectiveness, low power dissipation and sound enrichment.

The power section consists of four independent half-bridges. These can be configured via digital control to operate in different modes.

For example, 2.1 channels can be provided by two half-bridges and a single full-bridge, supplying up to 2 x 9 W + 1 x 20 W of output power or two channels can be provided by two full-bridges, supplying up to 2 x 20 W of output power.

The IC can also be configured as 2.1 channels with 2 x 20 W supplied by the device plus a drive for an external FFX power amplifier, such as STA533WF or STA515W.

The serial audio data input interface accepts all possible formats, including the popular I format. The high-quality conversion from PCM audio to FFX PWM switching provides over 100 dB of SNR and of dynamic range.

family that provides full digital audio

Also provided in the STA333BW are a full assortment of digital processing features. This includes up to 5 programmable biquads (EQ) per channel. Available presets enable a time-to-market advantage by substantially reducing the amount of software development needed for functions such as audio preset volume loudness, preset volume curves and preset EQ settings. There are also new advanced AM radio interference reduction modes. The DRC dynamically equalizes the system to provide a linear frequency speaker response regardless of output power level.

Figure 1. Block diagram

I2S

interface

Vol um e

control

PLL

FFX

I2C

Powe r control

Protection

current / thermal

Logic

Regulators

Bias

Channel

PowerDigital DSP

8/67 Doc ID 13773 Rev 3

STA333BW Pin connections

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

EP, exposed pad (device ground)

D05AU1638

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

2.2 Pin description

Table 2. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at V

5 I/O VCC_REG Internal V

6 O OUT2B Output half-bridge channel 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half-bridge channel 2A

10 O OUT1B Output half-bridge channel 1B

C select address (pull-down)

- 3.3 V

reference

Doc ID 13773 Rev 3 9/67

Pin connections STA333BW

Table 2. Pin description (continued)

Pin Type Name Description

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half-bridge channel 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Parallel mode command

17 O OUT3B / FFX3B PWM out channel 3B / external bridge driver

18 O OUT3A / FFX3A PWM out channel 3A / external bridge driver

19 O EAPD / OUT4B Power down for external bridge / PWM out channel 4B

20 I/O TWARN / OUT4A

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

Thermal warning from external bridge (pull-up when input) / PWM out channel 4A

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

28 I BICKI I

29 I LRCKI I

30 I SDI I

S serial clock

S left / right clock

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

33 I/O SDA I

34 I SCL I

C serial data

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

- - EP Exposed pad for PCB heatsink, to be connected to GND

10/67 Doc ID 13773 Rev 3

STA333BW Electrical specifications

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

Operating junction temperature -20 - 150 °C

Storage temperature -40 - 150 °C

stg

Power supply voltage (pins VCCx) -0.3 - 24 V

Digital supply voltage (pins VDD_DIG) -0.3 - 4.0 V

PLL supply voltage (pin VDD_PLL) -0.3 - 4.0 V

Warning: Stresses beyond those listed in Tab l e 3 above may cause

permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended operating conditions” are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, power supplies with nominal values rated within the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded.

3.2 Thermal data

Table 4. Thermal data

th j-case

th-sdj

th-w

th-sdh

th j-amb

1. See Chapter 8: Package thermal characteristics on page 63 for details.

Thermal resistance junction-case (thermal pad) - - 1.5 °C/W

Thermal shut-down junction temperature - 150 - °C

Thermal warning temperature - 130 - °C

Thermal shut-down hysteresis - 20 - °C

Thermal resistance junction-ambient

Parameter Min Typ Max Unit

(1)

-24-°C/W

Doc ID 13773 Rev 3 11/67

Electrical specifications STA333BW

3.3 Recommended operating conditions

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

DD_DIG

DD_PLL

amb

Power supply voltage (VCCxA, VCCxB) 4.5 - 21.5 V

Digital supply voltage 2.7 3.3 3.6 V

PLL supply voltage 2.7 3.3 3.6 V

Ambient temperature -20 - 70 °C

3.4 Electrical specifications for the digital section

The specifications given in this section are valid for T

Table 6. Electrical specifications - digital section

Symbol Parameter Conditions Min Typ Max Unit

Low level input current without pull-up/down device

High level input current without pull-up/down device

Vi = 0 V --1 µA

Vi = VDD_DIG = 3.6 V

Low level input voltage - - -

High level input voltage -

Low level output voltage Iol = 2 mA -

High level output voltage Ioh = 2 mA

= 25 °C unless otherwise specified.

amb

--1µA

0.8 *

VDD_DIG

0.8 *

VDD_DIG

--V

0.2 *

VDD_DIG

0.4 *

VDD_DIG

Equivalent pull-up/down resistance

--50-kΩ

12/67 Doc ID 13773 Rev 3

STA333BW Electrical specifications

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC=18V, f=1kHz, f

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

= 384 kHz, T

= 25 °C and RL = 8 Ω, unless otherwise specified.

amb

Output power BTL

THD = 10% - 20 -

THD = 1% - 16 -

Output power SE

dsON

gP Power P-channel R

gN Power N-channel R

Power P-channel or N-channel MOSFET ld = 0.75 A - - 250 mΩ

matching ld = 0.75 A - 100 - %

dsON

matching ld = 0.75 A - 100 - %

dsON

Idss Power P-channel / N-channel leakage V

Rise time

Fall time - - 10 ns

THD = 1%, R

THD = 10%, R

= 20 V - - 1 µA

Resistive load, see Figure 3 below

= 4 Ω -7-

= 4 Ω -9-

- - 10 ns

Supply current from VCC in power down PWRDN = 0 - 0.3 - µA

VCC

VDD

LIM

SCP

min

UVP

Supply current from V

Supply current FFX processing

Overcurrent limit

in operation PWRDN = 1 - 15 - mA

Internal clock =

49.152 MHz

(1)

-55-mA

2.2 3.0 - A

Short -circuit protection RL = 0 Ω 2.7 3.6 - A

Undervoltage protection - - - 4.3 V

Output minimum pulse width No load 20 40 60 ns

DR Dynamic range - - 100 - dB

Signal to noise ratio, ternary mode A-Weighted - 100 - dB

SNR

Signal to noise ratio binary mode - - 90 - dB

FFX stereo mode,

THD+N Total harmonic distortion + noise

Po = 1 W

-0.2-%

f=1kHz

FFX stereo mode, <5 kHz

TA LK

Crosstalk

One channel driven

-80-dB

at 1 W, other channel measured

Peak efficiency, FFX mode

Peak efficiency, binary modes

Po = 2 x 2 0 W into 8 Ω

Po = 2 x 9 W into 4 Ω + 1 x 20 W into 8 Ω

-90-

-87-

1. Limit the current if overcurrent warning detect adjustment bypass is enabled (register bit CONFC.OCRB on

page 28). When disabled refer to the I

SCP

Doc ID 13773 Rev 3 13/67

Electrical specifications STA333BW

Figure 3. Test circuit

OUTxY

VCC

(0.9)*VCC

½VCC

(0.1)*VCC

tr tf

R 8

Ω

V67

vdc = Vcc/2

Duty cycle = 50%

INxY

+Vcc

M58

OUTxY

M57

gnd

14/67 Doc ID 13773 Rev 3

STA333BW Electrical specifications

3.6 Power-on/off sequence

Figure 4. Power-on sequence

VCC

VDD_Dig

XTI

Reset

PWDN

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

on sequence

Don’t care

CMD0 CMD1 CMD2

TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I

Note: The definition of a stable clock is when f

Section Serial audio input interface format on page 25 gives information on setting up the

S interface.

Figure 5. Power-off sequence for pop-free turn-off

VCC

VDD_Dig

XTI

Soft Mute

Reg. 0x07

Reg. 0x07 Data 0xFE

Data 0xFE

Soft EAPD

Reg. 0x05

Reg. 0x05 Bit 7 = 0

Bit 7 = 0

Don’t care

C program, sequence start: 1ms

- f

max

< 1 MHz.

min

Note: no specific VCC and VDD_DIG turn is required

Don’t care

−

off sequence

Don’t care

Doc ID 13773 Rev 3 15/67

Processing data paths STA333BW

4 Processing data paths

Figure 6 and Figure 7 below show the data processing paths inside STA333BW. The whole

processing chain is composed of two consecutive sections. In the first one, dual-channel processing is implemented and in the second section each channel is fed into the post mixing block either to generate a third channel (typically used in 2.1 output configuration and with crossover filters enabled) or to have the channels processed by the DRC block (2.0 output configuration with crossover filters used to define the cut-off frequency of the two bands).

The first section, Figure 6, begins with a 2x oversampling FIR filter providing 2 * f

audio

processing. Then a selectable high-pass filter removes the DC level (enabled if HPB = 0). The left and right channel processing paths can include up to 8 filters, depending on the selected configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]). By default, four user programmable, independent filters per channel are enabled, plus the preconfigured de-emphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).

If the coefficient sets for the two channels are linked (BQL = 1) it is possible to use the de-emphasis, bass and treble filters in a user defined configuration (provided the relevant BQx bits are set). In this case both channels use the same processing coefficients and can have up to seven filters each. If BQL = 0 the BQx bits are ignored and the fifth, sixth and seventh filters are configured as de-emphasis, bass and treble controls, respectively.

Figure 6. Left and right processing, section 1

Sampling

Sampling frequency=Fs

frequency=Fs

From

From I2S input

I2S input

I2S input interface

interface

sampling

FIR

over

FIR

over

FIR

over

FIR

over

Sampling

Sampling frequency=2xFs

frequency=2xFs

PreScale

If HPB=0

PreScale

Hi-Pass

Filter

Hi-Pass

Filter

Biquad#1Biquad#2Biquad#3Biquad

User Defined Filters

If DSPB=0 and C1EQBP=0

Biquad#1Biquad#2Biquad#3Biquad

If BQ5=1

and BQL=1

Biquad

De-Emph.

If DEMP=0

If BQ5=1

and BQL=1

Biquad

De-Emph.

IF BQ7=1

If BQ6=1

and BQL=1

If C1TCB=0

If C1TCB=0 BTC: Bass Boost/Cut

BTC: Bass Boost/Cut TTC: Treble Boost/Cut

TTC: Treble Boost/Cut

and BQL=1

Biquad

Bass Treble

If BQ6=1

IF BQ7=1

and BQL=1

Biquad

Bass Treble

Biquad

If HPB=0

User Defined Filters

If DSPB=0 and C2EQBP=0

Moreover, the common 8th filter can be available on both channels provided the predefined crossover frequencies are not used, XO[3:0] = 0, and the DRC is not used.

In the second section, Figure 7, mixing and crossover filters are available. If DRC is not enabled they are fully user-programmable and allow the generation of a third channel (2.1 outputs). Alternatively, in mode DRC, these blocks are used to split the sub-band and define the cut-off frequencies of the two bands. A prescaler and a final postscaler allow full control over the signal dynamics before and after the filtering stages. A mixer function is also available.

16/67 Doc ID 13773 Rev 3

If DEMP=0

If C2TCB=0

If C2TCB=0 BTC: Bass Boost/Cut

BTC: Bass Boost/Cut TTC: Treble Boost/Cut

TTC: Treble Boost/Cut

STA333BW Processing data paths

Figure 7. Left and right processing, section 2

C1Mx1

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

Hi-Pass XO

Filter

Hi-Pass XO

Filter

Lo-Pass XO

Filter

Vol

Vol And

And

Limiter

Vol

Vol And

And

Limiter

Vol

Vol And

And

Limiter

Post scale

User-Defined Mix Coefficients

Crossover Frequency d etermined by XO Setting

Crossover Frequency d etermined by XO Setting User Defined If XO=0000

User Defined If XO=0000

Doc ID 13773 Rev 3 17/67

I2C bus specification STA333BW

5 I2C bus specification

The STA333BW supports the I2C protocol via the input ports SCL and SDA_IN (master to slave) and the output port SDA_OUT (slave to master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333BW is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate).

For correct operation of the I has a frequency at least 10 times higher than the frequency of the applied SCL clock.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition while the clock is high is used to identify a START or STOP condition.

C interface ensure that the master clock generated by the PLL

5.1.2 Start condition

START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is stable in the high state. A START condition must precede any command for data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of SDA while SCL is stable in the high state. A STOP condition terminates communication between STA333BW and the bus master.

5.1.4 Data input

During the data input the STA333BW samples the SDA signal on the rising edge of SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the STA333BW, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode bit.

The seven most significant bits are the device address identifiers, corresponding to the I bus definition. In the STA333BW the I the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

C interface has two device addresses depending on

The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to 0 for write. After a START condition the STA333BW identifies the device address on the SDA bus and if a match is found, acknowledges the identification during the 9th bit time frame. The byte following the device identification is the address of a device register.

18/67 Doc ID 13773 Rev 3

STA333BW I2C bus specification

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA333BW again responds with an acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the STA333BW. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer.

Figure 8. Write mode sequence

BYTE

WRITE

MULTIBYTE

WRITE

DEV-ADDR

START RW

DEV-ADDR

START RW

ACK

SUB-ADDR

ACK

DATA IN

ACK

STOP

DATA IN

ACK

STOP

5.4 Read operation

5.4.1 Current address byte read

Following the START condition the master sends a device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

5.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

5.4.3 Random address byte read

Following the START condition the master sends a device select code with the RW bit set to 0. The STA333BW acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333BW again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333BW acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.

Doc ID 13773 Rev 3 19/67

I2C bus specification STA333BW

5.4.4 Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333BW. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.

Figure 9. Read mode sequence

CURRENT ADDRESS

READ

RANDOM

ADDRESS

READ

SEQUENTIAL

CURRENT

READ

SEQUENTIAL

RANDOM

READ

DEV-ADDR

START RW

DEV-ADDR

START RW

DEV-ADDR

START

DEV-ADDR

START RW

RW=

HIGH

ACK

DATA

SUB-ADDR

DATA

SUB-ADDR

NO ACK

STOP

ACK

DEV-ADDR

START RW

ACK

DATA

ACK

DEV-ADDR

START RW

ACK

DATA

NO ACK

ACK

STOP

ACK NO ACK

DATA

STOP

20/67 Doc ID 13773 Rev 3

STA333BW Register description

6 Register description

Note: Addresses exceeding the maximum address number must not be written.

Table 8. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CONFA

0x01 CONFB

0x02 CONFC

0x03 CONFD

0x04 CONFE

0x05 CONFF

0x06 MUTELOC

0x07 MVOL

0x08 C1VOL

0x09 C2VOL

0x0A C3VOL

0x0B AUTO1

0x0C AUTO2

0x0D AUTO3

0x0E C1CFG

0x0F C2CFG

0x10 C3CFG

0x11 TONE

0x12 L1AR

0x13 L1ATRT

0x14 L2AR

0x15 L2ATRT

0x16 CFADDR

0x17 B1CF1

0x18 B1CF2

0x19 B1CF3

0x1A B2CF1

0x1B B2CF2

0x1C B2CF3

0x1D A1CF1

0x1E A1CF2

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

SME ZDE DRC BQL PSL DSPB DEMP HPB

SVE ZCE DCCV PWMS AME NSBW MPC MPCV

EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

LOC1 LOC0 Reserved Reserved C3M C2M C1M Reserved

MVOL[7:0]

C1VOL[7:0]

C2VOL[7:0]

C3VOL[7:0]

Reserved Reserved AMGC[1:0] Reserved Reserved Reserved Reserved

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

Reserved

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved Reserved

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

Reserved Reserved CFA[5:0]

C1B[23:16]

C1B[15:8]

C1B[7:0]

C2B[23:16]

C2B[15:8]

C2B[7:0]

C3B[23:16]

C3B[15:8]

Doc ID 13773 Rev 3 21/67

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