ST STA321MP User Manual

Scalable digital microphone processor

Features

■ 8 digital processing channels each 24-bit

– 6 channels of PDM input
– 2 additional virtual channels

■ >100 dB SNR and dynamic range

■ Digital gain/attenuation +58 dB to -100 dB in

0.5 dB steps

■ Soft volume update

■ Individual channel and master level control

■ Up to 10 independent 32-bit user-

programmable biquads (EQ) per channel

■ Bass/treble tone control

■ Pre- and post-EQ full 8-channel input mix on all

8 channels

■ Dual independent limiters/compressors

■ Dynamic range compression or anti-clipping

modes

■ Individual channel and master soft/hard mute

2

■ 3 I

S data outputs

2

■ I

S data output channel mapping function

■ Independent channel volume and DSP bypass

■ Channel mapping of any input to any

processing channel

Applications

■ Tablets

■ Smartphones

■ Gaming

■ Audio conference sets

■ Legacy microphone-equipped devices

STA321MP

TQFP - 64

10 mm x 10 mm

Description

The STA321MP is a PDM high-performance
multichannel processor with ultra-low quiescent
current designed for general-purpose digital
microphone applications. The device is fully digital
and is comprised of three main sections. The first
section is the PDM input interface which can
accept up to six serial digital inputs. The second
section is a high-quality audio processor allowing
flexible channel mixing/muxing and provides up to
10 biquads for general sound equalization and
voice enhancement with independent volume
control. The last block is the I
which streams out the processed digital audio.
The output interface can also be programmed for
flexible channel mapping. The device offers some
of the most commonly required audio
enhancements such as programmable voice
tuning and equalization, limiter/compressor for
improved voice quality, multiband selection for
customizable microphone usage and configurable
wind-noise rejection. The embedded digital
processor allows offloading the microphone
processing from the main CPU or SoC, moving it
to the device.

Table 1. Device summary

VFQFPN - 56
8 mm x 8 mm

2

S output interface

Order code Package Packing

STA321MPL TQFP64 Tube

STA321MP VFQFPN56 Tube

February 2012 Doc ID 022647 Rev 1 1/50

www.st.com

1

Contents STA321MP

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5I

2

C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2.2 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 23

7.2.3 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2.4 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2.5 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2.6 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2/50 Doc ID 022647 Rev 1

STA321MP Contents

7.2.7 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.2.8 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.9 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.10 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.11 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.12 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.13 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.2.14 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.15 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.16 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.17 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.2.18 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 30

7.2.19 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 30

7.2.20 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 30

7.2.21 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 31

7.2.22 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 31

7.2.23 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 31

7.2.24 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 31

7.2.25 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 31

7.2.26 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 33

7.2.27 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 33

7.2.28 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 33

7.2.29 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 33

7.2.30 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 34

7.2.31 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 35

7.2.32 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2.33 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7.2.34 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.35 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.36 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.37 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2.38 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2.39 Channel I

7.2.40 Channel I

7.2.41 Channel I

7.2.42 Channel I

2

S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 37

2

S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 37

2

S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 37

2

S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 38

7.2.43 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Doc ID 022647 Rev 1 3/50

Contents STA321MP

7.2.44 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2.45 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 38

7.2.46 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 39

7.2.47 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 39

7.2.48 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 39

7.2.49 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 39

7.2.50 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 39

7.2.51 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 39

7.2.52 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 39

7.2.53 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 40

7.2.54 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 40

7.2.55 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 40

7.2.56 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 40

7.2.57 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 40

7.2.58 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 40

7.2.59 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 40

7.2.60 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.1 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.4 Reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.1 TQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

9.2 VFQFPN56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4/50 Doc ID 022647 Rev 1

STA321MP List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description: TQFP-64 (STA321MPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Pin description: VFQFPN-56 (STA321MP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 7. General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 8. DC electrical characteristics: 3.3-V buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 9. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 11. VFQFPN56 (8 x 8 x 0.9 mm) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 12. Exposed pad variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Doc ID 022647 Rev 1 5/50

List of figures STA321MP

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 6. Reference schematic for STA321MP-based application . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 9. TQFP64 (10 x 10 x 1.4 mm) mechanical data and package dimensions . . . . . . . . . . . . . . 46

Figure 10. VFQFPN56 (8 x 8 x 0.9 mm) package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . 47

6/50 Doc ID 022647 Rev 1

STA321MP Block diagram

1 Block diagram

Figure 1. Block diagram

FFX

Figure 2. Channel signal flow

AM045327v1

AM045328v1

Doc ID 022647 Rev 1 7/50

Pin connections STA321MP

2 Pin connections

Figure 3. Pin connections (top view)

PDM_CLK

GND

VDD3

GND

PDMIN_6

PDMIN_5

PDMIN_4

PDMIN_3

PDMIN_2

PDMIN_1

VDD3

GND

RESET

PDM_CLK

GND

VDD3

GND

PDMIN_6

PDMIN_5

PDMIN_4

PDMIN_3

PDMIN_2

PDMIN_1

VDD3

GND

RESET

VDD3

52

29

OUT8B

EAPD

51

30

OUT8A

OUT1A

50

31

OUT7B

OUT1B

49

32

OUT7A

48

OUT2A

OUT2B

47

46

NC

45

GND

44

VDD3

OUT3A

43

OUT3B

42

41

OUT4A

OUT4B

40

39

OUT5A

38

OUT5B

37

NC

36

GND

35

VDD3

34

OUT6A

33

OUT6B

SDO_78

PWDN

SDO_56

64

62

63

1

2

3

4

5

NC

6

7

8

9

10

11

12

13

14

NC

15

16 PLLB

17

18

19

NC

SCL

SDA

VDD3

NC GND

61

SDO_34

59

58

60

TQFP-64

20

21

22

XTI

23

VDDA

GNDA

FILTER_PLL

SDO_12

57

24

VDD3

LRCKO

56

25

CKOUT

BIKO

55 54

26

NC

GND

NC

53

27

28

GND

VDD3

PWDN

SDO_78

56

55

VDD3

SDO_56

GND

52

53

54

LRCKO

SDO_34

51

BIKO GND

SDO_12

50

49

VDD3

48

47

46 45

1

2

3

4

5

6

7

8

VFQFPN-56

10

10

11

12

13

14 PLLB

15 16

SDA

18

19

17

XTI

SCL

20 21

VDDA

GNDA

23

22

VDD3

24 25 26

CKOUT

GND

VDD3

OUT8B

FILTER_PLL

EAPD

OUT8A

OUT1A

44

27

OUT7B

OUT1B

43

28

OUT7A

OUT2A

42

OUT2B

41

GND

40

VDD3

39

OUT3A

38

OUT3B

37

OUT4A

36

OUT4B

35

OUT5A

34

OUT5B

33

32

GND

31

VDD3

OUT6A

30

29

OUT6B

AM045329v1

8/50 Doc ID 022647 Rev 1

STA321MP Pin connections

Table 2. Pin description: TQFP-64 (STA321MPL)

Pin

number

Type Name Description

1 5-V tolerant TTL input buffer PDM_CLK PDM I/F CLK

6 5-V tolerant TTL input buffer PDMIN_6 PDM input channel 6

7 5-V tolerant TTL input buffer PDMIN_5 PDM input channel 5

8 5-V tolerant TTL input buffer PDMIN_4 PDM input channel 4

9 5-V tolerant TTL input buffer PDMIN_3 PDM input channel 3

10 5-V tolerant TTL input buffer PDMIN_2 PDM input channel 2

11 5-V tolerant TTL input buffer PDMIN_1 PDM input channel 1

15 5-V tolerant TTL Schmitt trigger input buffer RESET Global reset

16 CMOS input buffer with pull-down PLLB Bypass phase-locked loop

18

Bidirectional buffer: 5-V tolerant TTL Schmitt
trigger input; 3.3-V capable 2 mA slew-rate

SDA Serial data (I

2

C)

controlled output

2

19 5-V tolerant TTL Schmitt trigger input buffer SCL Serial clock (I

C)

20 5-V tolerant TTL Schmitt trigger input buffer XTI Crystal oscillator input (clock input)

21 Analog pad FILTER_PLL PLL filter

22 3.3-V analog supply voltage VDDA PLL supply

23 Analog ground GNDA PLL ground

25 3.3-V capable TTL tristate 4 mA output buffer CKOUT Clock output

29 3.3-V capable TTL 2 mA output buffer OUT8B PWM channel 8 output B

30 3.3-V capable TTL 2 mA output buffer OUT8A PWM channel 8 output A

31 3.3-V capable TTL 2 mA output buffer OUT7B PWM channel 7 output B

32 3.3-V capable TTL 2 mA output buffer OUT7A PWM channel 7 output A

33 3.3-V capable TTL 2 mA output buffer OUT6B PWM channel 6 output B

34 3.3-V capable TTL 2 mA output buffer OUT6A PWM channel 6 output A

38 3.3-V capable TTL 2 mA output buffer OUT5B PWM channel 5 output B

39 3.3-V capable TTL 2 mA output buffer OUT5A PWM channel 5 output A

40 3.3-V capable TTL 2 mA output buffer OUT4B PWM channel 4 output B

41 3.3-V capable TTL 2 mA output buffer OUT4A PWM channel 4 output A

42 3.3-V capable TTL 2 mA output buffer OUT3B PWM channel 3 output B

43 3.3-V capable TTL 2 mA output buffer OUT3A PWM channel 3 output A

47 3.3-V capable TTL 2 mA output buffer OUT2B PWM channel 2 output B

48 3.3-V capable TTL 2 mA output buffer OUT2A PWM channel 2 output A

49 3.3-V capable TTL 2 mA output buffer OUT1B PWM channel 1 output B

50 3.3-V capable TTL 2 mA output buffer OUT1A PWM channel 1 output A

Doc ID 022647 Rev 1 9/50

Pin connections STA321MP

Table 2. Pin description: TQFP-64 (STA321MPL) (continued)

Pin

number

Type Name Description

51 3.3-V capable TTL 4 mA output buffer EAPD Ext. amp power-down

55 3.3-V capable TTL 2 mA output buffer BICKO Output serial clock

56 3.3-V capable TTL 2 mA output buffer LRCKO Output left/right clock

57 3.3-V capable TTL 2 mA output buffer SDO_12 Output serial data channels 1 & 2

58 3.3-V capable TTL 2 mA output buffer SDO_34 Output serial data channels 3 & 4

62 3.3-V capable TTL 2 mA output buffer SDO_56 Output serial data channels 5 & 6

63 3.3-V capable TTL 2 mA output buffer SDO_78 Output serial data channels 7 & 8

64 5-V tolerant TTL Schmitt trigger input buffer PWDN Device power-down

3,12,24,

28,35,

3.3-V digital supply voltage VDD3 3.3-V supply

44,52,59

2,4,13,

27,36,

Digital ground GND Ground

45,53,60

14,17,26,

37, 46,

NC Not connected

54,61,63

Table 3. Pin description: VFQFPN-56 (STA321MP)

Pin

number

Type Name Description

1 5-V tolerant TTL input buffer PDM_CLK PDM I/F CLK

5 5-V tolerant TTL input buffer PDMIN_6 PDM input channel 6

6 5-V tolerant TTL input buffer PDMIN_5 PDM input channel 5

7 5-V tolerant TTL input buffer PDMIN_4 PDM input channel 4

8 5-V tolerant TTL input buffer PDMIN_3 PDM input channel 3

9 5-V tolerant TTL input buffer PDMIN_2 PDM input channel 2

10 5-V tolerant TTL input buffer PDMIN_1 PDM input channel 1

13 5-V tolerant TTL Schmitt trigger input buffer RESET Global reset

14 CMOS input buffer with pull-down PLLB Bypass phase-locked loop

15

Bidirectional buffer: 5-V tolerant TTL Schmitt
trigger input; 3.3-V capable 2 mA slew-rate

SDA Serial data (I

2

C)

controlled output

2

16 5-V tolerant TTL Schmitt trigger input buffer SCL Serial clock (I

C)

17 5-V tolerant TTL Schmitt trigger input buffer XTI Crystal oscillator input (clock input)

18 Analog pad FILTER_PLL PLL filter

19 3.3-V analog supply voltage VDDA PLL supply

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STA321MP Pin connections

Table 3. Pin description: VFQFPN-56 (STA321MP) (continued)

Pin

number

20 Analog ground GNDA PLL ground

22 3.3-V capable TTL tristate 4 mA output buffer CKOUT Clock output

25 3.3-V capable TTL 2 mA output buffer OUT8B PWM channel 8 output B

26 3.3-V capable TTL 2 mA output buffer OUT8A PWM channel 8 output A

27 3.3-V capable TTL 2 mA output buffer OUT7B PWM channel 7 output B

28 3.3-V capable TTL 2 mA output buffer OUT7A PWM channel 7 output A

29 3.3-V capable TTL 2 mA output buffer OUT6B PWM channel 6 output B

30 3.3-V capable TTL 2 mA output buffer OUT6A PWM channel 6 output A

33 3.3-V capable TTL 2 mA output buffer OUT5B PWM channel 5 output B

34 3.3-V capable TTL 2 mA output buffer OUT5A PWM channel 5 output A

35 3.3-V capable TTL 2 mA output buffer OUT4B PWM channel 4 output B

36 3.3-V capable TTL 2 mA output buffer OUT4A PWM channel 4 output A

37 3.3-V capable TTL 2 mA output buffer OUT3B PWM channel 3 output B

38 3.3-V capable TTL 2 mA output buffer OUT3A PWM channel 3 output A

41 3.3-V capable TTL 2 mA output buffer OUT2B PWM channel 2 output B

42 3.3-V capable TTL 2 mA output buffer OUT2A PWM channel 2 output A

43 3.3-V capable TTL 2 mA output buffer OUT1B PWM channel 1 output B

Type Name Description

44 3.3-V capable TTL 2 mA output buffer OUT1A PWM channel 1 output A

45 3.3-V capable TTL 4 mA output buffer EAPD Ext. amp power-down

48 3.3-V capable TTL 2 mA output buffer BICKO Output serial clock

49 3.3-V capable TTL 2 mA output buffer LRCKO Output left/right clock

50 3.3-V capable TTL 2 mA output buffer SDO_12 Output serial data channels 1 & 2

51 3.3-V capable TTL 2 mA output buffer SDO_34 Output serial data channels 3 & 4

54 3.3-V capable TTL 2 mA output buffer SDO_56 Output serial data channels 5 & 6

55 3.3-V capable TTL 2 mA output buffer SDO_78 Output serial data channels 7 & 8

56 5-V tolerant TTL Schmitt trigger input buffer PWDN Device power-down

3,11,21,

24,31,

39,46,52

2,4,12,

23,32,

40,47,53

3.3-V digital supply voltage VDD3 3.3-V supply

Digital ground GND Ground

Doc ID 022647 Rev 1 11/50

Electrical specifications STA321MP

3 Electrical specifications

3.1 Absolute maximum ratings

Table 4. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

V

V

V

V

T

T

DD

DDA

i

o

stg

amb

3.3-V I/O power supply -0.5 4 V

3.3-V logic power supply -0.5 4 V

Voltage on input pins -0.5 VDD + 0.5 V

Voltage on output pins -0.5 VDD + 0.3 V

Storage temperature -40 150 °C

Ambient operating temperature -40 90 °C

3.2 Thermal data

Table 5. Thermal data

Symbol Parameter Min Typ Max Unit

R

thj-case

Thermal resistance, junction-case (thermal pad)
STA321MP

3.3 Recommended operating conditions

Table 6. Recommended operating conditions

Symbol Parameter Min Typ Max Unit

1.5 °C/W

V

V

T

DD

DDA

j

I/O power supply 3.0 3.6 V

Logic power supply 3.0 3.6 V

Operating junction temperature -40 125 °C

12/50 Doc ID 022647 Rev 1

STA321MP Electrical specifications

3.4 Electrical specifications

The following specifications are valid for VDD = 3.3 V ± 0.3 V, V

= 3.3 V ± 0.3 V and

DDA

Tamb = 0 to 70 °C, unless otherwise stated

Table 7. General interface electrical specifications

Symbol Parameter Conditions Min Typ Max Unit

I

il

I

ih

I

OZ

V

esd

1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.

Table 8. DC electrical characteristics: 3.3-V buffers

Low-level input no pull-up Vi = 0 V 1

High-level input no
pull-down

Tristate output leakage
without pull-up/down

Electrostatic protection
(human body model)

V

= VDD 2μA

i

= VDD 2μA

V

i

Leakage < 1μA2000V

Symbol Parameter Conditions Min Typ Max Unit

V

IL

V

IH

V

ILhyst

V

IHhyst

V

hyst

V

ol

V

oh

Low-level input voltage 0.8 V

High-level input voltage 2.0 V

Low-level threshold Input falling 0.8 1.35 V

High-level threshold Input rising 1.3 2.0 V

Schmitt trigger hysteresis 0.3 0.8 V

Low-level output IoI = 100 µA 0.2 V

VDD-

0.2

High-level output

I

= -100 µA

oh

= -2 mA 2.4 V

I

oh

(1)

μA

V

Doc ID 022647 Rev 1 13/50

Pin description STA321MP

4 Pin description

PDM interface clock (PDM_CLK)

The clock to the PDM interface is provided on this pin and will be used by the device to
sample the digital microphone data. This clock must be used to clock both the interface and
the microphones. The clock frequency must not exceed the upper limit of the microphone’s
specific clock frequency (please refer to the datasheet of the specific microphone used).

PDM input channels (PDMIN_1/6)

Audio information enters the device through the PDM input channels. These input pins
receive the digital output signal from the microphones.

RESET

Driving this pin low turns off the outputs and returns all settings to their defaults.

I2C bus

The SDA and SCL pins operate per the Phillips I2C specification. See Section 5: I2C bus

operation.

Phase-locked loop (PLL)

The phase-locked loop section provides the system timing signals and CKOUT.

Clock output (CKOUT)

System synchronization and master clocks are provided by CKOUT. This clock can be
conveniently divided and then used to clock both the PDM interface and the microphones.
Please refer to Figure 6.

PWM outputs (OUT1 through OUT8)

The PWM outputs provide the input signal for the power devices.

Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)

These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.

Device power-down (PWDN)

Pulling PWDN low begins the power-down sequence which puts the STA321MP into a
low-power state. EAPD (pin 45 of the VFQFN-56 or pin 51 of the TQFP-64) goes low
approximately 30 ms later.

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STA321MP I2C bus operation

5 I2C bus operation

The STA321MP supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).

This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA321MP is always a slave device in all of its communications.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.

5.1.2 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.

5.1.3 Stop condition

STOP is identified by a low to high transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A STOP condition terminates communication between
STA321MP and the bus master.

5.1.4 Data input

During the data input the STA321MP samples the SDA signal on the rising edge of clock
SCL.

For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the Omega FFX core, the master must
initiate with a start condition. Following this, the master sends 8 bits to the SDA line (MSB
first) corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA321MP the I
SA port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.

th

The 8
0 for write mode. After a START condition the STA321MP identifies on the bus the device

bit (LSB) identifies a read or write operation RW, this bit is set to 1 in read mode and

2

C interface has two device addresses depending on the

2

C bus

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