ST STA020 User Manual

STA020

96kHz DIGITAL AUDIO INTERFACE TRANSMITTER

MONOLITHIC DIGITAL AUDIO INTERFACE TRANSMITTER

3.3V SUPPLY VOLTAGE

SUPPORTS:

– AES/EBU, IEC 958,

– S/PDIF, & EIAJ CP-340

– Professional and Consumer Formats

SO24

PARITY BITS AND CRC CODES

ORDERING NUMBER: STA020D

GENERATED

Product(s)

TRANSPARENT MODE ALLOWS DIRECT

CONNECTION OF STA020D AND STA120

DESCRIPTION

The STA020D is a monolithic CMOS device which

encodes and transmits audio data according to the

Obsolete

AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 inter-

face standards. It supports 96kHz sample rate op-

eration

ble of supporting a wide variety of formats.

The STA020D accepts audio and digital data

The STA020D multiplexes the channel, user, and

which is then multiplexed, encoded and driven

validity data directly from serial input pins with

onto a cable.

dedicated input pins for the most important chan-

The audio serial port is double buffered and capa-

nel status bits.

Product(s)

BLOCK DIAGRAM

VD+

GND

MCK

RST

Obsolete

SCK

AUDIO

FSYNC

SERIAL PORT

TXP

SDATA

MUX

DIFFERENTIAL

TXN

REGISTERS

DEDICATED CHANNEL CBL

TRNPT

D97AU599A

STATUS BUS

April 2010

1/14

STA020

ABSOLUTE MAXIMUM RATINGS

Symbol	Parameter	Value	Unit

VD+	DC Power Supply	4	V
VIND	Digital Input Voltage	-0.3 to VD+ 0.3	V
Tamb	Ambient Operating Temperature (power applied)	-20 to +85	°C
Tstg	Storage Temperature	-40 to 150	°C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground)

	Symbol		Parameter								Test Condition			Min.	Typ.	Max.	Unit

	VD+	DC Voltage												3	3.3	3.6	V
	Tamb	Ambient Operating Temp.												0	25	70	°C
	PIN CONNECTIONS (Top view)													Product(s)
	PIN CONNECTIONS (Top view)

									1			24
					C7/C3				1			24	TRNPT/FC1
									2			23
						PRO			2			23	M0
									3			22
				C1/FC0					3			22	M1

					C6/C2			4			Obsolete
					C6/C2			4				21	M2
						MCK			5			20	TXP
						SCK		6				19	VD+
				FSYNC				7		-		18	GND
				SDATA				8		-		17	TXN
				SDATA				8				17	TXN
							V	9				16
							V	9				16	RST
		Product(s)										15	CBL/SBC
					C/SBF			10				15	CBL/SBC
							U	11				14	EM0/C9
				C9/C15				12				13	EM1/C8
											D97AU608A

Obsolete
	PIN DESCRIPTION
	N°	Pin										Function
	Power Supply Connections
	18	GND		Ground.

	19	VD+		Positive Digital Power. Nominally +3.3V.

	Audio Input Interface

	6	SCK		Serial Clock.
				Serial clock for SDATA pin which can be configured (via the M0, M1 and M2 pins) as an
				input or output and can sample data on the rising or falling edge.As an output, SCK will
				contain 32 clocks for every audio sample.

2/14

STA020

PIN DESCRIPTION (continued)

N°

Function

FSYNC

Frame Sync.

Delineates the serial data and may indicate the particular channel, left or right and may be

an input or output. The format is based on M0, M1 and M2 pins.

SDATA

Serial Data.

Audio data serial input pin.

21,

M0, M1, M2

Serial Port Mode Select.

22,23

Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.

Control Pins

Channel Status Bit 7/Channel Status Bit 3

C7/C3

In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the

inverse of channel status bit 3,

C7/C3 are ignored in Transparent Mode.

Professional/Consumer Select.

PRO

Selects between professional mode

(PRO

low) and consumer mode

(PRO

high). This pin

defines the functionality of the channel status parallel pins. PRO is ignored in Transparent

Mode.

Channel Status Bit 1/Frequency Control 0.

C1/FC0

In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and

FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When

FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent

Mode.

Channel Status Bit 6/Channel Status Bit 2.

C6/C2

In professional mode, C6 is the inverse of channel status bit 6. In consumer mode,

is the

inverse of channel status bit 2.

C6/C2 are ignored in Transparent Mode

Product(s)

Validity.

Validity bit serial input port. This bit is defined as per the digital audio standards wherein V =

0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio

signal is not suitable for conversion to analog, i.e. invalid.

C/SBF

Channel Status Serial Input/Subcode Frame Clock.

In professional and consumer modes this pin is the channel status serial input port. In CD

mode this pin inputs the CD subcode frame clock.

Obsolete

User Bit.

User bit serial input port.

Channel Status Bit 9/Channel Status Bit 15.

C9/C15

In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer

mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1).

C9/C15 are ignored in

Transparent Mode.

Emphasis 1/Channel Status Bit 8.

EM1/C8

In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer

mode, C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in

Product(s)

Transparent Mode.

Emphasis 0/Channel Status Bit 9.

EM0/C9

In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer

mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). EM0/C9 are ignored in

Transparent Mode.

CBL/SBC

Channel Status Block Output/Subcode Bit Clock.

Obsolete

In professional and consumer modes, the channel status block output is high for the first 15

bytes of channel status. In CD mode, this pin outputs the subcode bit clock.

Master Reset.

RST

When low, all internal counters are reset.

3/14

STA020

PIN DESCRIPTION (continued)

N°	Pin	Function

24	TRNPT/FC1	Transparent Mode/Frequency Control 1.
		In professional mode, setting TRNPT low selects normal operation & CBL is an output.
		Setting TRNPT high, allows the STA020D to be connected directly to an STA120. In
		transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and
		FC1 are encoded versions of channel status bits 24 and 25. When FC0 and FC1 are both
		high, CD mode is selected.

Transmitter Interface

5	MCK	Master Clock. Clock input at 128x the sample frequency which defines the transmit timing.
		In trasparent mode MCK must be 256 Fs.

20, 17	TXP, TXN	Differential Line Drivers.

DIGITAL CHARACTERISTICS (Tamb = 25°C; VD+ = 3.3V 10%)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

VIH

High-Level Input Voltage

2.0

VDD+0.3

VIL

Low-Level Input Voltage

-0.3

Product(s)

+0.8

VOH

High-Level Output Voltage

IO = 200 A

VDD-1.0

VOL

Low-Level Output Voltage

IO = 3.2mA

0.4

Iin

Input Leakage Current

1.0

MCK

Master Clock frequency

(Note 1)

Obsolete

MHz

Master Clock Duty Cycle

(high time/cycle time)

Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.

Figure 1. STA020D Professional & Consumer Modes Typical Connection Diagram.

Product(s)

+3.3V

EXTERNAL

CLOCK

0.1 F

FSYNC

MCK

VD+

GND

ObsoleteCONTROLLER

STA020

AUDIO

SCK

TRNPT

DATA

SDATA

PROCESSOR

CBL

SERIAL PORT

MODE SELECT

UNUSED

TXP

RST

TRANSMITTER

CHANNEL

TXN

CIRCUIT

8 DEDICATED C.S. BITS

STATUS BITS

CONTROL

D97AU600A

4/14

Line Drivers

The STA020D has and V bits.

STA020

Figure 2. STA020D Typical Connection Diagram.

to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The chip accepts audio and con-

			EXTERNAL	+5V
			CLOCK	+5V
	FSYNC		MCK	VD+		0.1 F
	FSYNC	7	5	19	GND
AUDIO	SCK	7	5	19	GND
AUDIO	SCK	6		18
DATA	SDATA	6
PROCESSOR	SDATA	8
PROCESSOR

	V	9		23	M0
	SBF	9		23	M1
DECODER	SBF	10		22	M1	SERIAL PORT
						SERIAL PORT
	U				M2	MODE SELECT
SUBCODE	U	11		21	M2	MODE SELECT
PORT	SBC	11	STA020	21
PORT
		15
		15
				20	TXP
RESET	RST	16		20		TRANSMITTER
CONTROL		16

					TXN	CIRCUIT
				17	TXN	CIRCUIT
				17
CHANNEL		8 DEDICATED C.S. BITS
STATUS BITS		8 DEDICATED C.S. BITS
CONTROL
						D99AU989A
						Product(s)
GENERAL DESCRIPTION
The STA020D is a monolithic CMOS circuit that encodes and transmits audio and digital data according
a transformer, to a transmission line.			Obsolete

ing 110Ohm transmission lines. (RS422 line driver compatible).

trol data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through - Product(s)dedicated pins for the most important control bits and a serial input port for the C, U The differential line drivers for STA020D are low skew, low impedance, differential outputs capable of driv-

ObsoleteThey can also be disabled by resetting the device (RST = low).

STA020D DESCRIPTION

The STA020D accepts 16 to 24-bit audio samples through a serial port configured in one of seven formats; provides several pins dedicated to particular channel status bits and allows all channel status, user and validity bits to be serially input through port pins. This data is multiplexed, the parity bit is generated and the bit stream is biphase-mark encoded and driven through an RS422 line driver.

The STA020D operates as a professional or consumer interface transmitter selectable by pin 2, PRO. As a professional interface device, the dedicated channel status input pins are defined according to the professional standard, and the CRC code (C.S. byte 23) can be internally generated.

As a consumer device, the dedicated channel status input pins are defined according to the consumer standard. A submode provided under the consumer mode is compact disk, CD, mode. When transmitting data from a compact disk, the CD subcode port can accept CD subcode data, extract channel status in-

5/14

+ 9 hidden pages

ST STA020 User Manual

96kHz DIGITAL AUDIO INTERFACE TRANSMITTER

VIND

Tamb

Tstg

Tamb

FSYNC

SDATA

TRNPT/FC1

Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.

Figure 1. STA020D Professional & Consumer Modes Typical Connection Diagram.

Figure 2. STA020D Typical Connection Diagram.