ST STA020 User Manual

96kHz DIGITAL AUDIO INTERFACE TRANSMITTER

Obsolete Product(s) - Obsolete Product(s)

 MONOLITHIC DIGITAL AUDIO INTERFACE

TRANSMITTER

 3.3V SUPPLY VOLTAGE
 SUPPORTS:

– AES/EBU, IEC 958,

– S/PDIF, & EIAJ CP-340

– Professional and Consumer Formats

 PARITY BITS AND CRC CODES

GENERATED

 TRANSPARENT MODE ALLOWS DIRECT

CONNECTION OF STA020D AND STA120

DESCRIPTION

The STA020D is a monolithic CMOS device which
encodes and transmits audio data according to the
AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 inter­face standards. It supports 96kHz sample rate op­eration

The STA020D accepts audio and digital data
which is then multiplexed, encoded and driven
onto a cable.

The audio serial port is double buffered and capa-

STA020

SO24

ORDERING NUMBER: STA020D

ble of supporting a wide variety of formats.

The STA020D multiplexes the channel, user, and
validity data directly from serial input pins with
dedicated input pins for the most important chan­nel status bits.

BLOCK DIAGRAM

M0 M1 M2 MCK RST

212223

SCK

FSYNC

SDATA

April 2010

6

7

8

10

C

11

U

9

V

AUDIO

SERIAL PORT

REGISTERS

DEDICATED CHANNEL

VD+19GND

7

STATUS BUS

18

MUX DIFFERENTIAL

15 24

CBL TRNPT

D97AU599A

165

20

TXP

17

TXN

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STA020

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

T

V

T

D+

IND

amb

stg

DC Power Supply 4 V

Digital Input Voltage -0.3 to VD+ 0.3 V

Ambient Operating Temperature (power applied) -20 to +85 °C

Storage Temperature -40 to 150 °C

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground)

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

T

DC Voltage 3 3.3 3.6 V

D+

Ambient Operating Temp. 0 25 70 °C

amb

PIN CONNECTIONS (Top view)

C7/C3

PRO

C1/FC0

C6/C2

MCK TXP

SCK

FSYNC

SDATA

C/SBF

C9/C15

1

2

3

4

5

6

7

8

V

9

10

11

U

12

D97AU608A

24

23

22

21

20

18

17

16

15

14

13

TRNPT/FC1

M0

M1

M2

VD+19

GND

TXN

RST

CBL/SBC

EM0/C9

EM1/C8

PIN DESCRIPTION

N° Pin Function

Power Supply Connections

18 GND Ground.

19 VD+ Positive Digital Power. Nominally +3.3V.

Audio Input Interface

6 SCK Serial Clock.

Serial clock for SDATA pin which can be configured (via the M0, M1 and M2 pins) as an
input or output and can sample data on the rising or falling edge.As an output, SCK will
contain 32 clocks for every audio sample.

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STA020

PIN DESCRIPTION (continued)

N° Pin Function

7 FSYNC Frame Sync.

8 SDATA Serial Data.

21,

22,23

Control Pins

10 C/SBF Channel Status Serial Input/Subcode Frame Clock.

11 U User Bit.

12 C9

13 EM1/C8

14 EM0/C9

15 CBL/SBC Channel Status Block Output/Subcode Bit Clock.

16 RST

M0, M1, M2 Serial Port Mode Select.

1C7

2PRO

3C1

4C6

9VValidity.

/C3 Channel Status Bit 7/Channel Status Bit 3

/FC0 Channel Status Bit 1/Frequency Control 0.

/C2 Channel Status Bit 6/Channel Status Bit 2.

/C15 Channel Status Bit 9/Channel Status Bit 15.

Delineates the serial data and may indicate the particular channel, left or right and may be
an input or output. The format is based on M0, M1 and M2 pins.

Audio data serial input pin.

Selects the format of FSYNC and the sample edge of SCK with respect to SDATA.

In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the
inverse of channel status bit 3, C7

Professional/Consumer Select.
Selects between professional mode (PRO
defines the functionality of the channel status parallel pins. PRO
Mode.

In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and
FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When
FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent
Mode.

In professional mode, C6
inverse of channel status bit 2. C6

Validity bit serial input port. This bit is defined as per the digital audio standards wherein V =
0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio
signal is not suitable for conversion to analog, i.e. invalid.

In professional and consumer modes this pin is the channel status serial input port. In CD
mode this pin inputs the CD subcode frame clock.

User bit serial input port.

In professional mode, C9
mode, C15
Transparent Mode.

Emphasis 1/Channel Status Bit 8.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C8
Transparent Mode.

Emphasis 0/Channel Status Bit 9.
In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer
mode, C9
Transparent Mode.

In professional and consumer modes, the channel status block output is high for the first 15
bytes of channel status. In CD mode, this pin outputs the subcode bit clock.

Master Reset.
When low, all internal counters are reset.

is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in

is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in

is the inverse of channel status bit 9 (bit 1 of byte 1). EM0/C9 are ignored in

is the inverse of channel status bit 6. In consumer mode, C2 is the

is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer

/C3 are ignored in Transparent Mode.

low) and consumer mode (PRO high). This pin

is ignored in Transparent

/C2 are ignored in Transparent Mode

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STA020

PIN DESCRIPTION (continued)

N° Pin Function

24 TRNPT/FC1 Transparent Mode/Frequency Control 1.

Transmitter Interface

5 MCK Master Clock. Clock input at 128x the sample frequency which defines the transmit timing.

20, 17 TXP, TXN Differential Line Drivers.

In professional mode, setting TRNPT low selects normal operation & CBL is an output.
Setting TRNPT high, allows the STA020D to be connected directly to an STA120. In
transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and
FC1 are encoded versions of channel status bits 24 and 25. When FC0 and FC1 are both
high, CD mode is selected.

In trasparent mode MCK must be 256 Fs.

DIGITAL CHARACTERISTICS (T

= 25°C; VD+ = 3.3V 10%)

amb

Symbol Parameter Test Condition Min. Typ. Max. Unit

V

V

V

V

High-Level Input Voltage 2.0

IH

Low-Level Input Voltage -0.3 +0.8 V

IL

High-Level Output Voltage IO = 200µA

OH

Low-Level Output Voltage IO = 3.2mA 0.4 V

OL

Input Leakage Current 1.0 10 A

I

in

VDD-1.0

V

VDD+0.3

V

MCK Master Clock frequency (Note 1) 26 MHz

Master Clock Duty Cycle (high time/cycle time) 40 60 %

Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.

Figure 1. STA020D Professional & Consumer Modes Typical Connection Diagram.

EXTERNAL

CLOCK

MCK

FSYNC

AUDIO

DATA

PROCESSOR

µCONTROLLER

or

UNUSED

CHANNEL

STATUS BITS

CONTROL

SCK

SDATA

CBL

C

U

V

RST

5

7

6

8

15

10

11

9

16

8 DEDICATED C.S. BITS

STA020

+3.3V

19

VD+

18

24

23

22

21

20

17

GND

TRNPT

M0

M1

M2

TXP

TXN

0.1µF

SERIAL PORT

MODE SELECT

TRANSMITTER

CIRCUIT

D97AU600A

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Figure 2. STA020D Typical Connection Diagram.

STA020

AUDIO

DATA

PROCESSOR

DECODER
SUBCODE

PORT

RESET

CONTROL

CHANNEL

STATUS BITS

CONTROL

FSYNC

SCK

SDATA

SBF

SBC

RST

EXTERNAL

CLOCK

MCK

7

6

8

V

9

10

U

11

15

16

8 DEDICATED C.S. BITS

5

STA020

+5V

19

VD+

18

23

22

21

20

17

GND

M0

M1

M2

TXP

TXN

0.1µF

SERIAL PORT

MODE SELECT

TRANSMITTER

CIRCUIT

D99AU989A

GENERAL DESCRIPTION

The STA020D is a monolithic CMOS circuit that encodes and transmits audio and digital data according
to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The chip accepts audio and con­trol data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through
a transformer, to a transmission line.

The STA020D has dedicated pins for the most important control bits and a serial input port for the C, U
and V bits.

Line Drivers

The differential line drivers for STA020D are low skew, low impedance, differential outputs capable of driv­ing 110Ohm transmission lines. (RS422 line driver compatible).

They can also be disabled by resetting the device (RST = low).

STA020D DESCRIPTION

The STA020D accepts 16 to 24-bit audio samples through a serial port configured in one of seven formats;
provides several pins dedicated to particular channel status bits and allows all channel status, user and
validity bits to be serially input through port pins. This data is multiplexed, the parity bit is generated and
the bit stream is biphase-mark encoded and driven through an RS422 line driver.

The STA020D operates as a professional or consumer interface transmitter selectable by pin 2, PRO

. As
a professional interface device, the dedicated channel status input pins are defined according to the pro­fessional standard, and the CRC code (C.S. byte 23) can be internally generated.

As a consumer device, the dedicated channel status input pins are defined according to the consumer
standard. A submode provided under the consumer mode is compact disk, CD, mode. When transmitting
data from a compact disk, the CD subcode port can accept CD subcode data, extract channel status in-

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