ST ST72E331, ST72T331 User Manual

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ST72E331

ST72T331

8-BIT MCU WITH 8 TO 16K OTP/EPROM, 256 EEPROM,

384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS

DATASHEET

■ User Program Memory (OTP/EPROM):

8 to 16K byte s

■ User EEPROM: 256 bytes

■ Data RAM: 384 to 512 bytes including 256 bytes

of stack

■ Master Reset and Power-On Reset

■ Low Voltage Detector (LVD) Reset option

■ Run and Power Saving modes

■ 44 or 32 multifunctional bidirectional I/O lines:

PSDIP42

– 15 or 9 programmable interrupt inputs – 8 or 4 high sink outputs

– 8 or 6 analog alternate inputs – 13 alternate functions –EMI filtering

■ Software or Hardware Watchdog (WDG)

■ Two 16-bit Timers, each featuring:

– 2 Input Captures – 2 Output Compares – External Clock input (on Timer A)

PSDIP56

– PWM and Pulse Generator modes

■ Synchronous Serial Peripheral Interface (SPI)

■ Asynchronous Serial Communications Interface

(SCI)

■ 8-bit ADC with 8 channels

■ 8-bit Data Manipulation

■ 63 basic Instructions an d 17 main Addressing

Modes

■ 8 x 8 Unsigned Multiply Instruction

■ True Bit Manipulation

■ Complete Development Support on DOS/

WINDOWS

■ Full Software Package on DOS/WINDOWS

Real-Time Emulator

(C-Compiler, Cross-Assembler, Debugger)

TQFP64

(See ordering information at the end of datashe

Notes:

1. One only on Time r A.

2. Six channels only for ST72 T 331J.

Device Summary

Features ST72T33 1J2 ST72T331J4 ST72T331 N2 ST72T331N4

Program Memory - bytes 8K 16K 8K 16K EEPROM - bytes 256 RAM (stack) - bytes 384 (256) 512 (256) 384 (256) 512 (256) Peripherals Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset Operating Supply 3 to 5.5 V CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85°C

Temperature Range - 40°C to + 125°C

Package TQFP44 - SDIP42 TQFP64 - SDIP56

Note: The ROM versions are supported by the ST72334 family.

May 2001 1/107

CSDIP42W

CSDIP56W

TQFP44

Rev. 1.8

Table of Contents

ST72E331

ST72T331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.5 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 EEPROM (EEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.2.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.2.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Table of Contents

5.3 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.3.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.4.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.6.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5.6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.6.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.6.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.6.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.7 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.7.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.7.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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ST72E331 ST72T331

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.3 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.4 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.5 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.6 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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1 GENERAL DESCRIPTION

1.1 INTRODUCTION

ST72E331 ST72T331

The ST72T331 HCMOS Microcontroller Unit (MCU) is a member of the ST7 f amily. The de vic e is based on an industry-standard 8-bit core and features an enhanced instruction set . The device is normally operated at a 16 MHz oscillator frequency. Under software control, the ST72T331 may be placed in either Wait, Slow or Halt modes, thus reducing power consumption. Th e enhance d instruction set and ad dressing modes afford real programming potential. In addition to standard 8-bit data management, the ST72T331 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes on the whole memory. The device includes a lo w consumption and

Figure 1. ST72T331 Block Diagram

Internal

OSCIN

OSCOUT

RESET

OSC

CONTROL

AND L VD

8-BIT CO RE

ALU

PROGRAM

MEMORY

(8 - 16K Bytes)

EEPROM

(256 Bytes)

CLOCK

fast sta r t on - c hip o s c illator, CP U , p r og ra m memo ry (OTP/EPROM versions), EEPROM, RAM, 44 (QFP64 and SDIP56) o r 32 (QFP44 and SD IP42) I/O lines, a Low V oltage Detector (LVD) and the following on-chip peripherals: Analog-to-Digital converter (ADC) with 8 (QFP64, SDIP56) or 6 (QFP44, SDIP42) multiplexed analog inputs, industry standard s ynchronous SPI and asynchronous SCI serial interfaces, digital Watchdog, two independent 16-bit Timers, one featuring an External Clock Input, and bo th featuring Pulse G enerator capabilities, 2 Input Captures and 2 Output Compares (only 1 Input Capture and 1 Output Compare on Timer A).

PORT A

PORT B

TIMER B

ADDRESS AND DATA BUS

PORT C

SPI

PORT D

8-BIT ADC

PA0 - > PA7

(8 bits for ST72T331N)

(5 bits for ST72T331J)

PB0 - > PB7

(8 bits for ST72T331N) (5 bits for S T 72T331J)

PC0 -> PC7

(8 bits)

PD0 -> PD7 (8 bits for ST72T331N) (6 bits for S T 72T331J)

PF0 -> PF 2,4,6,7

(6 bits)

RAM

(384 - 512 Bytes)

PORT F

TIMER A

POWER SUPPLY

PORT E

SCI

WATCHDOG

PE0 -> PE7

(6 bits for S T 72T 331N)

(2 bits for ST72T331J)

DDA

SSA

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ST72E331 ST72T331

1.2 PIN DESCRI PTION Figure 2. 64-Pin Thin QFP Package Pinout

1) PP

DD_2

NCNCPE1/RDI

64636261 60595857 56 555453 52 515049

PE4

PE5

PE6

PE7

PB0

(EI2)

PB1

(EI2)

PB2

(EI2)

PB3

(EI2)

(EI3)

PB4

(EI3)

PB5

(EI3)

PB6

(EI3)

PB7 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3

13 14 15 16

17181920 21222324 29303132

AIN4/PD4

1. VPP on EPROM/OTP only

PE0/TDO

AIN5/PD5

AIN6/PD6

AIN7/PD7

SS_2

OSCIN

OSCOUT

NCNCRESET

TEST/V

PA7

PA6

PA5

PA4

SS_1

DD_1

ICAP1_A/PF6

46 45 44

42 41 40 39 38 37 36 35 34 33

EXTCLK_A/PF7

PA3 PA2 PA1 PA0 PC7/SS PC6/SCK PC5/MOSI PC4/MISO PC3/ICAP1_B PC2/ICAP2_B PC1/OCMP1_B PC0/OCMP2_B V

SS_0

DD_0

(EI0) (EI0) (EI0) (EI0)

(EI1)

25262728

SSA

DDA

PF1

SS_3

DD_3

CLKOUT/PF0

PF2

OCMP1_A/PF4

Figure 4. 44-Pin Thin QFP Package Pinout

1) PP

DD_2

SS_2

RESET

TEST/V

PA7

PA6

PA5

20 21 22

ICAP1_A/PF 6

EXTCLK_A/PF7

(EI0)

PA4

SS_1

DD_1

PA3

PC7/S S

PC6/SCK

PC5/MOSI

PC4/MISO

PC3/ICAP 1_ B

PC2/ICAP 2_ B

PC1/OCMP1 _B

PC0/OCMP2 _B

SS_0

DD_0

PE0/TD0

PE1/RDI

PB0 PB1 PB2 PB3

PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4

44 43 42 41 40 39 3 8 37 3 6 35 3 4

(EI2)

(EI3)

6 7 8 9 10 11

12 13 14 15 16 1 7 18 1 9

AIN5/PD5

1. VPP on EPROM/OTP only

DDA

OSCIN

SSA

OSCOUT

(EI1)

PF1

PF2

CLKOUT/PF 0

OCMP1_A/PF4

Figure 3. 56-Pin Shrink DIP Package Pinout

PB4 PB5 PB6

PB7 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 AIN5/PD5 AIN6/PD6 AIN7/PD7

DDA

SSA

CLKOUT/PF0

PF1

OCMP1_A/PF4

EXTCLK_A/PF7

PC0/OCMP2_B PC1/OCMP1_B

1. VPP on EPROM/OTP only

PF2

ICAP1_A/PF6

DD_0

SS_0

PC2/ICAP2_B PC3/ICAP1_B

PC4/MISO PC5/MOSI

1 (EI3) 2 (EI3) 3 (EI3) 4 (EI3) 5 6 7 8 9 10 11 12 13 14

15 (EI1) 16 (EI1) 17 (EI1) 18 19 20 21 22 23 24 25 26 27 28

(EI2) 56 (EI2) 55 (EI2) 54 (EI2) 53

(EI0) 34 (EI0) 33 (EI0) 32 (EI0) 31

PB3 PB2 PB1

PB0 PE7

PE6

PE5

PE4

PE1/RDI

PE0/TD0

DD_2

OSCIN

OSCOUT

SS_2

RESET

TEST/V

41 40 39 38 37 36 35

30 29

PA7 PA6 PA5 PA4 V

SS_1

DD_1

PA3 PA2 PA1 PA0 PC7/SS PC6/SCK

Figure 5. 42-Pin Shrink DIP Package Pinout

PB4 AIN0/PD0 AIN1/PD1 AIN2/PD2 AIN3/PD3 AIN4/PD4 AIN5/PD5

DDA

SSA

CLKOUT/PF0

PF1

OCMP1_A/PF4

EXTCLK_A/PF7

PC0/OCMP2_B PC1/OCMP1_B

1. VPP on EPROM/OTP only

PF2

ICAP1_A/PF6

PC2/ICAP2_B PC3/ICAP1_B

PC4/MISO PC5/MOSI

(EI3) 2 3 4 5 6 7 8 9 10 11 12 13 14

15 16 17 18 19 20 21

(EI1) (EI1) (EI1)

(EI2) (EI2) (EI2) (EI2)

(EI0)

41 40 39 38 37 36 35 34 33 32 31 30 29

28 27 26 25 24 23 22

PB3 PB2 PB1 PB0 PE1/RDI PE0/TD0

DD_2

OSCIN OSCOUT

SS_2

RESET TEST/V PA7 PA6 PA5 PA4

SS_1

DD_1

PA3 PC7/SS PC6/SCK

6/107

Table 1. ST72T331Nx Pin Description

ST72E331 ST72T331

Pin n°

QFP64

Pin n°

SDIP56

Pin Na m e

Type

Description Remarks

1 49 PE4 I/O Port E4 High Sink 2 50 PE5 I/O Port E5 High Sink 3 51 PE6 I/O Port E6 High Sink 4 52 PE7 I/O Port E7 High Sink 5 53 PB0 I/O Port B0 External Interrupt: EI2 6 54 PB1 I/O Port B1 External Interrupt: EI2 7 55 PB2 I/O Port B2 External Interrupt: EI2 8 56 PB3 I/O Port B3 External Interrupt: EI2

9 1 PB4 I/O Port B4 External Interrupt: EI3 10 2 PB5 I/O Port B5 External Interrupt: EI3 11 3 PB6 I/O Port B6 External Interrupt: EI3 12 4 PB7 I/O Port B7 External Interrupt: EI3 13 5 PD0/AIN0 I/O Port D0 or ADC Analog Input 0 14 6 PD1/AIN1 I/O Port D1 or ADC Analog Input 1 15 7 PD2/AIN2 I/O Port D2 or ADC Analog Input 2 16 8 PD3/AIN3 I/O Port D3 or ADC Analog Input 3 17 9 PD4/AIN4 I/O Port D4 or ADC Analog Input 4 18 10 PD5/AIN5 I/O Port D5 or ADC Analog Input 5 19 11 PD6/AIN6 I/O Port D6 or ADC Analog Input 6 20 12 PD7/AIN7 I/O Port D7 or ADC Analog Input 7 21 13 V 22 14 V 23 V 24 V

DDA SSA DD_3 SS_3

S Power Supply for analog peripheral (ADC) S Ground for analog peripheral (ADC) S Main power supply

S Ground 25 15 PF0/CLKOUT I/O Port F0 or CPU Clock Output External Interrupt: EI1 26 16 PF1 I/O Port F1 External Interrupt: EI1 27 17 PF2 I/O Port F2 External Interrupt: EI1 28 NC Not Connected 29 18 PF4/OCMP1_A I/O Port F4 or Timer A Output Compare 1 30 NC Not Connected 31 19 PF6/ICAP1_A I/O Port F6 or Timer A Input Capture 1 32 20 PF7/EXTCLK_A I/O Port F7 or External Clock on Timer A 33 21 V 34 22 V

DD_0 SS_0

S Main power supply

S Ground 35 23 PC0/OCMP2_B I/O Port C0 or Timer B Output Compare 2 36 24 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1 37 25 PC2/ICAP2_B I/O Port C2 or Timer B Input Capture 2 38 26 PC3/ICAP1_B I/O Port C3 or Timer B Input Capture 1 39 27 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data 40 28 PC5/MOSI I/O Port C5 or SPI Master Out / Slave In Data 41 29 PC6/SCK I/O Port C6 or SPI Serial Clock 42 30 PC7/SS

I/O Port C7 or SPI Slave Select 43 31 PA0 I/O Port A0 External Interrupt: EI0

7/107

ST72E331 ST72T331

Pin n°

QFP64

Pin n°

SDIP56

Pin Na m e

Type

Description Remarks

44 32 PA1 I/O Port A1 External Interrupt: EI0 45 33 PA2 I/O Port A2 External Interrupt: EI0 46 34 PA3 I/O Port A3 External Interrupt: EI0 47 35 V 48 36 V

DD_1 SS_1

S Main power supply

S Ground 49 37 PA4 I/O Port A4 High Sink 50 38 PA5 I/O Port A5 High Sink 51 39 PA6 I/O Port A6 High Sink 52 40 PA7 I/O Port A7 High Sink

53 41 TEST/V

54 42 RESET

Test mode pin . In the EPROM programming mode, this pin acts as the programming voltage input V

PP.

I/O Bidirectional. Active low. Top priority non maskable interrupt.

This pin must be tied low in user mode

55 NC Not Connected 56 NC Not Connected 57 43 V

SS_2

58 44 OSCOUT O 59 45 OSCIN I 60 46 V

DD_2

S Ground

Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.

S Main power supply 61 47 PE0/TDO I/O Port E1 or SCI Transmit Data Out 62 48 PE1/RDI I/O Port E1 or SCI Receive Data In 63 NC Not Connected 64 NC Not Connected

Note 1: VPP on EPROM/OTP only.

Table 2. ST72T331Jx Pin Desc ription

Pin n°

QFP44

Pin n°

SDIP42

Pin Name Type Description Remarks

1 38 PE1/RDI I/O Port E1 or SCI Receive Data In 2 39 PB0 I/O Port B0 External Interrupt: EI2 3 40 PB1 I/O Port B1 External Interrupt: EI2 4 41 PB2 I/O Port B2 External Interrupt: EI2 5 42 PB3 I/O Port B3 External Interrupt: EI2 6 1 PB4 I/O Port B4 External Interrupt: EI3 7 2 PD0/AIN0 I/O Port D0 or ADC Analog Input 0 8 3 PD1/AIN1 I/O Port D1 or ADC Analog Input 1

9 4 PD2/AIN2 I/O Port D2 or ADC Analog Input 2 10 5 PD3/AIN3 I/O Port D3 or ADC Analog Input 3 11 6 PD4/AIN4 I/O Port D4 or ADC Analog Input 4 12 7 PD5/AIN5 I/O Port D5 or ADC Analog Input 5 13 8 V 14 9 V

DDA SSA

S Pow er Supply for analog perip heral (ADC )

S Ground for analog peripheral (ADC) 15 10 PF0/CLKOUT I/O Port F0 or CPU Clock Output External Interrupt: EI1 16 11 PF1 I/O Port F1 External Interrupt: EI1 17 12 PF2 I/O Port F2 External Interrupt: EI1

8/107

ST72E331 ST72T331

Pin n°

QFP44

Pin n°

SDIP42

Pin Name Type Description Remarks

18 13 PF4/OCMP1_A I/O Port F4 or Timer A Output Compare 1 19 14 PF6/ICAP1_A I/O Port F6 or Timer A Input Capture 1 20 15 PF7/EXTCLK_A I/O Port F7 or External Clock on Timer A 21 V 22 V

DD_0 SS_0

S Main power supply

S Ground 23 16 PC0/OCMP2_B I/O Port C0 or Timer B Output Compare 2 24 17 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1 25 18 PC2/ICAP2_B I/O Port C2 or Timer B Input Capture 2 26 19 PC3/ICAP1_B I/O Port C3 or Timer B Input Capture 1 27 20 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data 28 21 PC5/MOSI I/O Port C5 or SPI Master Out / Slave In Data 29 22 PC6/SCK I/O Port C6 or SPI Serial Clock 30 23 PC7/SS

I/O Port C7 or SPI Slave Select 31 24 PA3 I/O Port A3 External Interrupt: EI0 32 25 V 33 26 V

DD_1 SS_1

S Main power supply

S Ground 34 27 PA4 I/O Port A4 High Sink 35 28 PA5 I/O Port A5 High Sink 36 29 PA6 I/O Port A6 High Sink 37 30 PA7 I/O Port A7 High Sink

38 31 TEST/V

39 32 RESET 40 33 V

SS_2

41 34 OSCOUT O 42 35 OSCIN I 43 36 V

DD_2

Test mode pin. In the EPROM programming

mode, this pin acts as the programming voltage input V

PP.

I/O Bidirectional. Active low. Top priority non maskable interrupt.

S Ground

Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.

S Main power supply

This pin must be tied low in user mode

44 37 PE0/TDO I/O Port E0 or SCI Transmit Data Out

Note 1: VPP on EPROM/OTP only.

9/107

ST72E331 ST72T331

1.3 EXTERNAL CONNECTIONS

The following figure shows the recom mended external connections for the device.

The V

pin is only used for programming OTP

and EPROM devices and must be tied to ground in user mode.

The 10 nF and 0. 1 µF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff.

Figure 6. Recommended Extern al Connec tions

Optional if Low Voltage

Detector (LVD) is used

EXTERNAL RESET CIRCUIT

10nF

See A/D Converter Section

0.1µF

The external reset network is intended to protect the device against parasitic resets, especially in noisy environments.

Unused I/Os shoul d be t ied hi gh to av oid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.

4.7K

DDA

SSA

RESET

0.1µF

10/107

See Clocks Section

Or configure unused I/O ports by software as input with pull-up

10K

OSCIN

OSCOUT

Unused I/O

1.4 MEMORY MA P Figure 7. Program Memo ry Map

ST72E331 ST72T331

0000h

007Fh

0080h

01FFh

027Fh

0200h / 0280h

0BFFh

0C00h

0CFFh

0D00h

BFFFh C000h

E000h

FFDFh

FFE0h

FFFFh

HW Registers

(see Table 4)

384 Bytes RAM

512 Bytes RAM

Reserved

EEPROM256 Bytes

Reserved

16K Bytes

Program

8K Bytes

Memory

Program

Memory

Interrupt & Reset Vectors

(see Table 3)

0080h

Short Addressing

00FFh

0100h

01FFh

0080h

00FFh

0100h

RAM (zero page)

256 Bytes Stack/

16-bit Addressing RAM

Short Addressing

RAM (zero page)

256 Bytes Stack/

16-bit Addressing RAM

01FFh 0200h

027Fh

16-bit Addressing

RAM

Table 3. Interrupt Vector Map

Vector Address Description Remarks

FFE0-FFE1h FFE2-FFE3h FFE4-FFE5h FFE6-FFE7h

FFE8-FFE9h FFEA-FFEBh FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h FFF2-FFF3h FFF4-FFF5h FFF6-FFF7h FFF8-FFF9h

FFFA-FFFBh FFFC-FFFDh

FFFE-FFFFh

EEPROM Interrupt Vector

TIMER B Interrupt Vector TIMER A Interrupt Vector

External Interrupt Vector EI3 External Interrupt Vector EI2 External Interrupt Vector EI1 External Interrupt Vector EI0

TRAP (software) Interrupt Vector

Not Used Not Used

SCI Interrupt Vector

SPI interrupt vector

Not Used

Not Used Not Used

RESET Vector

Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt Internal Interrupt

External Interrupt External Interrupt External Interrupt External Interrupt

CPU Interrupt

11/107

ST72E331 ST72T331

Table 4. Hardware Register Mem ory Map

Address Block

0000h 0001h

Port A

0002h

Label

PADR PADDR PAOR

Data Register Data Direction Register Option Register

Reset

Status

00h 00h 00h

Remarks

R/W R/W R/W

0003h Reserved Area (1 byte) 0004h 0005h 0006h

Port C

PCDR PCDDR PCOR

Data Register Data Direction Register Option Register

00h 00h 00h

R/W R/W

R/W 0007h Reserved Area (1 byte) 0008h 0009h 000Ah

Port B

PBDR PBDDR PBOR

Data Register Data Direction Register Option Register

00h 00h 00h

R/W

000Bh Reserved Area (1 byte) 000Ch 000Dh 000Eh

Port E

PEDR PEDDR PEOR

Data Register Data Direction Register Option Register

00h 00h

0Ch

R/W

000Fh Reserved Area (1 byte) 0010h 0011h 0012h

Port D

PDDR PDDDR PDOR

Data Register Data Direction Register Option Register

00h 00h 00h

R/W

0013h Reserved Area (1 byte) 0014h 0015h 0016h 0017h to 001Fh

Port F

PFDR PFDDR PFOR

Data Register Data Direction Register Option Register

Reserved Area (9 bytes)

00h 00h 28h

R/W

0020h MISCR Miscellaneous Regis ter 00h 0021h 0022h 0023h 0024h to 0029h 002Ah

002Bh

SPI

WDG

SPIDR SPICR SPISR

WDGCR WDGSR

SPI Data I/O Register SPI Control Register SPI Status Register

Reserved Area (6 bytes)

Watchdog Control Register Watchdog Status Register

xxh xxh 00h

7Fh

00h

R/W

Read Only

R/W

R/W 002Ch EEPROM EEPCR EEPROM Control Register 00h R/W Register 002Dh to 0030h

Reserved Area (4 bytes)

12/107

ST72E331 ST72T331

Address Block

0031h 0032h 0033h 0034h-0035h

0036h-0037h

0038h-0039h

Timer A

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

Label

TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR

Reset

Status

00h 00h xxh xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W

R/W 0040h Reserved Area (1 byte) 0041h 0042h 0043h 0044h-0045h

0046h-0047h

0048h-0049h

004Ah-004Bh

004Ch-004Dh

004Eh-004Fh

0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h to 006Fh 0070h 0071h 0072h to 007Fh

Timer B

SCI

ADC

TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR

SCIETPR

ADCDR ADCCSR

Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved SCI Extended Transmit Prescaler Register

Reserved Area (24 bytes)

ADC Data Register ADC Control/Status Register

Reserved Area (14 bytes)

00h 00h xxh xxh xxh 80h

00h FFh FCh FFh FCh

xxh

80h

00h C0h

xxh

00x----xb

xxh

00h

---

00h

R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W Read Only R/W R/W R/W R/W R/W Reserved R/W

Read Only R/W

Notes:

1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

2. External pin not available.

3. Not used in versions without Low Voltage Detector Reset.

Remarks

13/107

ST72E331 ST72T331

1.5 OPTION BYTE

The user has the option to select software watchdog or hardware watchdog (see description in the Watchdog chapter). When program ming EPROM or OTP devices, this o ption is selected in a men u by the user of the EPROM programmer before burning the EPROM/O TP. The Option Byte is located in a non-user map. No address has to be specified. The Option Byte is at FFh after UV erasure and must be properly programmed t o set desired options.

OPTBYTE

- - - - b3 b2 - WDG

Bit 7:4 = Not used

Bit 3 = Reserved, must be cleared.

Bit 2 = Reserved, must be s et on S T7 2T331 N devices and must be cleared on ST72T331J devices.

Bit 1 = Not used

Bit 0 = WDG

Watchdog disable

0: The Watchdog is enabled after reset (Hardware

Watchdog).

1: The Watchdog is not enabled after reset (Soft-

ware Watchdog).

14/107

2 CENTRAL PROCE SSI NG UNIT

ST72E331 ST72T331

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

2.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low po wer modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions.

Figure 8. CPU Registers

RESET VALUE = XXh

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Cou nt er (P C )

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

1C11HI NZ

1X11X1XX 70

PCL

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

15/107

ST72E331 ST72T331

CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC)

Read/Write Reset Value: 111x1xxx

111HINZC

The 8-bit Condition Code register c ontains the interrupt mask and four flags represent ative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H

Half carry

This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines .

Bit 3 = I

Interrupt mask

This bit is set by hardware when entering in interrupt or by software to disable all interrup ts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed whe n I is cleared. By default an interrupt routine is not in terruptable

because the I bi t is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N

Negative

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmeti c, logical or data manipulation. It is a copy of the 7 bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Zero

Bit 1 = Z

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from

zero.

1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

16/107

ST72E331 ST72T331

CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP)

Read/Write Reset Value: 01FFh

15 8

00000001

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9).

Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, wi thout indicating the s tack overflow. The prev iously stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the retu rn address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location point ed to by the SP. Then the other registers are stored in the next locations as shown in Figure 9.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.

Figure 9. Stack Manipulation Example

@ 0100h

@ 01FFh

CALL

Subroutine

PCH PCL

Stack Higher Address = 01FFh Stack Lower Address =

Interrupt

Event

X PCH PCL PCH PCL

0100h

PUSH Y POP Y IRET

X PCH PCL PCH

PCL

A X

PCH

PCL

PCH

PCL

PCH

PCL

RET

or RSP

17/107

ST72E331 ST72T331

3 CLOCKS, RESET, INTERRUPTS & POWER SAVI NG MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a crystal or ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f

from the external oscillator frequency (f

) is derived

CPU

OSC).

The

external Oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in Slow Mode, to red uce th e f requency of the f

; this clock signal is also routed to the on-

CPU

chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.

The internal oscillat or is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for f

osc

. The

circuit shown in Fi gure 11 is recommended whe n using a crystal, and Tab le 5 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as p ossible to the input pins i n order to minimize output distortion and start-up stabilisation time.

Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used.

3.1.2 External Clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 10.

Figure 10. External Clock Source Connections

OSCIN OSCOUT

EXTERNAL

CLOCK

Figure 11. Crystal/Ceramic Resonator

OSCOUT

OSCIN

Table 5 Recommended Values for 16 MHz

SMAX

Crystal Resonator (C

SMAX

OSCIN

OSCOUT

Ω

56pF 47pF 22pF 56pF 47pF 22pF

: Parasitic series resistance of the quartz

< 7pF)

Ω

150

Ω

crystal (upper limit).

: Parasitic shunt capacitance of the quartz crys-

tal (upper limit 7pF).

OSCOUT

, C

: Maximum total capacitance on

OSCIN

pins OSCIN and OSCOUT (the value includes the external capacitance tied to the p in plus the parasitic capacitance of the board and of the device).

18/107

Figure 12. Clock Prescaler Block Diagram

OSCIN

OSCOUT

%2 % 2, 4, 8, 16

OSCOUT

CPU

to CPU and Peripherals

3.2 RESET

ST72E331 ST72T331

3.2.1 Introd uct i on

There are four sources of Reset:

– RESET

pin (external source) – Power-On Reset (Internal source) – WATCHDOG (Internal Source) – Low Voltage Detection Reset (internal source) The Reset Service Routine vector is located at ad-

dress FFFEh-FFFFh.

3.2.2 External Reset

The RESET

pin is both an input and an open-drain output with integrated pull-up resi stor. When one of the internal Reset sources is active, the Reset pin is driven low for a duration of t

RESET

to reset

the whole application.

3.2.3 Reset Operation

The duration of the Reset state is a minimum of 4096 internal CPU Clock cycles. During the Reset state, all I/Os take their reset value.

A Reset signal originating from an external source must have a duration of at least t

PULSE

in order to

Figure 13. Reset Block Diagram

be recognised. This detection is asynchronous and therefore the MCU can enter Reset state even in Halt mode.

At the end of the Reset cycle, the MCU may be held in the Reset state by an External Reset signal. The RESET

has risen to a point where the MCU can oper-

pin may thus be used to ens ure

ate correctly before the user program is run. Following a Reset event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to allow the oscillat or to stabilise and to ensure that recovery has taken place from the Reset state.

In the high state, the RESET ternally to a pull-up resistor (R

pin is connected in-

). This resistor

can be pulled low b y ex ternal circuitry to res et t he device.

The RESET

pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is rec ommended to u se the external connections shown in Figure 6.

RESET

OSCILLATOR

SIGNAL

TO ST7

RESET

INTERN AL RESET

COUNTER

POWER-ON RESE T WATCHDOG RESET LOW VOLTAGE DETECTOR RESET

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ST72E331 ST72T331

RESET (Cont’d)

3.2.4 Low Voltage Detector Reset

The on-chip Low Voltage Detector (LVD) generates a static reset when the supply voltage is below a reference value. The LVD functions both during power-on as well as when the power supply drops (brown-out). The reference value for a voltage drop is lower than the reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

V V

Provided the minimun V the oscillator frequency) is above V MCU can only be in two modes:

- under full software control or

- in static safe reset In this condition, secure operation is always en-

sured for the application without the need for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus perm itting the MCU to reset other devices.

In noisy environments, the power supply may drop for short periods and cause the Low Voltage Detector to generate a Reset too frequen tly. In such

when VDD is rising

LVDUP LVDDOWN

when VDD is falling

value (guaranteed for

LVDDOWN

, the

cases, it is recommended to us e devices without the LVD Reset option and to rely on the watchdog function to detect application runaway conditions.

Figure 14. Low Voltage Detector Reset Function

LOW VOLTAGE

DETECTOR RESET

FROM

WATCHDOG

RESET

Figure 15. Low Voltage Detector Reset Signal

RESET

LVDUP

LVDDOWN

Note: See electrical characteristics for values of

LVDUP

and V

LVDDOWN

Figure 16. Temporization timing diagram after an internal Reset

LVDUP

Temporiz ation (40 96 CP U clock cy cl es)

$FFFE

20/107

Addresses

4 INTE RRUPTS

ST72E331 ST72T331

The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).

Note: After reset, all interrupts are disabled. When an interrupt has to be serviced:

– No rmal processing is susp ended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).

The interrupt service routine should finish with the IRET instruction which c auses the conten ts o f the saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction, the I bit will be cleared a nd the main pro gram will resume.

Priority Management

By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.

In the case when several inte rrupt s ar e simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the WAIT low power mode. Only external and specifically mentioned interrupts allow the proc essor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the I nterrupt Mapping Table).

4.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 1.

4.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding ext ernal interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.

The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).

An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.

If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed and inverted before entering the edge/level detection block.

Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.

4.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:

– The I bit of the CC register is cleared. – The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt is latched and thus remains pending.

Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status

– Access to the status register while the f lag i s set

followed by a read or write of an associated register.

Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

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ST72E331 ST72T331

INTERRUPTS (Cont’d) Figure 17. Inte rru pt P rocessing Flow c hart

FROM RESET

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

I BIT SET?

FETCH NEXT INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

IRET?

INTER RUPT

PENDING?

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM INTERRUPT VECTOR

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ST72E331 ST72T331

Table 6. Int errupt Mapp in g

Source

Block

RESET Reset N/A N/A yes F FFEh-FFFFh TRAP So ftware N/A N/A no FFFCh-FFFDh

EI0 Ext. Interrupt (Ports PA0:PA3) N/A N/A EI1 Ext. Interrupt (Ports PF0:PF2) N/A N/A FFF4h-FFF5h EI2 Ext. Interrupt (Ports PB0:PB3) N/A N/A FFF2h-FFF3h EI3 Ext. Interrupt (Ports PB4:PB7) N/A N/A FFF0h-FFF1h

SPI

TIMER A

TIMER B

SCI

EEPROM EEPROM End of Programming EEPCR E2ITE FFE4h-FFE5h

Transfer Complete Mode Fault MODF Input Capture 1 Output Compare 1 OCF1_A Input Capture 2 ICF2_A Output Compare 2 OCF2_A Timer Overflow TOF_A Input Capture 1 Output Compare 1 OCF1_B Input Capture 2 ICF2_B Output Compare 2 OCF2_B Timer Overflow TOF_B Transmit Buffer Empty Transmit Complete TC Receive Buffer Full RDRF Idle Line Detect IDLE Overrun OR

Description

NOT USED FFFAh-FFFBh NOT USED FFF8h-FFF9h

NOT USED FFEEh-FFEFh

NOT USED FFE2h-FFE3h NOT USED FFE0h-FFE1h

Label

SPISR

TASR

TBSR

SCISR

Flag

SPIF

ICF1_A

ICF1_B

TDRE

Exit

from

HALT

yes

Vector

Address

FFF6h-FFF7h

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

Priority

Order

Highest

Priority

Lowest Priority

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ST72E331 ST72T331

4.4 POWER SAVING MODES

4.4.1 Introd uct i on

There are three Power Saving modes. Slow Mode is selected by setting the rele vant bits in the Miscellaneous register. Wait and Halt m odes may b e entered using the WFI and HALT instructions.

Figure 18. WAIT Flow Chart

WFI INSTRUCTION

4.4.2 Slow Mode

In Slow mode, the oscillator frequency can be d ivided by a value defined in the Miscellaneous Register. The CPU and peripherals are clocked at this lower frequency. Slow mode is used to reduce power consumption, and enables the user to adapt clock frequency to available supply voltage.

4.4.3 Wait Mode

Wait mode places the M CU in a low power consumption mode by stopping the CPU. All peripherals remain active. During Wait mode, th e I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU w ill remain in Wait mode u ntil an Inte rrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up.

Refer to Figure 18 below.

INTERRUPT

OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT

RESET

OSCILLATOR PERIPH. CLOCK CPU CLOCK

I-BIT

4096 CPU CLOCK

CYCLES DELAY

OFF CLEARED

ON SET

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OSCILLATOR PERIPH. CLOCK CPU CLOCK

I-BIT

FETCH RESET VECTOR

OR SERVICE INTERRUP T

Note: Before servicing an interrupt, the CC register is pushed on the sta ck. The I-Bit is s et d uring the inte rrupt routine and cleared when the CC register is popped.

ON SET

POWER SAVING MODES (Cont’d)

4.4.4 Halt Mode

The Halt mode is the MCU lowest power consumption mode. The Halt mode is entered by executing the HALT instruction. The internal oscillator is then turned off, causing all internal processing to be stopped, including the operation of the on-chip peripherals. The Halt mode cannot be used whe n the watchdog is enabled, if the HALT instruction is executed while the watchdog system is enabled, a watchdog reset is generated thus resetting the entire MCU.

When entering Halt mode, the I bit in the CC Register is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of an interrupt or a reset. Refer t o the I nterrupt M apping Table. The oscillator is then turned on and a stabilization time is provided before releasing CPU operation. The stabilization time is 4096 CPU clock cycles. After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or by fetching the reset vector if a reset wakes it up.

ST72E331 ST72T331

Figure 19. HALT Flow Chart

HALT INSTRUCTION

WATCHDOG

RESET

EXTERNAL

INTERRUPT

OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT

WDG

ENABLED?

OFF

OFF CLEARED

RESET

1) or some specific interrupts

2) if reset PERIPH. CLOCK = ON ; if interrupt PERIPH. CLOCK = OFF

Note: Before servicing an interrupt, the CC register is pushed on th e sta ck. The I-Bit is s et d uring the inte rrupt routine and cleared when the CC register is popped.

OSCILLATOR PERIPH. CLOCK CPU CLOCK

I-BIT

4096 CPU CLOCK

CYCLES DELAY

OSCILLATOR PERIPH. CLOCK

CPU CLOCK I-BIT

FETCH RESET VECTOR

OR SERVICE INTERRUPT

OFF

ON SET

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ST72E331 ST72T331

4.5 MISCELLANEOUS REGISTER

The Miscellaneous register allows to select the SLOW operating mode , the polarity of ex ternal i nterrupt requests and to output the internal clock.

PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS

Bit 7:6 = PEI[3:2]

Polarity Options

External Interrupt EI3 a nd EI2

These bits are set and cleared by software. They determine which event on EI2 and EI3 causes the

Bit 4:3 = PEI[1:0]

Polarity Opti o n s

These bits are set and cleared by so ftware. They determine which event on EI0 and EI1 causes the external interrupt according to Table 8.

Table 8. EI0 and E I1 External Inte rrup t P o larity

Options

Falling edge and low level

(Reset state) Falling edge only 1 0 Rising edge only 0 1

Rising and falling edge 1 1

External Interrupt EI1 and EI0

MODE PEI1 PEI0

external interrupt according to Table 7.

Table 7. EI2 and EI3 External Interrupt Polarity

Options

Note: Any modification of one of these two bits re-

sets the interrupt request related to t his interrupt vector.

MODE PEI3 PEI2

Falling edge and low level

(Reset state)

Falling edge only 1 0

Rising edge only 0 1

Rising and falling edge 1 1

Note: Any modification of one of these two bits resets the interrupt request related to this interrupt vect or.

Bit 5 = MCO

Main Clock Out

This bit is set and cleared by software. When set, it

Bit 2:1 = PSM[1:0]

Prescaler for Slow Mode

These bits are set and cleared by so ftware. They determine the CPU clock when the SMS bit is set according to the following table.

Table 9. f

Value in Slow Mode

CPU

Valu e

CPU

/ 4 0 0

OSC

/ 16 0 1

OSC

/ 8 1 0

OSC

/ 32 1 1

OSC

enables the output of the Internal Clock on the PPF0 I/O port. 0 - PF0 is a general purpose I/O port. 1 - MCO alternate function (f

is output on PF0

CPU

pin).

Bit 0 = SMS This bit is set and cleared by software.

0: Normal Mode - f

Slow Mode Select

= f

CPU

OSC

/ 2

(Reset state)

1: Slow Mode - the f

PSM[1:0] bits .

value is determined by the

CPU

PSM1 PSM0

26/107

5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introd uction

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs and for specific pins: – an alog signal input (ADC) – alterna te signal input/output for the on-chip pe-

ripherals. – external interrupt generat ion An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input (with or without interrupt generation) or digital output.

5.1.2 Functional Description

Each port is associated to 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and some of them to an optional register: – Option Register (OR) Each I/O pin may be programmed using the corre-

sponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.

The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation

Section 4.1.3. The generic I/O block diagram is

shown on Figure 21.

5.1.2.1 Input Modes

The input configuration is sele cted by clearing the corresponding DDR register bit.

In this case, reading the DR register returns the digital value applied to the external I/O pin.

Different input modes can be selected by software through the OR register.

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is configured as an output.

ST72E331 ST72T331

Interrupt function

When an I/O is configured in Input with Interrupt, an event on thi s I/O can generat e an external Interrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous regi ster or in the interrupt register (where available).

Each pin can independently generate an Interrupt request.

Each external interrupt vector is linked t o a dedicated group of I/O port pins (see Interrupts section). If several input pins are configured as inputs to the same interrupt vector, their sign als are logically ANDed before entering the edge/level detection block. For this reason if one of the interrupt pins is tied low, it masks the other ones.

5.1.2.2 Output Mode

The pin is configured in output mode by setting the corresponding DDR register bit.

In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value.

Note: In this mode, the interrupt function is disabled.

5.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a pin, the alternate function is au tomatically selected. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).

When the signal is goi ng to an on-chip peripheral, the I/O pin ha s to be configured in i nput mode. In this case, the pin’s state is a lso digitally readable by addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex pected value at the input of the alternate peripheral input.

2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0).

Warning

vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.

: The alternate func tion m us t not be a cti-

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ST72E331 ST72T331

I/O PORTS (Cont’d)

5.1.2.4 Analog Alternate Function

When the pin is used as an ADC input the I/O must be configured as input, floating. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present o n the selected pin to the common ana log rail which i s c onnect ed to the ADC input.

It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it i s recommended not to have clocking pins located close t o a sele cted analog pin.

Warning

within the limits stated in the Absolute M aximum Ratings.

Figure 20. Recommended I/O State Transition Diagram

: The analog input voltage level mus t be

5.1.3 I/O Port Implementation

The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input (see Figure 21) or true open drain. Switching these I/O ports from one state to an other should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 20. Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.

INPUT

with interrupt

INPUT

no interrupt

OUTPUT

open-drain

OUTPUT push-pull

28/107

I/O PORTS (Cont’d)

ST72E331 ST72T331

Figure 21

. I/O Block Diagram

COMMON ANALOG RAIL

ALTERNATE INPUT

LATCH

DDR LATCH

DATA BUS

LATCH

(SEE TABLE BELOW)

OR SEL

DDR SEL

DR SEL

ALTERNATE OUTPUT

ALTERNATE ENABLE

M U X

ALTERNATE

1 M U

ENABLE

ALTERNATE ENABLE

PULL-UP CONDITION

ANALOG ENABLE

(ADC)

EE NOTE BELOW)

PULL-UP

ANALOG SWITCH

P-BUFFER

EE TABLE BELOW)

DIODE

(SEE TABLE BELOW)

GND

N-BUFFER

GND

PAD

CMOS

SCHMITT TRIGGER

EXTERNAL INTERRUPT

SOURCE (EIx)

POLARITY

SEL

FROM OTHER BITS

Table 10. Port Mode Configuration

Configuration Mode Pull-up P-buffer VDD Diode

Floating 0 0 1 Pull-up 1 0 1 Push-pull 0 1 1 True Open Drain not present not present not present Open Drain (logic level) 0 0 1

Legend: 0 - present, not activated 1 - present and activated

Notes:

– No OR Register on some ports (see register map). – ADC Switch on ports with analog alternate functions.

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ST72E331 ST72T331

I/O PORTS (Cont’d) Table 11. Port Configuration

Port Pin name

PA0:PA2

Port A

PA3 floating* pull-up with interrupt open-drain push-pull

Input (DDR = 0) Output (DDR = 1)

OR = 0 OR = 1 OR = 0 OR =1

floating* pull-up with interrupt open-drain push-pull

PA4:PA7 floating* open drain, high sink capability PB0:PB4 floating* pull-up with interrupt open-drain

Port B

PB5:PB7

floating* pull-up with interrupt open-drain

Port C PC0:PC7 floating* pull-up open-drain push-pull

PD0:PD5 floating* pull-up open-drain push-pull

Port D

PD6:PD7

floating* pull-up open-drain push-pull

PE0:PE1 floating* pull-up open-drain push-pull

Port E

PE4:PE7

floating*2) open drain, high sink capability3)

PF0:PF2 floating* pull-up with interrupt open-drain push-pull

Port F

PF4, PF6, PF7 floating* pull-up open-drain push-pull

Notes:

1. ST72T331N only

2. For OTP/EPROM version, when OR=0: floating & when OR=1: reserved

3. For OTP/EPROM version, when OR=0: open-drain, high sink capability & when OR=1: reserved

push-pull push-pull

* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).

Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must not be modified by the user otherwise a spurious interrupt may be generated.

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