ST ST72E121, ST72T121 User Manual

查询ST72121供应商

8-BIT MCU WITH 8 TO 16K OTP/EPROM,

384 TO 512 BYTES RAM, WDG, SCI, SPI AND 2 TIMERS

■ User Program Memory (OTP/EPROM):

8 to 16K byte s

■ Data RAM: 384 to 512 bytes including 256 bytes

of stack

■ Master Reset and Power-On Reset

■ Low Voltage Detector (LVD) Reset option

■ Run and Power Saving modes

■ 32 multifunctional bidirectional I/O lines:

– 9 programmable interrupt inputs
– 4 high sink outputs

– 13 alternate functions
–EMI filtering

■ Software or Hardware Watchdog (WDG)

■ Two 16-bit Timers, each featuring:

– 2 Input Captures and 2 Output Compares
– External Clock input (on Timer A)
– PWM and Pulse Generator modes

■ Synchronous Serial Peripheral Interface (SPI)

■ Asynchronous Serial Communications Interface

(SCI)

■ 8-bit Data Manipulation

■ 63 basic Instructions an d 17 main Addressing

Modes

■ 8 x 8 Unsigned Multiply Instruction

■ True Bit Manipulation

■ Complete Development Support on DOS/

WINDOWS

■ Full Software Package on DOS/WINDOWS

(C-Compiler, Cross-Assembler, Debugger)

Note: 1. One only of each on Tim er A.

TM

Real-Time Emulator

ST72E121

ST72T121

DATASHEET

PSDIP42

1)

CSDIP42W

TQFP44

TM

(See ordering information at the end of datasheet)

Device Summary

Features ST72T121J2 ST72T121J4

Program Memory - bytes 8K 16K
RAM (stack) - bytes 384 (256) 512 (256)
Peripherals Watchdog, Timers, SPI, SCI and optional Low Voltage Detector Reset
Operating Supply 3 to 5.5 V
CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max over 85°C

Temperature Range - 40°C to + 125°C

Package TQFP44 - SDIP42
OTP/EPROM Devices ST72T121J4/ST72E121J4

Note: ROM versions are supported by the ST72334/124 family. Important product differences must be taken into account.

Refer to the Preamble in the ST72334/124 Datasheet for more information.

Revision 1.9

May 2001 1/93

1

Table of Contents

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2.4 Low Voltage Detector Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.2 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.3 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.4 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.5 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4

5.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.1.3 I/O Port Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2.4 Hardware Watchdog Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

93

2/93

2

Table of Contents

5.3.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.6 Summary of Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.4 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.4.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.4.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.5.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.1.7 Relative Mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

7.4 RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.5 OSCILLATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.6 PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.1 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.2 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3/93

3

ST72E121 ST72T121

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72T121 HCMOS Microcontroller Unit
(MCU) is a member of the ST7 f amily. The de vic e
is based on an industry-standard 8-bit core and
features an enhanced instruction set . The device
is normally operated at a 16 MHz oscillator fre­quency. Under software control, the ST72T121
may be placed in either Wait, Slow or Halt modes,
thus reducing power consumption. Th e enhance d
instruction set and ad dressing modes afford real
programming potential. In addition to standard
8-bit data management, the ST72T121 features
true bit manipulation, 8x8 unsigned multiplication

Figure 1. ST72T121 Block Diagram

Internal

OSCIN

OSCOUT

RESET

OSC

CONTROL

AND L VD

8-BIT CO RE

ALU

PROGRAM

MEMORY

(8 - 16K Bytes)

CLOCK

and indirect addressing modes on the whole mem­ory. The device includes a low consumption and
fast sta r t on - c hip o s c illator, CP U , p r og ra m memo ­ry (OTP/EPROM vers ions), RAM, 32 I/O lines, a
Low Voltage Detector (LVD) and the following on­chip peripherals: industry standard synchronous
SPI and asynchronous SCI serial interfaces, digi t­al Watchdog, two independent 16-bit Timers, one
featuring an External Clock Input, and both featur­ing Pulse Generator capabilities, 2 Input Captures
and 2 Output Compares (only 1 Input Capture and
1 Output Compare on Timer A).

PORT A

PORT B

TIMER B

ADDRESS AND DATA BUS

PORT C

SPI

PA3 - > PA7

(5 bits)

PB0 - > PB4

(5 bits)

PC0 -> PC7

(8 bits)

PF0 -> PF 2,4,6,7

4/93

4

(6 bits)

PORT D

RAM

(384 - 512 Bytes)

PORT E

PORT F

SCI

TIMER A

V

DD

V

SS

POWER
SUPPLY

WATCHDOG

PD0 -> PD5

(6 bits)

PE0 -> PE1

(2 bits)

1.2 PIN DESCRIPTI ON
Figure 2. 44-Pin Thin QFP Package Pinout

PE0/TD0

PE1/RDI

PB0
PB1
PB2
PB3
PB4
PD0
PD1
PD2
PD3
PD4

44 43 42 41 40 39 38 37 36 35 34

1

(EI2)

2

(EI2)

3

(EI2)

4

(EI2)

5

(EI3)

6
7
8
9
10
11

12 13 14 15 16 17 18 19

PD5

DD_3

V

ST72E121 ST72T121

1)
PP

DD_2

SS_2

V

V

RESET

TEST/V

PA7

PA6

PA5

(EI0)

20 21 22

DD_0

V

31
30
29
28

V

PA4

33
32

27
26
25
24
23

SS_0

V

SS_1

V

DD_1

PA3
PC7/SS
PC6/SCK
PC5/MOSI
PC4/MISO
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B

OSCIN

OSCOUT

(EI1)

(EI1)

(EI1)

PF1

PF2

SS_3

V

1. VPP on EPROM/OTP only

Figure 3. 42-Pin Shrink DIP Package Pinout

PB4
PD0
PD1
PD2
PD3
PD4
PD5

V

DD_3

V

SS_3

CLKOUT/PF0

PF1

OCMP1_A/PF4

EXTCLK_A/PF7

PC0/OCMP2_B
PC1/OCMP1_B

PF2

ICAP1_A/PF6

PC2/ICAP2_B
PC3/ICAP1_B

PC4/MISO
PC5/MOSI

CLKOUT/PF0

1
2
3
4
5
6
7
8
9
10
11
12
13
14

15
16
17
18
19
20
21

(EI3)

(EI1)
(EI1)
(EI1)

ICAP1_A/PF6

OCMP1_A/PF4

EXTCLK_A/PF7

PB3

42

(EI2)
(EI2)
(EI2)
(EI2)

(EI0)

41
40
39
38
37
36
35
34
33
32
31
30
29

28
27
26
25
24
23
22

PB2
PB1
PB0
PE1/RDI
PE0/TD0

V

DD_2

OSCIN
OSCOUT

V

SS_2

RESET
TEST/V
PA7
PA6
PA5
PA4

V

SS_1

V

DD_1

PA3
PC7/SS
PC6/SCK

1)

PP

1. VPP on EPROM/OTP only

5/93

5

ST72E121 ST72T121

Table 1. ST72T121Jx Pin Desc ription

Pin n°

QFP44

Pin n°

SDIP42

Pin Name Type Description Remarks

1 38 PE1/RDI I/O Port E1 or SCI Receive Data In
2 39 PB0 I/O Port B0 Extern al Interrupt: EI2
3 40 PB1 I/O Port B1 Extern al Interrupt: EI2
4 41 PB2 I/O Port B2 Extern al Interrupt: EI2
5 42 PB3 I/O Port B3 Extern al Interrupt: EI2
6 1 PB4 I/O Port B4 External Int er ru pt: EI3
7 2 PD0 I/O Port D0
8 3 PD1 I/O Port D1

9 4 PD2 I/O Port D2
10 5 PD 3 I/O Port D3
11 6 PD 4 I/O Port D4
12 7 PD 5 I/O Port D5
13 8 V
14 9 V

DD_3
SS_3

S Main Power Supply

S Ground
15 10 PF0/CLKOUT I/O Port F0 or CPU Clock Output External Interrup t: EI1
16 11 PF1 I/O Port F1 External Interrupt: EI1
17 12 PF2 I/O Port F2 External Interrupt: EI1
18 13 PF4/OCMP1_A I/O Port F4 or Timer A Output Compare 1
19 14 PF6/ICAP1_A I/O Port F6 or Timer A Input Capture 1
20 15 PF7/EXTCLK_A I/O Port F7 or External Clock on Timer A
21 V
22 V

DD_0
SS_0

S Main power supply

S Ground
23 16 PC0/OCMP2_B I/O Port C0 or Timer B Output Compare 2
24 17 PC1/OCMP1_B I/O Port C1 or Timer B Output Compare 1
25 18 PC2/ICAP2_B I/O Port C2 or Timer B Input Capture 2
26 19 PC3/ICAP1_B I/O Port C3 or Timer B Input Capture 1
27 20 PC4/MISO I/O Port C4 or SPI Master In / Slave Out Data
28 21 PC5/MOSI I/O Port C5 or SPI Master Out / Sl ave In Data
29 22 PC6/SCK I/O Port C6 or SPI Serial Clock
30 23 PC7/SS

I/O Port C7 or SPI Slave Select
31 24 PA3 I/O Port A3 External Interrupt: EI0
32 25 V
33 26 V

DD_1
SS_1

S Main power supply

S Ground
34 27 PA4 I/O Port A4 High Sink
35 28 PA5 I/O Po rt A5 High Sink
36 29 PA6 I/O Po rt A6 High Sink
37 30 PA7 I/O Po rt A7 High Sink

38 31 TEST/V

PP

1)

39 32 RESET
40 33 V

SS_2

41 34 OSCOUT O
42 35 OSCIN I
43 36 V

DD_2

S

mode, this pin acts as the programming voltage
input V

PP.

I/O Bidirectional. Active low. Top priority non maskable interrupt.

S Ground

Input/Ou tput Oscill ator p in. The se pins conn ect a paral lel-re sonant cr ystal, or
an external source to the on-chip oscillator.

S Main power supply

Test mode pin. In the EPROM programming

This pin must be tied low
in user mode

44 37 PE0/TDO I/O Port E0 or SCI Transmit Dat a Out

Note 1: VPP on EPROM/OTP only.

6/93

6

1.3 EXTERNAL CONNECTIONS

ST72E121 ST72T121

The following figure shows the recom mended ex­ternal connections for the device.

The V

pin is only used for programming OTP

PP

and EPROM devices and must be tied to ground in
user mode.

The 10 nF and 0. 1 µF decoupling capacitors on
the power supply lines are a suggested EMC per­formance/cost tradeoff.

Figure 4. Recommended Extern al Connec tions

V

DD

Optional if Low Voltage
Detector (LVD) is used

EXTERNAL RESET CIRCUIT

10nF

+

V

DD

0.1µF

0.1µF

The external reset network is intended to protect
the device against parasitic resets, especially in
noisy environments.

Unused I/Os shoul d be t ied hi gh to av oid any un­necessary power consumption on floating lines.
An alternative solution is to program the unused
ports as inputs with pull-up.

V

PP

V

4.7K

DD

V

SS

RESET

0.1µF

See
Clocks
Section

Or configure unused I/O ports
by software as input with pull-up

V

10K

DD

OSCIN
OSCOUT

Unused I/O

7/93

7

ST72E121 ST72T121

1.4 MEMORY MAP
Figure 5. Program Memo ry Map

0000h

007Fh

0080h

01FFh

027Fh

0200h / 0280h

BFFFh
C000h

E000h

FFDFh

FFE0h

FFFFh

HW Registers

(see Table 3)

384 Bytes RAM

512 Bytes RAM

Reserved

16K Bytes

Program

8K Bytes

Memory

Program

Memory

Interrupt & Reset Vectors

(see Table 2)

0080h

Short Addressing

00FFh

0100h

01FFh

0080h

00FFh

0100h

RAM (zero page)

256 Bytes Stack/

16-bit Addressing RAM

Short Addressing

RAM (zero page)

256 Bytes Stack/

16-bit Addressing RAM

01FFh
0200h

027Fh

16-bit Addressing

RAM

Table 2. Interrupt Vector Map

Vector Address Description Remarks

FFE0-FFE1h
FFE2-FFE3h
FFE4-FFE5h
FFE6-FFE7h

FFE8-FFE9h
FFEA-FFEBh
FFEC-FFEDh

FFEE-FFEFh

FFF0-FFF1h

FFF2-FFF3h

FFF4-FFF5h

FFF6-FFF7h

FFF8-FFF9h

FFFA-FFFBh

FFFC-FFFDh

FFFE-FFFFh

TIMER B Interrupt Vector
TIMER A Interrupt Vector

External Interrupt Vector EI3 (PB4)
External Interrupt Vector EI2 (PB0:PB3)
External Interrupt Vector EI1 (PF0:PF2)

External Interrupt Vector EI0 (PA3)

TRAP (software) Interrupt Vector

Not Used
Not Used
Not Used

SCI Interrupt Vector

SPI interrupt vector

Not Used

Not Used
Not Used

RESET Vector

8/93

8

Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt

External Interrupt
External Interrupt
External Interrupt
External Interrupt

CPU Interrupt

Table 3. Hardware Register Mem ory Map

ST72E121 ST72T121

Address Block

0000h
0001h

Port A

0002h

Register

Label

PADR
PADDR
PAOR

Register Name

Data Register
Data Direction Register
Option Register

Reset

Status

00h
00h

00h
0003h Reserved Area (1 byte)
0004h
0005h
0006h

Port C

PCDR
PCDDR
PCOR

Data Register
Data Direction Register
Option Register

00h

00h

00h
0007h Reserved Area (1 byte)
0008h
0009h
000Ah

Port B

PBDR
PBDDR
PBOR

Data Register
Data Direction Register
Option Register

00h

00h

00h
000Bh Reserved Area (1 byte)
000Ch
000Dh
000Eh

Port E

PEDR
PEDDR
PEOR

Data Register
Data Direction Register
Option Register

00h

00h

0Ch
000Fh Reserved Area (1 byte)
0010h
0011h
0012h

Port D

PDDR
PDDDR
PDOR

Data Register
Data Direction Register
Option Register

00h
00h

00h
0013h Reserved Area (1 byte)
0014h
0015h
0016h
0017h to
001Fh

Port F

PFDR
PFDDR
PFOR

Data Register
Data Direction Register
Option Register

Reserved Area (9 bytes)

00h

00h

28h

0020h MISCR Miscellaneous Register 00h
0021h
0022h
0023h
0024h to
0029h
002Ah

002Bh
002Ch to
0030h

SPI

WDG

SPIDR
SPICR
SPISR

WDGCR
WDGSR

SPI Data I/O Register
SPI Control Register
SPI Status Register

Reserved Area (6 bytes)

Watchdog Control Register
Watchdog Status Register

Reserved Area (5 bytes)

xxh

xxh

00h

7Fh

00h

Remarks

R/W
R/W

1)

R/W

R/W
R/W
R/W

R/W
R/W

1)

R/W

R/W
R/W

1)

R/W

R/W
R/W

1)

R/W

R/W
R/W

1)

R/W

R/W
R/W
Read Only

R/W

3)

R/W

9/93

9

ST72E121 ST72T121

Address Block

0031h
0032h
0033h
0034h-0035h

0036h-0037h

0038h-0039h

Timer A

003Ah-003Bh

003Ch-003Dh

003Eh-003Fh

Register

Label

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Register Name

Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register

Reset

Status

00h

00h

xxh

xxh

xxh

80h

00h

FFh
FCh
FFh
FCh

xxh

xxh

80h

00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W

R/W
0040h Reserved Area (1 byte)
0041h
0042h
0043h
0044h-0045h

0046h-0047h

0048h-0049h

004Ah-004Bh

004Ch-004Dh

004Eh-004Fh

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h to
007Fh

Timer B

SCI

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved
SCI Extended Transmit Prescaler Register

Reserved Area (40 bytes)

00h
00h
xxh
xxh
xxh
80h

00h
FFh
FCh
FFh
FCh

xxh

xxh

80h

00h
C0h

xxh

00x----xb

xxh

00h

00h

---

00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
Reserved
R/W

Notes:

1. The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

2. External pin not available.

3. Not used in versions without Low Voltage Detector Reset.

Remarks

2)

2)

2)

2)

10/93

10

1.5 OPTION BYTE

ST72E121 ST72T121

The user has the option to select software watch­dog or hardware watchdog (see description in the
Watchdog chapter). When program ming EPROM
or OTP devices, this o ption is selected in a men u
by the user of the EPROM programmer before
burning the EPROM/O TP. The Option Byte is lo­cated in a non-user map. No address has to be
specified. The Option Byte is at FFh after UV eras­ure and must be properly programmed t o set de­sired options.

OPTBYTE

70

- - - - b3 b2 - WDG

Bit 7:4 = Not used

Bit 3 = Reserved, must be cleared.

Bit 2 = Reserved, must be s et on S T7 2T121 N de­vices and must be cleared on ST72T121J devices.

Bit 1 = Not used

Bit 0 = WDG

Watchdog disable

0: The Watchdog is enabled after reset (Hardware

Watchdog).

1: The Watchdog is not enabled after reset (Soft-

ware Watchdog).

11/93

11

ST72E121 ST72T121

2 CENTRAL PROCE SSI NG UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

2.2 MAIN FEATURES

■ 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low po wer modes

■ Maskable hardware interrupts

■ Non-maskable software interrupt

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specific instructions.

Figure 6. CPU Registers

70

RESET VALUE = XXh

70

RESET VALUE = XXh

70

RESET VALUE = XXh

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operan ds and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in­struction (PRE) to indicate that the following in­struction refers to the Y register.)

The Y register is not affected by the interrupt auto­matic procedures (not pushed to and popped from
the stack).

Program Cou nt er (P C )

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

ACCUMULA T OR

X INDEX REGISTER

Y INDEX REGISTER

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15

RESET VALUE = STACK HIGHER ADDRESS

12/93

PCH

RESET VALUE =

7

70

1C11HI NZ

1X11X1XX
70

8

PCL

12

0

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

ST72E121 ST72T121

CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)

Read/Write
Reset Value: 111x1xxx

70

111HINZC

The 8-bit Condition Code register c ontains the in­terrupt mask and four flags represent ative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Bit 4 = H

Half carry

.

This bit is set by hardware when a carry occurs be­tween bits 3 and 4 of t he ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines .

Bit 3 = I

Interrupt mask

.

This bit is set by hardware when entering in inter­rupt or by software to disable all interrup ts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in­structions and is tested by the JRM and JRNM in­structions.

Note: Interrupts requested while I is set are
latched and can be processed whe n I is cleared.
By default an interrupt routine is not in terruptable

because the I bi t is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur­rent interrupt routine.

Bit 2 = N

Negative

.

This bit is set and cleared by hardware. It is repre­sentative of the result sign of the last arithmeti c,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

Zero

Bit 1 = Z

.

This bit is set and cleared by hardware. This bit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

th

13/93

13

ST72E121 ST72T121

CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)

Read/Write
Reset Value: 01FFh

15 8

00000001

70

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).

Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in­struction (RSP), the Stack Pointer contains its re­set value (the SP7 to SP0 bits are set) which is the
stack higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, wi th­out indicating the s tack overflow. The previously
stored information is then o verwritten and there­fore lost. The stack also wraps in case of an under­flow.

The stack is used to save the retu rn address dur­ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location point ed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in­terrupt five locat ions i n the sta ck ar ea.

Figure 7. Stack Manipulation Example

@ 0100h

SP

@ 01FFh

CALL

Subroutine

SP

PCH
PCL

Stack Higher Address = 01FFh
Stack Lower Address =

Interrupt

Event

SP

CC

A

X
PCH
PCL
PCH
PCL

0100h

PUSH Y POP Y IRET

SP

Y

CC

A

X
PCH
PCL
PCH

PCL

CC

A

X
PCH
PCL
PCH

PCL

SP

PCH

PCL

RET

or RSP

SP

14/93

14

ST72E121 ST72T121

3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a crystal or ceramic reso­nator, or an external clock signal to drive the inter­nal oscillator. The internal clock (f

from the external oscillator frequency (f

) is derived

CPU

OSC).

The

external Oscillator clock is first divided by 2, and
an additional division factor of 2, 4, 8, or 16 can be
applied, in Slow Mode, to red uce th e f requency of
the f

; this clock signal is also routed to the on-

CPU

chip peripherals. The CPU clock signal consists of
a square wave with a duty cycle of 50%.

The internal oscillat or is designed to operate with
an AT-cut parallel resonant quartz crystal resona­tor in the frequency range specified for f

osc

. The

circuit shown in Figure 9 is recommended whe n
using a crystal, and Tab le 4 lists the recommend­ed capacitance and feedback resistance values.
The crystal and associated components should be
mounted as close as p ossible to the input pins i n
order to minimize output distortion and start-up
stabilisation time.

Use of an external CMOS oscillator is recom­mended when crystals outside the specified fre­quency ranges are to be used.

3.1.2 External Clock

An external clock may be applied to the OSCIN in­put with the OSCOUT pin not connected, as
shown on Figure 8.

Figure 8. External Clock Source Connections

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

Figure 9. Crystal/Ceramic Resonator

OSCIN OSCOUT

C

OSCIN

C

OSCOUT

Table 4 Recommended Values for 16 MHz

R

SMAX

Crystal Resonator (C

R

SMAX

C

OSCIN

C

OSCOUT

40

Ω

56pF 47pF 22pF
56pF 47pF 22pF

: Parasitic series resistance of the quartz

60

< 7pF)

0

Ω

150

Ω

crystal (upper limit).

: Parasitic shunt capacitance of the quartz crys-

C

0

tal (upper limit 7pF).

C

OSCOUT

, C

: Maximum total capacitance on

OSCIN

pins OSCIN and OSCOUT (the value includes the
external capacitance tied to the p in plus the para­sitic capacitance of the board and of the device).

Figure 10. Clock Prescaler Block Diagram

C

OSCIN

OSCIN

OSCOUT

%2 % 2, 4, 8, 16

C

OSCOUT

f

CPU

to CPU and
Peripherals

15/93

15

ST72E121 ST72T121

3.2 RESET

3.2.1 Introd uction

There are four sources of Reset:

– RESET

pin (external source)
– Power-O n Reset (Internal source)
– W ATCHDOG (Internal Source)
– Lo w Voltage Detection Reset (internal source)
The Reset Service Routine vector is located at ad-

dress FFFEh-FFFFh.

3.2.2 External Reset

The RESET

pin is both an input and an open-drain
output with integrated pull-up resi stor. When one
of the internal Reset sources is active, the Reset
pin is driven low for a duration of t

RESET

to reset

the whole application.

3.2.3 Reset Operation

The duration of the Reset state is a minimum of
4096 internal CPU Clock cycles. During the Reset
state, all I/Os take their reset value.

A Reset signal originating from an external source
must have a duration of at least t

PULSE

in order to

Figure 11. Reset Block Diagram

be recognised. This detection is asynchronous
and therefore the MCU can enter Reset state even
in Halt mode.

At the end of the Reset cycle, the MCU may be
held in the Reset state by an External Reset sig­nal. The RESET

has risen to a point where the MCU can oper-

V

DD

pin may thus be used to ens ure

ate correctly before the user program is run. Fol­lowing a Reset event, or after exiting Halt mode, a
4096 CPU Clock cycle delay period is initiated in
order to allow the oscillat or to stabilise and to en­sure that recovery has taken place from the Reset
state.

In the high state, the RESET
ternally to a pull-up resistor (R

pin is connected in-

). This resistor

ON

can be pulled low b y ex ternal circuitry to res et t he
device.

The RESET

pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is rec ommended to u se the exter­nal connections shown in Figure 4.

RESET

OSCILLATOR

SIGNAL

V

DD

R

ON

TO ST7

RESET

INTERN AL
RESET

COUNTER

POWER-ON RESE T
WATCHDOG RESET
LOW VOLTAGE DETECTOR RESET

16/93

16

RESET (Cont’d)

3.2.4 Low Voltage Detector Reset

The on-chip Low Voltage Detector (LVD) gener­ates a static reset when the supply voltage is be­low a reference value. The LVD functions both
during power-on as well as when the power supply
drops (brown-out). The reference value for a volt­age drop is lower than the reference value for pow­er-on in order to avoid a parasitic reset when the
MCU starts running and sinks current on the sup­ply (hysteresis).

The LVD Reset circuitry generates a reset when

is below:

V

DD

V
V

Provided the minimun V
the oscillator frequency) is above V
MCU can only be in two modes:

when VDD is rising

LVDUP
LVDDOWN

when VDD is falling

value (guaranteed for

DD

LVDDOWN

, the

- under full software control or

- in static safe reset
In this condition, secure operation is always en-

sured for the application without the need for ex­ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus perm itting the MCU to reset
other devices.

In noisy environments, the power supply may drop
for short periods and cause the Low Voltage De­tector to generate a Reset too frequen tly. In such

ST72E121 ST72T121

cases, it is recommended to us e devices without
the LVD Reset option and to rely on the watchdog
function to detect application runaway conditions.

Figure 12. Low Voltage Detector Reset Function

V

DD

Figure 13. Low Voltage Detector Reset Signal

V

DD

RESET

Note: See electrical characteristics for values of
V

LVDUP

LOW VOLTAGE

DETECTOR RESET

WATCHDOG

V

LVDUP

and V

LVDDOWN

FROM

RESET

RESET

V

LVDDOWN

Figure 14. Temporization timing diagram after an internal Reset

V

V

DD

Addresses

LVDUP

Temporiz ation (40 96 CP U clock cy cl es)

$FFFE

17/93

17

ST72E121 ST72T121

4 INTE RRUPTS

The ST7 core may be interrupted by one of two dif­ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non­maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 15.
The maskable interrupts must be enabled by
clearing the I bit in order to be serviced. However,
disabled interrupts may be latched and processed
when they are enabled (see external interrupts
subsection).

Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:

– No rmal processing is susp ended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– The I bit of the CC register is set to prevent addi-

tional interrupts.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address­es).

The interrupt service routine should finish with the
IRET instruction which c auses the conten ts o f the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I bit will be cleared a nd the main pro gram will
resume.

Priority Management

By default, a servicing interrupt cannot be inter­rupted because the I bit is set by hardware enter­ing in interrupt routine.

In the case when several inte rrupt s are simultane­ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map­ping Table).

Interrupts and Low Power Mode

All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi­cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the I nterrupt Mapping Ta­ble).

4.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc­tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on

Figure 15.

4.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the
PC register if the corresponding ext ernal interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.

The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).

An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.

If several input pins, connected to the same inter­rupt vector, are configured as interrupts, their sig­nals are logically ANDed and inverted before en­tering the edge/level detection block.

Caution: The type of sensitivity defined in the Mis­cellaneous or Interrupt register (if available) ap­plies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising­edge sensitivity.

4.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:

– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control

register.

If any of these two conditions is false, the interrupt
is latched and thus remains pending.

Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status

register or

– Access to the status register while the f lag i s set

followed by a read or write of an associated reg­ister.

Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en­abled) will therefore be lost if the clear sequence is
executed.

18/93

18

INTERRUPTS (Cont’d)
Figure 15. Inte rru pt P rocessing Flow c hart

FROM RESET

ST72E121 ST72T121

EXECUTE INSTRUCTION

RESTORE PC, X, A, CC FROM STACK

I BIT SET?

Y

FETCH NEXT INSTRUCTION

N

THIS CLEARS I BIT BY DEFAULT

IRET?

Y

N

N

INTER RUPT

PENDING?

Y

STACK PC, X, A, CC

SET I BIT

LOAD PC FROM I NTER RU PTVECTOR

19/93

19

ST72E121 ST72T121

Table 5. Int errupt Mapp in g

Source

Block

RESET Reset N/A N/A yes FFFEh-FFFFh
TRAP So ftware N/A N/A no FFFCh-FFFDh

EI0 Ext. Interrupt (Ports PA0:PA3) N/A N/A
EI1 Ext. Interrupt (Ports PF0:PF2) N/A N/A FFF4h-FFF5h
EI2 Ext. Interrupt (Ports PB0:PB3) N/A N/A FFF2h-FFF3h
EI3 Ext. Interrupt (Ports PB4:PB7) N/A N/A FFF0h-FFF1h

SPI

TIMER A

TIMER B

SCI

Transfer Complete
Mode Fault MODF
Input Capture 1
Output Compare 1 OCF1_A
Input Capture 2 ICF2_A
Output Compare 2 OCF2_A
Timer Overflow TOF_A
Input Capture 1
Output Compare 1 OCF1_B
Input Capture 2 ICF2_B
Output Compare 2 OCF2_B
Timer Overflow TOF_B
Transmit Buffer Empty
Transmit Complete TC
Receive Buffer Full RDRF
Idle Line Detect IDLE
Overrun OR

Description

NOT USED FFFAh-FFFBh
NOT USED FFF8h-FFF9h

NOT USED FFEEh-FFEFh

NOT USED FFE4h-FFE5h
NOT USED FFE2h-FFE3h
NOT USED FFE0h-FFE1h

Register

Label

SPISR

TASR

TBSR

SCISR

Flag

SPIF

ICF1_A

ICF1_B

TDRE

Exit

from

HALT

yes

no

Vector

Address

FFF6h-FFF7h

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

Priority

Order

Highest

Priority

Lowest
Priority

20/93

20

4.4 POWER SAVING MODES

4.4.1 Introd uct i on

There are three Power Saving modes. Slow Mode
is selected by setting the rele vant bits in the Mis­cellaneous register. Wait and Halt m odes may b e
entered using the WFI and HALT instructions.

ST72E121 ST72T121

Figure 16. WAIT Flow Chart

WFI INSTRUCTION

4.4.2 Slow Mode

In Slow mode, the oscillator frequency can be d i­vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.

4.4.3 Wait Mode

Wait mode places the M CU in a low power con­sumption mode by stopping the CPU. All peripher­als remain active. During Wait mode, th e I bit (CC
Register) is cleared, so as to enable all interrupts.
All other registers and memory remain unchanged.
The MCU w ill remain in Wait mode u ntil an Inte r­rupt or Reset occurs, whereupon the Program
Counter branches to the starting address of the In­terrupt or Reset Service Routine.
The MCU will remain in Wait mode until a Reset or
an Interrupt occurs, causing it to wake up.

Refer to Figure 16 below.

N

INTERRUPT

Y

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT

N

RESET

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK

I-BIT

4096 CPU CLOCK

CYCLES DELAY

ON

ON

OFF
CLEARED

Y

ON

ON

ON
SET

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT

FETCH RESET VECTOR

OR SERVICE INTERRUP T

Note: Before servicing an interrupt, the CC register is
pushed on the sta ck. The I-Bit is s et d uring the inte r­rupt routine and cleared when the CC register is
popped.

ON

ON

ON
SET

21/93

21

ST72E121 ST72T121

POWER SAVING MODES (Cont’d)

4.4.4 Halt Mode

The Halt mode is the MCU lowest power con­sumption mode. The Halt mode is entered by exe­cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used whe n
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en­tire MCU.

When entering Halt mode, the I bit in the CC Reg­ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.

The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer t o the I nterrupt M ap­ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues oper­ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.

Figure 17. HALT Flow Chart

HALT INSTRUCTION

WATCHDOG

RESET

N

EXTERNAL

INTERRUPT

Y

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT

N

1)

WDG

ENABLED?

N

OFF

OFF

OFF
CLEARED

RESET

Y

Y

1) or some specific interrupts

2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF

Note: Before servicing an interrupt, the CC register is
pushed on th e sta ck. The I-Bit is s et d uring the inte r­rupt routine and cleared when the CC register is
popped.

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK

I-BIT

4096 CPU CLOCK

CYCLES DELAY

OSCILLATOR
PERIPH. CLOCK

CPU CLOCK
I-BIT

FETCH RESET VECTOR

OR SERVICE INTERRUPT

ON

2)

OFF

ON
SET

ON

ON

ON
SET

22/93

22

4.5 MISCELLANEOUS REGISTER

ST72E121 ST72T121

The Miscellaneous register allows to select the
SLOW operating mode , the polarity of ex ternal i n­terrupt requests and to output the internal clock.

Register Address: 0020h — Read/Write
Reset Value: 0000 0000 (00h)

Bit 4:3 = PEI[1:0]

Polarity Opti o n s

These bits are set and cleared by so ftware. They
determine which event on EI0 and EI1 causes the
external interrupt according to Table 7.

External Interrupt EI1 and EI0

.

Table 7. EI0 and E I1 External Inte rrup t P o larity

70

PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS

Bit 7:6 = PEI[3:2]

Polarity Options

External Interrupt EI3 a nd EI2

.

These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the

Options

MODE PEI1 PEI0

Falling edge and low level

(Reset state)
Falling edge only 1 0
Rising edge only 0 1

Rising and falling edge 1 1

external interrupt according to Table 6.

Table 6. EI2 and EI3 External Interrupt Polarity

Options

MODE PEI3 PEI2

Falling edge and low level

(Reset state)

Falling edge only 1 0

Rising edge only 0 1

Rising and falling edge 1 1

00

Note: Any modification of one of these two bits re­sets the interrupt request related to this interrupt
vect or.

Bit 5 = MCO

Main Clock Out

This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PPF0 I/O port.
0 - PF0 is a general purpose I/O port.
1 - MCO alternate function (f

is output on PF0

CPU

pin).

Note: Any modification of one of these two bits re­sets the interrupt request related to t his interrupt
vector.l

Bit 2:1 = PSM[1:0]

Prescaler for Slow Mode.

These bits are set and cleared by so ftware. They
determine the CPU clock when the SMS bit is set
according to the following table.

Table 8. f

Bit 0 = SMS

Value in Slow Mode

CPU

f

Valu e

CPU

/ 4 0 0

f

OSC

f

/ 16 0 1

OSC

/ 8 1 0

f

OSC

/ 32 1 1

f

OSC

Slow Mode Select

This bit is set and cleared by software.

= f

0: Normal Mode - f

CPU

OSC

/ 2

(Reset state)

1: Slow Mode - the f

PSM[1:0] b its.

value is determined by the

CPU

00

PSM1 PSM 0

23/93

23

ST72E121 ST72T121

5 ON-CHIP PERIPHERALS

5.1 I/O PORTS

5.1.1 Introd uction

The I/O ports offer different functional modes:

– transfer of data through digital inputs and outputs
and for specific pins:
– an alog signal input (ADC)
– alterna te signal input/output for the on-chip pe-

ripherals.
– external interrupt generat ion
An I/O port is composed of up to 8 pins. Each pin

can be programmed independently as digital input
(with or without interrupt generation) or digital out­put.

5.1.2 Functional Description

Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and some of them to an optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-

sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same cor­respondence is used for the DR register.

The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation

Section 5.1.3. The generic I/O block diagram is

shown on Figure 19.

5.1.2.1 Input Modes

The input configuration is sele cted by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can be selected by software
through the OR register.

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con­figured as an output.

Interrupt function

When an I/O is configured in Input with Interrupt,
an event on thi s I/O can generat e an external In­terrupt request to the CPU. The interrupt polarity is
given independently according to the description
mentioned in the Miscellaneous regi ster or in the
interrupt register (where available).

Each pin can independently generate an Interrupt
request.

Each external interrupt vector is linked t o a dedi­cated group of I/O port pins (see Interrupts sec­tion). If several input pins are configured as inputs
to the same interrupt vector, their sign als are logi­cally ANDed before entering the edge/level detec­tion block. For this reason if one of the interrupt
pins is tied low, it masks the other ones.

5.1.2.2 Output Mode

The pin is configured in output mode by setting the
corresponding DDR register bit.

In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.

Note: In this mode, the interrupt function is disa­bled.

5.1.2.3 Digital Alternate Function

When an on-chip peripheral is configured to use a
pin, the alternate function is au tomatically select­ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).

When the signal is goi ng to an on-chip peripheral,
the I/O pin ha s to be configured in i nput mode. In
this case, the pin’s state is a lso digitally readable
by addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex ­pected value at the input of the alternate peripher­al input.

2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).

Warning

vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious in­terrupts.

: The alternate func tion m us t not be a cti-

24/93

24

I/O PORTS (Cont’d)

5.1.2.4 Analog Alternate Function

When the pin is used as an ADC input the I/O must
be configured as input, floating. The analog multi­plexer (controlled by the ADC registers) switches
the analog voltage present o n the selected pin to
the common ana log rail which i s c onnect ed to the
ADC input.

It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it i s recommended not to
have clocking pins located close t o a sele cted an­alog pin.

Warning

within the limits stated in the Absolute M aximum
Ratings.

Figure 18. Recommended I/O State Transition Diagram

: The analog input voltage level mus t be

5.1.3 I/O Port Implementation

The hardware implementation on each I/O port de­pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In­put (see Figure 19) or true open drain. Switching
these I/O ports from one state to an other should
be done in a sequence that prevents unwanted
side effects. Recommended safe transitions are il­lustrated in Figure 18. Other transitions are poten­tially risky and should be avoided, since they are
likely to present unwanted side-effects such as
spurious interrupt generation.

ST72E121 ST72T121

INPUT

with interrupt

INPUT

no interrupt

OUTPUT

open-drain

OUTPUT
push-pull

25/93

25

ST72E121 ST72T121

I/O PORTS (Cont’d)
Figure 19

. I/O Block Diagram

COMMON ANALOG RAIL

ALTERNATE INPUT

LATCH

DDR
LATCH

DATA BUS

LATCH

(SEE TABLE BELOW)

OR SEL

DDR SEL

DR SEL

ALTERNATE
OUTPUT

DR

OR

ALTERNATE ENABLE

1

M
U
X

0

ALTERNATE

1
M
U
X

0

ENABLE

ALTERNATE
ENABLE

PULL-UP
CONDITION

ANALOG ENABLE

(ADC)

(S

EE NOTE BELOW)

PULL-UP

ANALOG
SWITCH

V

DD

P-BUFFER

EE TABLE BELOW)

(S

V

DD

DIODE

(SEE TABLE BELOW)

GND

N-BUFFER

GND

PAD

CMOS

SCHMITT TRIGGER

EXTERNAL
INTERRUPT

SOURCE (EIx)

POLARITY

SEL

FROM
OTHER
BITS

Table 9. Port Mode Configuration

Configuration Mode Pull-up P-buffer VDD Diode

Floating 0 0 1
Pull-up 1 0 1
Push-pull 0 1 1
True Open Drain not present not present not present
Open Drain (logic level) 0 0 1

Legend:
0 - present, not activated
1 - present and activated

26/93

Notes:

– No OR Register on some ports (see register map).
– ADC Switch on ports with analog alternate functions.

26

I/O PORTS (Cont’d)
Table 10. Port Configuration

ST72E121 ST72T121

Port Pin name

PA3 floating* pull-up with interrupt open-drain push-pull

Port A

PA4:PA7 floating* true open drain, high sink capability
Port B PB0:PB4 floating* pull-up with interrupt open-drain push-pull
Port C PC0:PC7 floating* pull-up open-drain push-pull
Port D PD0:PD5 floating* pull-up open-drain push-pull
Port E PE0:PE1 floating* pull-up open-drain push-pull

PF0:PF2 floating* pull-up with interrupt open-drain push-pull

Port F

PF4, PF6, PF7 floating* pull-up open-drain push-pull

* Reset state (The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value).

Warning: All bits of the DDR register which correspond to unconnected I/Os must be left at their reset value. They must
not be modified by the user otherwise a spurious interrupt may be generated.

Input (DDR = 0) Output (DDR = 1)

OR = 0 OR = 1 OR = 0 OR =1

27/93

27

ST72E121 ST72T121

I/O PO R T S (Cont’d)

5.1.4 Register Description

5.1.4.1 Data registers

Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Port D Data Register (PDDR)
Port E Data Register (PEDR)
Port F Data Register (PFDR)
Read/Write

Reset Value: 0000 0000 (00h)

5.1.4.3 Option registers

Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PBOR)
Port D Option Register (PBOR)
Port E Option Register (PBOR)
Port F Option Register (PFOR)
Read/Write

Reset Value: see Register Memory Map Table 3

70

D7 D6 D5 D4 D3 D2 D1 D0

Bit 7:0 = D7-D0

Data Register 8 bits.

The DR register has a specific behaviour accord­ing to the selected input/output configuration. Writ­ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns ei ther the DR register latch
content (pin configured as output) or the digital val­ue applied to the I/O pin (pin configured as input).

70

O7 O6 O5 O4 O3 O2 O1 O0

Bit 7:0 = O7-O0

Option Register 8 bits.

The OR register allow to distinguish in input mode
if the interrupt c apability or t he floating conf igura­tion is selected.

In output mode it select push-pull or open-drain
capability.

Each bit is set and cleared by software.
Input mode:

5.1.4.2 Data direction registers

Port A D a t a D irection Regi s ter (PAD DR)
Port B D a t a D irection Regi s ter (PBD DR)
Port C Data Direction Register (PCDDR)

0: floating input
1: input pull-up with interrupt

Output mode:
0: open-drain configuration

1: push-pull configuration

Port D Data Direction Register (PDDDR)
Port E D a t a D irection Regi s ter (PED DR)
Port F Data Direction Register (PFDDR)
Read/Write

Reset Value: 0000 0000 (00h) (input mode)

70

DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0

Bit 7:0 = DD7-DD0

Data Direction Register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.

0: Input mode
1: Output mode

28/93

28