The ST72C171 is a member of the ST7 family of
Microcontrollers. All devices are based on a com mon industry-standard 8-bit core, featuring an enhanced instruction set.
The ST72C171 features single-voltage FLASH
memory with byte-by-byte In-Situ Programming
(ISP) capability.
Under software control, the device can be placed
in WAIT, SLOW, or HALT mode, reducing po wer
consumption when the application is in idle or
standby state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 un-
Figure 1. ST72C171 Block Diagram
OSCIN
OSCOUT
V
DD
V
RESET
V
DDA
V
SSA
SS
MULTIOSC
+
CLOCK FILTER
POWER
SUPPLY
CONTROL
8-BIT CORE
ALU
Internal
CLOCK
LVD
signed multiplication and indirect addressing
modes The device includes a low consumption
and fast start on-chip oscillator, CPU, Flash program memory, RAM, 22 I/O lines and the following
on-chip peripherals: Analog-to-Digital converter
(ADC) with 8 multiplexed a nalog inputs, Op-Amp
module, synchronous SPI serial interface, asyncronous serial interface (SCI), Watchdog timer, a
16-bit Timer featuring external Clock I nput, Pulse
Generator capabilities, 2 Input Captures and 2
Output Compares, an 8-bit Timer featuring external Clock Input, Pulse Generator Capabilities (2
channels), Autoreload and Input Capture.
The Op-Amp module adds on-chip analog features to the MCU, that usually require using external components.
PORT A
PWM/ART TIMER
16-BIT TIMER
ADDRESS AND DATA BUS
8-BIT ADC
OP-AMP
PORT C
PA[7:0]
OA3PIN*
OA1OUT
OA2OUT
OA3OUT*
PC[5:0]
4/152
*only on 34-pin devices
8K FLASH
MEMORY
256b-RAM
SCI
PORT B
SPI
WATCHDOG
PB[7:0]
1.2 PIN DESCRI PTION
Figure 2. 34-Pin SO Package Pinout
OA1 non-inverting input and/
or ART PWM0 resistive output
Notes:
1. In the interrupt input column, “eix” define s the associated external interrupt vect or. If the weak pull-up
column (wpu) is associated with the interrupt column (int), then the I/O configuration is p ull-up interrupt
input, else the configuration is floating interrupt input.
2. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see dedicated See “PIN DESCRIPTION” on page 5. for more details.
7/152
ST72C171
1.3 MEMORY MA P
1.3.1 Introd uct i on
Figure 4. Program Memory M ap
0000h
HW Registers
(see Table 1.3.2)
007Fh
0080h
256 bytes RAM
017Fh
0180h
0080h
00FFh
0100h
Short Addressing
RAM
Zero page
(128 Bytes)
Stack
(128 Bytes)
DFFFh
E000h
FFDFh
FFE0h
FFFFh
Reserved
8 Kbytes
FLASH
Interrupt & Reset Vectors
(see Table 4)
017Fh
8/152
ST72C171
1.3.2 Data Register
Table 2. Hardware Register Mem ory Map
Status Register
Data Register
Baud Rate Register
Control Register 1
Control Register 2
Reserved Area (27 Bytes)
Data Register
Control/Status Register
Reserved Area (2 Bytes)
PWM Duty Cycle Register 1
PWM Duty Cycle Register 0
PWM Control Register
Control/Status Register
Counter Access Register
Auto Reload Register
Input Capture Control Status Register
Input Capture Register 1
Reserved Area (4 Bytes)
Reset
Status
0C0h
0xxh
0Xxh
0xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Remarks
Read Only
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
10/152
2 FLASH PROGRAM MEMORY
ST72C171
2.1 INTRODUCTION
FLASH devices have a single voltage non-volatil e
FLASH memory that may be programmed in-situ
(or plugged in a programming t ool) on a byte-bybyte basis.
2.2 MAIN FEATURES
■ Remote In-Situ Programming (ISP) mode
■ Up to 16 bytes programmed in the same cycle
■ MTP memory (Multiple Time Programmable)
■ Read-out memory protection against piracy
2.3 STRUCTURAL ORGANISATION
The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.
The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes
the reset and interrupt user vector area .
2.4 IN-SITU PROGRAMMING (ISP) MODE
The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board.
This feature can be implem ented with a m inimum
number of added componen ts and bo ard area impact.
An example Remote ISP hardware interface to t he
standard ST7 programmi ng tool is described below. For more details on ISP programming, refer to
the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
– D ownl oad of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to pro-
gram the user program into the FLASH
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied
with power (V
and VSS) and a clock signal (os-
DD
cillator and application crystal circuit for example).
This mode needs five signals (plus the V
DD
signal
if necessary) to be connected to the program m ing
tool. This signals are:
– RESET
–V
: device reset
: device ground power supply
SS
– I S PCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin
must be connected to V
board through a pull-down resistor.
on the application
SS
If any of these pins are used for other purposes on
the application, a serial resist or has to be implemented to avoid a conflict if the other device forces
the signal level.
Figure 1 shows a typical hardware interface to a
standard ST7 programming t ool. For more det ails
on the pin locations, refer t o t he d ev ice pin out description.
Figure 5. Typi ca l Remote ISP Inter fa ce
HE10 CONNECTOR TYPE
TO PROGRAMMING TOOL
ISPSEL
DD
V
V
RESET
ISPCLK
ISPDATA
10KΩ
SS
APPLICATION
1
47KΩ
C
XTAL
L0
OSC2
ST7
C
L1
OSC1
2.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled throug h an option bit.
For FLASH devices, when this option is selected,
the program and data stored in the FLASH memory are protected against read-out piracy (including
a re-write protection). When this protection opt ion
is removed the entire FLASH program memory is
first automatically erased. However, the E
2
PROM
data memory (when available) can be protected
only with ROM devices.
11/152
ST72C171
3 CENTRAL PROCE SSI NG UNIT
3.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
3.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low po wer mo des
■ Maskable hardware interrupts
■ Non-maskable software interrupt
3.3 CPU REGISTERS
The 6 CPU registers shown in Figure 1 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 6. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Cou nt er (P C )
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULA T OR
X INDEX REGISTER
Y INDEX REGISTER
158
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACK HIGHER ADDRESS
12/152
PCH
RESET VALUE =
7
70
1C11HI NZ
1X11X1XX
70
8
PCL
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
70
111HINZC
The 8-bit Condition Code register c ontains the interrupt mask and four flags represent ative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
because the I bi t is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmeti c,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
Bit 4 = H
Half carry
.
tions.
This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines .
Bit 1 = Z
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Zero
.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I
Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all interrup ts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed whe n I is cleared.
.
Bit 0 = C
Carry/borrow.
This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
By default an interrupt routine is not in terruptable
ST72C171
th
13/152
ST72C171
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 7Fh
158
00000001
70
01SP5SP4SP3SP2SP1SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).
Since the stack is 128 bytes deep, the 10 most significant bits are forced by hardw are. Following a n
MCU Reset, or after a Reset Stack Pointe r instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, wi thout indicating the s tack overflow. The previously
stored information is then o verwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the retu rn address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location point ed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and reducing the number of external components. An
overview is shown in Figure 8.
To allow the integration of power management
features in the application, the Low Voltage Detector function (LVD) generates a static reset when
the V
supply voltage is below a V
DD
reference
IT-
value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.
The V
than the V
reference value for a voltage drop is lower
IT-
reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
V
is below:
DD
when VDD is rising
–V
IT+
when VDD is falling
–V
IT-
The LVD func t ion is illustrated in the Figure .
Provided the minimum V
the oscillator frequency) is above V
value (guaranteed for
DD
, the MCU
IT-
can only be in two modes:
– under fu ll software control
– in static safe reset
Figure 9. Low Voltage Detector vs Reset
V
DD
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus p ermitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to th e application requirement.
LVD application note
Application software can detect a reset caus ed by
the LVD by reading the LVDRF bit in the CRSR
register.
This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).
V
IT+
V
IT-
RESET
V
hyst
16/152
4.2.1 Reset Sequence Manager (RSM)
The RSM block of the CROSS Module includes
three RESET sources as shown in Figure 10:
■ EXTERNAL RESET SOURCE pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
Figure 10. Reset Block Diagram
ST72C171
These sources act on the RESET
ways kept low during the READ OPTION RESET
phase.
The RESET service routine vector is fixed at the
FFFEh-FFFFh addresses in the ST7 memory
map.
PIN and it is al-
V
DD
R
ON
f
CPU
RESET
The basic RESET s eque nc e cons i sts o f 4 p has es
as shown in Figure 11:
■ OPTION BYTE reading to configure the device
■ Delay depending on the RESET source
■ 4096 cpu clock cycle delay
■ RESET vector fetch
INTERNAL
RESET
COUNTER
WATCHDOG RESET
READ OPTION RESET
LVD RESET
The duration of the OPTION BY TE reading phase
) is defined in the Electrical Characteristics
(t
ROB
section. This first phase is initiated by an external
RESET
detection, or when V
pin pulse detection, a Watchdog RESET
rises up to V
DD
LVDopt
.
The 4096 cpu clock cycle delay al lows the osci llator to stabilise and to ensure that recovery has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 11. RESET Sequence Phases
READ
OPTION BYTE
t
ROB
DELAY
RESET
INTERNAL RESET
4096 CLOCK CYCL ES
FETCH
VECTOR
17/152
ST72C171
RESET SEQUENCE MANAGER (Cont’d)
4.2.2 Asynchronous External RES ET
The RESET
output with integrated R
pin is both an input and an open-drain
weak pull-up resistor.
ON
pin
This pull-up has no fixe d value but varies in accordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state
even in HALT mode.
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electr ical characteristics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 12).
Starting from the external RESET pulse recognition, the device RESET
is pulled low during at least t
pin acts as an output that
w(RSTL)out
.
Figure 12. RESET Sequences
4.2.3 Inte r na l Lo w Volta ge Detection RESET
Two differen t RESET sequences caused by the internal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pulled low when V
V
DD<VIT-
(falling edge) as shown in Figure 12.
The LVD filters spikes on V
pin acts as an output that is
DD<VIT+
(rising edge) or
larger than t
DD
g(VDD)
to
avoid parasitic resets.
4.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 12.
Starting from the Watchdog counter underflow, the
device RESET
low during at least t
pin acts as an output that is pulled
w(RSTL)out
.
V
V
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
IT+
IT-
V
DD
RUN
LVD
RESET
DELAY
RUN
t
w(RSTL)out
t
h(RSTL)in
SHORT EXT.
RESET
DELAY
LONG EXT.
RESET
RUNRUN
DELAY
t
h(RSTL)in
WATCHDOG UNDERFLOW
WATCHDOG
RESET
RUN
DELAY
t
w(RSTL)out
INTERNALRESET(4096 T
FETCH V ECTOR
CPU
)
18/152
ST72C171
4.2.4.1 Multi-Oscillator (MO)
The Mu lti-Oscillato r (MO) blo ck is the m ain clock
supplier of the ST7. To insure an optimum integration in the application, it is based on an external
clock source and six different selectable oscillators.
The main clock of t he ST 7 ca n be generated by 8
different sources comming from the MO block:
■ an External source
■ 4 Crystal or Ceramic resonator oscillators
■ 1 Extern al RC os cill ators
■ 1 Internal H igh Fre quency RC os c illator
Each oscillator is optimized for a given frequenc y
range in term of consumption and is selectable
through the Option Byte.
External Clock Source
The default Option Byte value selects the External
Clock in the MO block. In this mode, a clock signal
(square, sinus or triangle) with ~50% duty cycle
has to drive the OSCin pin while the OSCout pin is
tied to ground (see Figure 13).
Figure 13. MO Ex te rn a l Cl ock
ST7
OSCinO SCout
EXTERNAL
SOURCE
Crystal/Ceramic Oscillators
This family of oscillators allows a high accuracy on
the main clock of the ST7. The selection within the
list of 4 oscillators has to b e done by Option Byte
according to the res onator frequency in order to
reduce the consum ption. In this mode of the MO
block, the resonator and the load capacitors have
to be connected as shown in Figure 14 a nd have
to be mounted as close as possible to the oscillator pins in order to minimize output distortion and
start-up stabilization time.
These oscillators, when selected via the Option
Byte, are not stopped during the RESET phas e to
avoid losing time in the oscillator starting phase.
Figure 14. MO Crystal/Ceramic Resonator
OSCinOSCout
C
L0
ST7
LOAD
CAPACIT ORS
C
L1
19/152
ST72C171
MULTIOSCILLATO R (MO) (Cont’d)
External RC Oscillator
This oscillator allows a low cost solution on the
main clock of the ST7 using only an external resistor and an external capacitor (see Figure 15). T he
selection of the ex ternal RC oscillator has to be
done by Option Byte.
The frequency of the external RC oscillator is fixed
by the resistor and the capacitor values:
R
EX
ST7
N
. C
EX
~
f
OSC
The previous formula shows that in this MO mode,
the accuracy of the clock is directly linked to the
accuracy of the discrete components.
Figure 15. MO External RC
OSCinOSCout
Internal RC Oscillator
The Internal RC oscil lator mode is based on the
same principle as the External RC one including
the an on-chip resistor and capacitor. This mode is
the most cost effective one with the drawback of a
lower frequency accuracy. Its frequency is in the
range of several MHz.
In this mode, the two oscillator pins have to be tied
to ground as shown in Figure 16.
The selection of the internal RC oscillator has to
be done by Option Byte.
Figure 16. MO Internal RC
ST7
OSCinOSCout
R
EX
C
EX
20/152
4.3 CLOCK SECURITY SYSTEM (CSS)
ST72C171
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or
disabled by option byte.
4.3.1 Clock Filter Control
The clock filter is based on a clock frequency limitation function.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working p roperly (e.g. working at a harmonic fr equency of the resonator), the
current active oscillator clock can be totally filtered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the f iltering is s topped automatically and the oscillator supplies the ST7
clock.
4.3.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low frequency back-up clock source (see Figur e 17).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe o scillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
Automatically, the ST7 clock source switches back
from the saf e osc illa tor if the o rig inal clo ck s ourc e
reco ve rs .
Limitat io n det ect i on
The automatic safe oscillator selection is notif ied
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generat ed if the CSSIE bit has been previously set.
These two bits are described in the CRSR register
description.
4.3.3 Low Power Modes
Mode Description
WAIT
HALT
No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.
The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
4.3.4 Interrupts
The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event
CSS event detection
(safe oscillator activated as main clock)
Flag
Enable
Control
Bit
Event
CSSD CSSIEYesNo
Exit
from
Wait
Exit
from
Halt
1)
Note 1: This interrupt allows to exit from active-halt
mode if this mode is available in the MCU.
Figure 17. Clock Filter Function and Safe Oscillator Function
f
/2
OSC
f
FUNCTION
CPU
CLOCK FILTER
f
/2
OSC
f
SFOSC
FUNCTION
f
CPU
SAFE OSCILLATOR
21/152
ST72C171
4.3.5 Main Clock Controller (MCC)
The MCC block supplies the clock for the ST7
CPU and its internal peripherals. It allows the power saving modes such as SLOW mode to be managed by the application.
All functions are managed by the Miscellaneous
Register 1 (MISCR1).
The MCC block consists of:
– a program mab le CPU clock prescaler
– a clock-out signal to supply external devices
Figure 18. Main Clock Controller (MCC) Block Diagram
The prescaler allows the selection of the main
clock frequency and is controlled with three bits of
the MISCR1: CP1, CP0 and SMS.
The clock-out capability is an Alternate Function of
an I/O port pin, providing the f
put for driving external devices. It is controlled by
the MCO bit in the MISCR1 register.
clock as an out-
CPU
OSCIN
OSCOUT
MCO
MULTI-
OSCILLATOR
(MO)
PORT
ALTERNATE
FUNCTION
CLOCK
FILTER
(CF)
CPU CLOCK
TO CPU AND
PERIPHERALS
f
OSC
DIV 2
MCO
f
CPU
DIV 2, 4, 8, 16
CP1 CP0
MISCR1
SMS
22/152
4.4 CLOCK, RESET AND SUPPLY REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Read/Write
Reset Value: 000x 000x (00h)
70
---
LVD
RF
CSSIECSSDWDG
RF
Bit 7:5 = Reserved.
Bit 1 = CSSD
CSS Safe Osc. Detection
This bit indicates that the safe oscillator of the CSS
block has been selected. It is set by hardware and
cleared by reading the CRSR register when the
original o s cilla t o r r ec o v er s.
0: Safe oscillator is not active
1: Safe oscillator has been activated
Bit 0 = WDGRF
WatchDog Reset Flag
This bit indicates when set that the last Reset was
generated by the Watchdog peripheral. It is set by
hardware (watchdog reset) and cleared by soft-
Bit 4 = LV DRF
This bit indicates when set that the last Reset was
generated by the LVD block. It is set by hardware
(LVD reset) and cleared by software (writing zero)
or a Watchdog Reset. See WDGRF flag description for more details.
Bit 3 = Reserved.
LVD Reset Flag
ware (writing zero) or an LVD Reset.
Combined with the LVDRF flag information, the
flag description is given by the following table.
RESET SourcesLVDRFWDGRF
External RESET
Watchdog01
LVD1X
pin00
ST72C171
Bit 2 = CSSIE
CSS Interrupt Enable
This bit allows to enable the interrupt whe n a distrurbance is detected by the Cloc k Security System (CSSD bit set). It is set and cleared by software.
0: Clock Filter interrupt disable
1: Clock Filter interrupt enable
Table 3. Supply, Reset and Clock Register Map and Reset Values
Address
(Hex.)
0020h
0025h
Register
Label
MISCR
Reset Value
CRSR
Reset Value
76543210
PEI3
0
-
0
PEI2
0
-
0
MCO
0
-
0
PEI1
0
LVDRF
x
PEI0
CP1
0
-
0
0
CSSIE0CSSD0WDGRF
CP0
0
SMS
0
x
23/152
ST72C171
5 INTE RRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in F igure 19.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec tion) .
When an interrupt has to be serviced:
– No rmal processing is susp ended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which c auses the contents o f the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared a nd the main pro gram will
resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several inte rrupt s ar e simultaneously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the proc essor to
leave the HALT low power mode (refer to the “Exit
from HALT“ column in the I nterrupt Mapping Table).
5.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 19.
5.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding ext ernal interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically ANDed before entering the edge/
level detection block.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of risingedge sensitivity.
5.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status
register or
– Access to the status register while the f lag i s set
followed by a read or write of an associated register.
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is
executed.
24/152
INTERRUPTS (Cont’d)
Figure 19. Inte rru pt P rocessing Flow chart
To give a large measure of flexibility to the application in terms of power consumption, three main
power saving modes are implemented in the ST7
(see Figure 20).
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscillator status.
Figure 20. P ower Saving Mo de Transitions
High
RUN
SLOW
CPU
).
6.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (f
CPU
) to
the available supply voltage.
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
CPU
).
In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in norm al ope ra ting mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enterring the WAIT mode while the device is already in
SLOW mode.
Figure 21. SLOW Mode Clock Transitions
f
f
CPU
f
OSC
CP1:0
/2
/4f
OSC
0001
/8f
OSC
OSC
/2
WAIT
SLOW WAIT
HALT
Low
POWER CONSUMPTION
SMS
MISCR1
NORMALRUN MODE
NEW SLOW
FREQUENCY
REQUEST
REQUEST
27/152
ST72C171
POWER SAVING MODES (Cont’d)
6.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This pow er s av in g mode is s elected by ca llin g the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register are forced to 0, to enable all interrupts. All other registers and memory
remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occu rs, where upon the Program Counter branc hes to the starting
address of the interrupt or Reset service routine.
The MCU will r e main in W AIT mod e unt il a Rese t
or an Interrupt occurs, causing it to wake up.
Refer to Figure 22.
Figure 22. WAIT Mode Flow-chart
OSCILLATOR
WFI INSTRUCTION
N
INTERRUPT
Y
PERIPHERALS
CPU
I BIT
N
RESET
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT (s ee note)
ON
ON
OFF
0
ON
OFF
ON
1
ON
ON
ON
1
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared
when the CC register is popped.
28/152
POWER SAVING MODES (Cont’d)
ST72C171
6.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see Figure 24).
The MCU can exit HALT m ode on reception of either an specific interrupt (see Table 4, “Interrupt
Mapping,” on page 26) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes
operation by servicing the i nterrupt or by fetching
the reset vector which woke it up (see Figure 23).
When entering HALT mode, the I bit in the CC register is forced to 0 to e nable interrupt s. Therefore,
if an interrupt is pending, the MCU wakes immediately.
In the HALT mode the m ain oscillator is t urned o ff
causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by t he “WD GHA LT” option bit of the option byte. The HALT instruction
when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 11.1 OPTION BYTES for more details).
Figure 23. HALT Mode Timing Overview
HALTRUNRUN
HALT
INSTRUCTION
INTERRUPT
4096 CPU CYCLE
RESET
OR
DELAY
FETCH
VECTOR
Figure 24. HALT Mode Flow - chart
HALT INSTRUCTION
WDGHALT
1
WATCHDOG
RESET
N
INTERRUPT
Y
1)
ENABLE
0
OSCILLATOR
PERIPHERALS
CPU
I BIT
N
3)
OSCILLATOR
PERIPHERALS
CPU
I BIT
4096 CPU CLOCK CYCLE
OSCILLATOR
PERIPHERALS
CPU
I BIT
FETCH RESET VECTOR
OR SERVICE INTERRUPT
WATCHDO G
RESET
Y
DELAY
4)
DISABLE
OFF
2)
OFF
OFF
0
ON
OFF
ON
1
ON
ON
ON
1
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some spec ific interrupt s can exit the MCU
from HALT mode (su ch as ex ternal i nterrupt). Refer to Table 4, “Interrupt Mapping,” on page 26 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
29/152
ST72C171
7 ON-CHIP PERIPHERALS
7.1 I/O PORTS
7.1.1 Introd uct i on
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– analog signal input (ADC)
– alternate signal input/output for the on-chip pe-
ripherals.
– external interrupt generation
An I/O port is composed of up to 8 pins. Each pin
can be programmed independently as digital input
(with or without interrupt generation) or digital output.
7.1.2 Functional Description
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and some of them to an optional register (see reg-
ister description):
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR and OR registers: bit
X corresponding to pin X of the port. The same correspondence is used for the DR register.
The following description takes into account the
OR register, for specific ports which do not provide
this register refer to the I/O Port Implementation
Section 7.1.2.5. The generic I/O block diagram is
shown on Figure 26.
7.1.2.1 Input Modes
The input configuration is sele cted by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Notes:
1. All the inputs are triggered by a Schmitt trigger.
2. When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on thi s I/O can generat e an external Interrupt request to the CPU. The interrupt sensitivity is given independently according to the description mentioned in the Miscellaneous register or in
the interrupt register (where available).
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked t o a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
7.1.2.2 Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit.
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.
Note: In this mode, the interrupt function is disabled.
7.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is au tomatically selected. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is goi ng to an on-chip peripheral,
the I/O pin ha s to be configured in i nput mode. In
this case, the pin’s state is a lso digitally readable
by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unex pected value at the input of the alternate peripheral input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Warning
vated as long as the pin is configured as input with
interrupt, in order to avoid generating spurious interrupts.
: The alternate func tion m us t not be a cti-
30/152
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