ST ST72774, ST72754, ST72734 User Manual

ST72734

ST72774/ST72754/ST72734

8-BIT USB MCU FOR MONITORS, WITH UP TO 60K OTP, 1K RAM, ADC, TIMER, SYNC, TMU, PWM/BRM, H/W DDC & I2C

■User ROM/OTP/EPROM: up to 60 Kbytes

■Data RAM: up to 1 Kbytes (256 bytes stack)

■8 MHz Internal Clock Frequency in fast mode,

4 MHz in normal mode

■Run and Wait CPU modes

■System protection against illegal address jumps and illegal opcode execution

■Sync Processor for Mode Recognition, power management and composite video blanking, clamping and free-running frequency generation

–Corrector mode

–Analyzer mode

■USB (Universal Serial Bus) for monitor function 1

–Three endpoints

–Integrated 3.3V voltage regulator

–Transceiver

–Suspend and Resume operations

■Timing Measurement Unit (TMU) for autoposition and autosize 1

■Fast I2C Single Master Interface

■DDC Bus Interface with:

–DDC1/2B protocol implemented in hardware

–Programmable DDC CI modes

–Enhanced DDC (EDDC) address decoding

■31 I/O lines

Device Summary

PSDIP42	TQFP44
	10 x 10

■2 lines programmable as interrupt inputs

■16-bit timer with 2 input captures and 2 output compare functions

■8-bit Analog to Digital Converter with 4 channels on port B

■8 10-bit PWM/BRM Digital to Analog outputs

■Master Reset and Low Voltage Detector (LVD) reset

■Programmable Watchdog for system reliability

■Fully static operation

■63 basic instructions / 17 main addressing modes

■8x8 unsigned multiply instruction

■True bit manipulation

■Complete development support on PC/DOSWindows: Real-Time Emulator, EPROM Programming Board and Gang Programmer

■Full software package (assembler, linker, C- compiler, source level debugger)

	Features	ST72(T/E)774(J/S)9		ST72(T)754(J/S)9	ST72774(J/S)7	ST72754(J/S)7	ST72(T/E)734J6
	Program Memory -		60K		48K		32K
	Bytes
	RAM (stack) - Bytes			1K (256)			512 (256)
		USB		No USB	USB	No USB	No USB
	Peripherals						ADC4, I2C,LVD,
		ADC 3, 16-bit timer, I2C, DDC, TMU,Sync, PWM, LVD, Watchdog					DDC,Sync,
							16-bit timer,
							PWM, Watchdog
	Operating Supply			4.0V to 5.5V supply operating range
	Oscillator Frequency				12 or 24 MHz
	Operating Temperature				0 to +70°C
	Package			CSDIP42 or PSDIP42 or TQFP44			PSDIP42
							CSDIP42
	(1) On some devices only, refer to Device Summary; (2) Contact Sales office for availability
	(3) 8-bit ±2 LSB A/D converter ; (4) 8-bit ±4 LSB A/D converter.
	October 2003						1/144

1

				Table of Contents
1 GENERAL DESCRIPTION . . . .				. . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . 6
1.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . 6
1.2		PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . . 7
1.3		MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 10
1.4		EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 14
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 15
2.1		INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 15
2.2		MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 15
2.3		CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 15
3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES . . . . . . .					. . . . . . . . . . . . . . . . . . . . 18
3.1		CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 18
		3.1.1	General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 18
		3.1.2	Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 19
		3.1.3	External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 19
3.2		RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 20
		3.2.1	LVD and Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 20
		3.2.2	External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 20
		3.2.3	Illegal Address Detection . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 20
		3.2.4	Illegal Opcode Detection . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 20
3.3		INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 22
3.4		POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 25
		3.4.1 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 25
		3.4.2 HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 25
3.5		MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 26
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 27
4.1		I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 27
		4.1.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 27
		4.1.2	Common Functional Description . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 28
		4.1.3	Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 29
		4.1.4	Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 31
		4.1.5	Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 33
		4.1.6	Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 35
		4.1.7	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 38
4.2		WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 39
		4.2.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 39
		4.2.2	Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 39
		4.2.3	Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 39
		4.2.4	Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 40
		4.2.5	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 40
4.3		16-BIT TIMER (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 41
		4.3.1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 41
		4.3.2	Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 41
		4.3.3	Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 41
		4.3.4	Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . . . . . . . . . . . . . . 51
4.4		SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . . . . . . . . 56

2/144

2

ST72774/ST727754/ST72734

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4.3 Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.4 Input Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.5 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.6 Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.4.7 Output Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.4.8 Analyzer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.9 Corrector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.4.10Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.5 TIMING MEASUREMENT UNIT (TMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.6.5 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.7.4 Functional Description (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.7.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.8 DDC INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.2 DDC Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.8.3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4.8.4 I2C BUS Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.8.5 DDC Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.8.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.9 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4.9.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

4.10 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.10.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.10.2Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.10.3Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.10.4Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.10.5Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.10.6Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

5 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	126
5.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	126

3/144

ST72774/ST727754/ST72734

5.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.4 Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.5 Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.1.6 Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.1.7 Relative mode (Direct, Indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

5.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.1 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.2 AC/DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	139
7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	139
8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	141

8.1 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4/144

ST72774/ST727754/ST72734

Revision follow-up

Changes applied since version 4.0

Version 4.0	March 2001
	Page 1:Addition of 72T774 (32KOTP).
	Addition of 60K/48K ROM for ST72754
	Deletion of table “ device summary”, replaced with cross reference to table 36 on page 147.
	page 13 - addition of section 1.4. external connections
Version 4.1	July 2001
	Initial format reapplied, text and related figures in the same page.
	Table “Device summary” reinserted in cover page and updated.
	Update of table 36: ordering information (p143)
Version 4.2	July 2001
	Cover - addition of feature about system protection added,
	table for device summary: addition of stack values
	page 9 - figure 3: replaced 1KByte with 512 Bytes + notes about opcode fetch and HALT
	mode
	page 10 - table: CR replaced by WDGCR
	TIM replaced with Timer and WDG replaced with Watchdog
	page 115 - EDF register: addition of “read from RAM”, EDE: few changes
	page 135 - Note 1 replaced, note 2 added SUSpend mode limitation..
	Whole document: all mentions of HALT mode either deleted or rewritten.
Version 4.3	October 2001
	p140, chapter 8, section 8.1-
	code for unused bytes ( FFh) replaced with 9Dh (opcode for NOP)
	page 141update of table 36 “Ordering information”
	page 142 - list of available devices updated
	page 114 - DDC DCR register: bit 5 = 1, text “or read from RAM” deleted
Version 4.3	November 2001
	page 10, one adddress corrected in the figure 3 “memory map”: 0400h
	page 14: addition of mandatory 1K resistor (text and figure)

5/144

3

ST72774/ST727754/ST72734

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST72774, ST72754 and ST72734 are HCMOS microcontroller units (MCU) from the ST727x4 family with dedicated peripherals for Monitor applications.

They are based around an industry standard 8-bit core and offer an enhanced instruction set. The processor runs with an external clock at 12 or 24 MHz with a 5V supply. Due to the fully static design of this device, operation down to DC is possible. Under software control the ST727x4 can be placed in WAIT mode thus reducing power consumption. The HALT mode is no longer available.

The enhanced instruction set and addressing modes afford real programming potential. Illegal opcodes are patched and lead to a reset.

Figure 1. ST727x4 Block Diagram

In addition to standard 8-bit data management the ST7 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.

The device includes an on-chip oscillator, CPU, System protection against illegal address jumps, Sync Processor for video timing & Vfback analysis, up to 60K Program Memory, up to 1K RAM, USB/ DMA, a Timing Measurement Unit, I/O, a timer with 2 input captures and 2 output compares, a 4- channel Analog to Digital Converter, DDC, I2C Single Master, Watchdog Reset, and eight 10-bit PWM/BRM outputs for analog DC control of external functions.

	Up to 60K Bytes		PORT A
	ROM/OTP/EPROM
			PORT B
	Up to 1K Bytes		ADC
	RAM
			I2C
			DDC
		ADDRESS	USB
RESET	CONTROL
	8-BIT CORE	AND	PORT D
	ALU
		DATA
		BUS	TIMER
	WATCHDOG
			SYNC
OSCIN	Mode		PROCESSOR
OSCOUT	OSC :3 Selection
VDD			TMU
	POWER SUPPLY
VSS			PORT C

DAC (PWM)

PA0/OCMP1

PA1

PA2/VSYNCI2

PA3-PA6

PA7/BLANKOUT

PB6-PB7/AIN2-AIN3/PWM1-PWM2 PB4-PB5/AIN0-AIN1

PB3/SDAI

PB2/SCLI

PB1/SDAD

PB0/SCLD

USBVCC

USBDP

USBDM

PD0/VSYNCO

PD1/HSYNCO

PD2/CSYNCI

PD3/ITA/VFBACK

PD4/ITB

PD5/HFBACK

PD6/CLAMPOUT

VSYNCI

HSYNCI

PC0/HSYNCDIV

PC1/AV

PC2-PC7/PWM3-PWM8

6/144

3

ST72774/ST727754/ST72734

1.2 PIN DESCRIPTION

Figure 2. 44-pin TQFP and 42-Pin SDIP Package Pinouts

PC5 / PWM6

44 PWM7 / PC6 1

PWM8 / PC7 2 PWM2 / AIN3 / PB7 3 PWM1 / AIN2 / PB6 4 AIN1 / PB5 5 AIN0 / PB4 6 NC 7

VDD 8 USBVCC 9

USBDM 10

USBDP 11 12

Vss

HSYNCDIV / PC0

AV / PC1

PWM3 / PC2

PWM4 / PC3

PWM5 / PC4

PWM6 / PC5

PWM7 / PC6

PWM8 / PC7

PWM2 / AIN3 / PB7

PWM1 / AIN2 / PB6

AIN1 / PB5

AIN0 / PB4

VDD

USBVCC

USBDM

USBDP

VSS

HSYNCI

VSYNCI

VSYNCO / PD0

HSYNCO / PD1

	/PC4PWM5		/PC3PWM4	/PC2PWM3	/PC1AV /PC0HSYNCDIV /PA0OCMP1	TEST/ V	RESET	PA1		PA2/VSYNCI2
						PP
43 42				41 40 39 38 37 36 35 34								PA3
									33
									32			PA4
									31			PA5
									30			PA6
									29			OSCIN
									28			OSCOUT
									27			PA7 / BLANKOUT
									26			PB3 / SDAI
									25			PB2 / SCLI
									24			PB1 / SDAD
									23			NC
13 14 15 16 17 18 19 20 21 22
	HSYNCI		VSYNCI	VSYNCO / PD0	HSYNCO / PD1 CSYNCI / PD2 VFBACK / ITA /PD3	ITB / PD4	HFBACK / PD5	CLAMPOUT / PD6		SCLD / PB0
										PA0 / OCMP1
		1					42
			2				41			TEST / VPP
		3					40				RESET
			4				39				PA1
		5					38				PA2/VSYNCI2
			6				37				PA3
		7					36				PA4
			8				35				PA5
		9					34				PA6
			10				33				OSCIN
		11					32				OSCOUT
			12				31				PA7 / BLANKOUT
		13					30				PB3 / SDAI
			14				29				PB2 / SCLI
		15					28				PB1 / SDAD
			16				27				PB0 / SCLD
		17					26				PD6 / CLAMPOUT
			18				25				PD5 / HFBACK
		19					24				PD4 / ITB
			20				23				PD3 / ITA / VFBACK
		21					22				PD2 / CSYNCI

NC = Not connected

7/144

3

ST72774/ST727754/ST72734

PIN DESCRIPTION (Cont’d)

RESET: Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non maskable interrupt. This pin is switched low when the Watchdog has triggered or VDD is low. It can be used to reset external peripherals.

OSCIN/OSCOUT: Input/Output Oscillator pin. These pins connect a parallel-resonant crystal, or an external source to the on-chip oscillator.

Table 1. ST727x4 Pin Description

TEST/VPP: Input. EPROM programming voltage. This pin must be held low during normal operating modes.

VDD: Power supply voltage (4.0V-5.5V)

VSS: Digital Ground.

Alternate Functions: several pins of the I/O ports assume software programmable alternate functions as shown in the pin description

Pin No.

	TQFP44	SDIP42	Pin Name	Type	Description	Remarks
	39	1	PC0/HSYNCDIV	I/O	Port C0 or HSYNCDIV output (HSYNCO divided by 2)
	40	2	PC1/AV	I/O	Port C1 or “Active Video” input
	41	3	PC2/PWM3	I/O	Port C2 or 10-bit PWM/BRM output 3
	42	4	PC3/PWM4	I/O	Port C3 or 10-bit PWM/BRM output 4
	43	5	PC4/PWM5	I/O	Port C4 or 10-bit PWM/BRM output5	For analog controls,
	44	6	PC5/PWM6	I/O	Port C5 or 10-bit PWM/BRM output 6	after external filtering
	1	7	PC6/PWM7	I/O	Port C6 or 10-bit PWM/BRM output 7
	2	8	PC7/PWM8	I/O	Port C7 or 10-bit PWM/BRM output 8
	3	9	PB7/AIN3/PWM2	I/O	Port B7 or ADC analog input 3 or 10-bit PWM/BRM
					output 2
	4	10	PB6/AIN2/PWM1	I/O	Port B6 or ADC analog input 2 or 10-bit PWM/BRM
					output 1
	5	11	PB5/AIN1	I/O	Port B5 or ADC analog input 1
	6	12	PB4/AIN0	I/O	Port B4 or ADC analog input 0
	8	13	VDD	S	Supply (4.0V - 5.5V)
	9	14	USBVCC	S	USB power supply (output 3.3V +/- 10%)
	10	15	USBDM	I/O	USB bidirectional data	Must be tied to ground
						for devices without
	11	16	USBDP	I/O	USB bidirectional data
						USB peripheral
	12	17	VSS	S	Ground 0V
	13	18	HSYNCI	I	SYNC horizontal synchronisation input	TTL levels
	14	19	VSYNCI	I	SYNC vertical synchronisation input	Refer to Figure 16
	15	20	PD0/VSYNCO	I/O	Port D0 or SYNC vertical synchronisation output
	16	21	PD1/HSYNCO	I/O	Port D1 or SYNC horizontal synchronisation output
	17	22	PD2/CSYNCI	I/O	Port D2 or SYNC composite synchronisation input	TTL levels with pull-up
						(SYNC input)
	8/144

3

ST72774/ST727754/ST72734

Pin No.

TQFP44	SDIP42		Pin Name		Type	Description	Remarks
						Port D3 or SYNC Vertical flyback input or interrupt fall-	Refer to Figure 16 and
18	23		PD3/VFBACK/ITA		I/O		Table 11 Port D De-
						ing edge detector input A	scription
19	24		PD4/ITB		I/O	Port D4 or Interrupt falling edge detector input B	Refer to Table 11 Port
							D Description
20	25		PD5/HFBACK		I/O	Port D5 or SYNC horizontal flyback input	TTL levels with pull-up
							(SYNC input)
21	26		PD6/CLAMPOUT		I/O	Port D6 or SYNC clamping/ MOIRE output
22	27		PB0/SCLD		I/O	Port B0 or DDC serial clock
24	28		PB1/SDAD		I/O	Port B1 or DDC serial data
25	29		PB2/SCLI		I/O	Port B2 or I2C serial clock
26	30		PB3/SDAI		I/O	Port B3 or I2C serial data
27	31		PA7/BLANKOUT		I/O	Port A7 or SYNC blanking output
28	32		OSCOUT		O	Oscillator output
29	33		OSCIN		I	Oscillator input
30	34		PA6		I/O	Port A6
31	35		PA5		I/O	Port A5
32	36		PA4		I/O	Port A4
33	37		PA3		I/O	Port A3
34	38		PA2/VSYNCI2		I/O	Port A2 or SYNC vertical synchronisation input 2	DDC1 only
35	39		PA1		I/O	Port A1
36	40				I/O	Reset pin	Active low
			RESET
37	41		TEST/VPP		S	Test mode pin or EPROM programming voltage. This
						pin should be tied low in user mode.
38	42		PA0/OCMP1		I/O	Port A0 or TIMER output compare 1

9/144

ST72774/ST727754/ST72734

1.3 MEMORY MAP

Figure 3. Memory Map

0000h	0060h
HW Registers		Short Addressing
(see Table 2)		RAM (zero page)
005Fh
0060h	0100h
512 Bytes RAM		256 Bytes Stack/
		16-bit Addressing RAM
1 Kbyte RAM	01FFh
03FFh
0400h
	0060h	Short Addressing
Reserved		RAM (zero page)
	0100h
0FFFh		256 Bytes Stack/
1000h		16-bit Addressing RAM
60 Kbytes ROM/EPROM
4000h	01FFh
48 Kbytes	0200h	16-bit Addressing
8000h		RAM
32 Kbytes
FFDFh
FFE0h		512 Bytes
Interrupt & Reset Vectors *
(see Table 3)	03FFh
FFFFh
any opcode fetch in those areas is considered as illegal and generates a reset
(*) this block only contains addresses of interrupts and reset routines, no opcode is run from this block

10/144

				ST72774/ST727754/ST72734
	MEMORY MAP (Cont’d)
	Table 2. Hardware Register Memory Map
	Address	Block	Register Label	Register Name	Reset	Remarks
					Status
	0000h		PADR	Port A Data Register	00h	R/W
	0001h		PADDR	Port A Data Direction Register	00h	R/W
	0002h		PBDR	Port B Data Register	00h	R/W
	0003h		PBDDR	Port B Data Direction Register	00h	R/W
	0004h		PCDR	Port C Data Register	00h	R/W
	0005h		PCDDR	Port C Data Direction Register	00h	R/W
	0006h		PDDR	Port D Data Register	00h	R/W
	0007h		PDDDR	Port D Data Direction Register	00h	R/W
	0008h	Watchdog	WDGCR	Watchdog Control Register	7Fh	R/W
	0009h		MISCR	Miscellaneous Register	10h	R/W
	000Ah	ADC	ADCDR	ADC Data Register	00h	Read only
	000Bh		ADCCSR	ADC Control Status register	00h	R/W
	000Ch	DDC1/2B	DDCDCR	DDC1/2B Control Register	00h	R/W
	000Dh		DDCAHR	DDC1/2B Address Pointer High Register	xxh	R/W
	000Eh		TMUCSR	TMU control status register	FCh	R/W
	000Fh	TMU	TMUT1CR	TMU T1 counter register	FFh	Read only
	00010h		TMUT2CR	TMU T2 counter register	FFh	Read only
	0011h		TIMCR2	Timer Control Register 2	00h	R/W
	0012h		TIMCR1	Timer Control Register 1	00h	R/W
	0013h		TIMSR	Timer Status Register	00h	Read only
	0014h		TIMIC1HR	Timer Input Capture 1 High Register	xxh	Read only
	0015h		TIMIC1LR	Timer Input Capture 1 Low Register	xxh	Read only
	0016h		TIMOC1HR	Timer Output Compare 1 High Register	80h	R/W
	0017h		TIMOC1LR	Timer Output Compare 1 Low Register	00h	R/W
	0018h	Timer	TIMCHR	Timer Counter High Register	FFh	Read only
	0019h		TIMCLR	Timer Counter Low Register	FCh	R/W
	001Ah		TIMACHR	Timer Alternate Counter High Register	FFh	Read only
	001Bh		TIMACLR	Timer Alternate Counter Low Register	FCh	R/W
	001Ch		TIMIC2HR	Timer Input Capture 2 High Register	xxh	Read only
	001Dh		TIMIC2LR	Timer Input Capture 2 Low Register	xxh	Read only
	001Eh		TIMOC2HR	Timer Output Compare 2 High Register	80h	R/W
	001Fh		TIMOC2LR	Timer Output Compare 2 Low Register	00h	R/W
	0020h
	to			Reserved Area (5 bytes)
	0024h

11/144

ST72774/ST727754/ST72734

	Address	Block	Register Label	Register Name	Reset	Remarks
					Status
	0025h		USBPIDR	USB PID Register	XXh	Read only
					XXh
	0026h		USBDMAR	USB DMA address Register		R/W
					XXh
	0027h		USBIDR	USB Interrupt/DMA Register		R/W
					00h
	0028h		USBISTR	USB Interrupt Status Register		R/W
					00h
	0029h		USBIMR	USB Interrupt Mask Register		R/W
					xxxx 0110
	002Ah		USBCTLR	USB Control Register		R/W
					00h
	002Bh	USB	USBDADDR	USB Device Address Register		R/W
					0000 xxxx
	002Ch		USBEP0RA	USB Endpoint 0 Register A		R/W
					80h
	002Dh		USBEP0RB	USB Endpoint 0 Register B		R/W
					0000 xxxx
	002Eh		USBEP1RA	USB Endpoint 1 Register A		R/W
					0000
	002Fh		USBEP1RB	USB Endpoint 1 Register B		R/W
					xxxx0000
	0030h		USBEP2RA	USB Endpoint 2 Register A		R/W
					0000
	0031h		USBEP2RB	USB Endpoint2 Register B		R/W
					xxxx0000
	0032h		PWM1		80h	R/W
	0033h		BRM21		00h	R/W
	0034h		PWM2		80h	R/W
	0035h		PWM3		80h	R/W
	0036h		BRM43		00h	R/W
	0037h		PWM4		80h	R/W
	0038h	PWM	PWM5	10 BIT PWM / BRM	80h	R/W
	0039h		BRM65		00h	R/W
	003Ah		PWM6		80h	R/W
	003Bh		PWM7		80h	R/W
	003Ch		BRM87		00h	R/W
	003Dh		PWM8		80h	R/W
	003Eh		PWMCR	PWM output enable register	00h	R/W
	003Fh			Reserved Area (1 byte)
	0040h		SYNCCFGR	SYNC Configuration Register	00h	R/W
	0041h		SYNCMCR	SYNC Multiplexer Register	20h	R/W
	0042h		SYNCCCR	SYNC Counter Register	00h	R/W
	0043h	SYNC	SYNCPOLR	SYNC Polarity Register	08h	R/W
	0044h		SYNCLATR	SYNC Latch Register	00h	R/W
	0045h		SYNCHGENR	SYNC H Sync Generator Register	00h	R/W
	0046h		SYNCVGENR	SYNC V Sync Generator Register	00h	R/W
	0047h		SYNCENR	SYNC Processor Enable Register	C3h	R/W
	0048h
	to			Reserved Area (8 bytes)
	004Fh

12/144

ST72774/ST727754/ST72734

	Address	Block	Register Label	Register Name	Reset	Remarks
					Status
	0050h		DDCCR	DDC/CI Control Register	00h	R/W
	0051h		DDCSR1	DDC/CI Status Register 1	00h	Read only
	0052h		DDCSR2	DDC/CI Status Register 2	00h	Read only
	0053h	DDC/CI		Reserved
	0054h		DDCOAR	DDC/CI (7 Bits) Slave address Register	00h	R/W
	0055h			Reserved
	0056h		DDCDR	DDC/CI Data Register	00h	R/W
	0057h			Reserved Area (2 bytes)
	0058h
	0059h		I2CDR	I2C Data Register	00h	R/W
	005Ah			Reserved
	005Bh			Reserved
	005Ch	I2C	I2CCCR	I2C Clock Control Register	00h	R/W
	005Dh		I2CSR2	I2C Status Register 2	00h	Read only
	005Eh		I2CSR1	I2C Status Register 1	00h	Read only
	005Fh		I2CCR	I2C Control Register	00h	R/W

Table 3. Interrupt Vector Map

Vector Address	Description	Remarks
FFE0-FFE1h	Not used
FFE2-FFE3h	Not used
FFE4-FFE5h	Not used
FFE6-FFE7h	USB interrupt vector	Internal Interrupts
FFE8-FFE9h	Not used
FFEA-FFEBh	I2C interrupt vector
FFEC-FFEDh	Timer Overflow interrupt vector
FFEE-FFEFh	Timer Output Compare interrupt vector
FFF0-FFF1h	Timer Input Capture interrupt vector
FFF2-FFF3h	ITA falling edge interrupt vector	External Interrupts
FFF4-FFF5h	ITB falling edge interrupt vector
FFF6-FFF7h	DDC1/2B interrupt vector	Internal Interrupt
FFF8-FFF9h	DDC/CI interrupt vector
FFFA-FFFBh	USB End Suspend interrupt vector
FFFC-FFFDh	TRAP (software) interrupt vector	CPU Interrupt
FFFE-FFFFh	RESET vector

13/144

ST72774/ST727754/ST72734

1.4 External connections

The following figure shows the recommended external connections for the device.

The VPP pin is only used for programming OTP and EPROM devices and must be tied to ground in user mode.

The 10 nF and 0.1 µF decoupling capacitors on the power supply lines are a suggested EMC performance/cost tradeoff.

Figure 4. Recommended External Connections

The external reset network (including the mandatory 1K serial resistor) is intended to protect the device against parasitic resets, especially in noisy environments.

Unused I/Os should be tied high to avoid any unnecessary power consumption on floating lines. An alternative solution is to program the unused ports as inputs with pull-up.

VDD

VPP

VDD

+

0.1µF

10nF

VSS

VDD

4.7K

0.1µF

EXTERNAL RESET CIRCUIT RESET 0.1µF 1K

See			OSCIN
Clocks
Section			OSCOUT

Or configure unused I/O ports by software as input with pull-up

VDD	10K
	Unused I/O

14/144

ST72774/ST727754/ST72734

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

2.2 MAIN FEATURES

■63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes

■Two 8-bit index registers

■16-bit stack pointer

■Low power modes

■Maskable hardware interrupts

■Non-maskable software interrupt

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

Program Counter (PC)

2.3 CPU REGISTERS

The 6 CPU registers shown in Figure 5 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

Figure 5. CPU Registers

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

										7										0
																							ACCUMULATOR
												RESET VALUE = XXh
										7										0
																							X INDEX REGISTER
											RESET VALUE = XXh
										7										0
																							Y INDEX REGISTER
											RESET VALUE = XXh
					PCH			8			7				PCL					0			PROGRAM COUNTER
	15
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
										7										0
												1	1	1	H	I	N		Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1									1	1	X	1	X		X	X
		15						8												0			STACK POINTER
											7
RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

15/144

ST72774/ST727754/ST72734

CPU REGISTERS (Cont’d)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	1	H	I	N	Z	C

The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 3 = I Interrupt mask.

This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.

0:Interrupts are enabled.

1:Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.

Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you

16/144

enter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative (i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

ST72774/ST727754/ST72734

CPU REGISTERS (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 6).

Since the stack is 256 bytes deep, the most significant byte is forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 6.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

Figure 6. Stack Manipulation Example

CALL

Interrupt

PUSH Y

POP Y

IRET

RET

Subroutine

event

or RSP

@ 0100h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

17/144

ST72774/ST727754/ST72734

3 CLOCKS, RESET, INTERRUPTS & LOW POWER MODES

3.1 CLOCK SYSTEM

3.1.1 General Description

The MCU accepts either a crystal or an external clock signal to drive the internal oscillator. The internal clock (CPU CLK running at fCPU) is derived from the external oscillator frequency

(fOSC), which is divided by 3. Depending on the external quartz or clock frequency, a division factor

of 2 is optionally added to generate the 12 MHz clock for the Sync Processor (clamp function) as

Figure 7. Clock divider chain

shown in Figure 7 and a second divider by 2 for the 6MHz USB clock.

The CPU clock is used also as clock for the ST727x4 peripherals.

Note: In the Sync processor, an additional divider by two is added in fast mode (same external timing for this peripheral).

%3 fCPU: 4 or 8 MHz (CPU and peripherals)

OSC	%2		12 MHz
			(Sync processor Clampout signal)
12 MHz		FAST
or
24MHz		%2	6 MHz
			(USB)
			12 MHz
			or
			24MHz
			(TMU)
FAST=1 for 24MHZ oscillator		FAST=0 for 12 MHz oscillator

18/144

4

ST72774/ST727754/ST72734

CLOCK SYSTEM (Cont’d)

3.1.2 Crystal Resonator

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for fosc. The circuit shown in Figure 8 is recommended when using a crystal, and Table 4, “. Recommended Crystal Values,” on page 19 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilization time.

Figure 8. Crystal/Ceramic Resonator

CRYSTAL CLOCK

OSCIN OSCOUT

CL1

CL2

1M* *Recommended for oscillator stability

Table 4. Recommended Crystal Values

24 Mhz				Unit
RSMAX	70	25	20	Ohms
CL1	22	47	56	pf
CL2	22	47	56	pf

Legend:

CL1, CL2 = Maximum total capacitance on pins OSCIN and OSCOUT (the value includes the external capacitance tied to the pin plus the parasitic capacitance of the board and of the device).

RSMAX = Maximum series parasitic resistance of the quartz allowed.

Note: The tables are relative to the quartz crystal only (not ceramic resonator).

3.1.3 External Clock

An external clock should be applied to the OSCIN input with the OSCOUT pin not connected as shown in Figure 9. The Crystal clock specifications do not apply when using an external clock input. The equivalent specification of the external clock source should be used.

Figure 9. External Clock Source Connections

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

19/144

ST72774/ST727754/ST72734

3.2 RESET

The Reset procedure is used to provide an orderly software start-up or to quit low power modes.

Five conditions generate a reset:

■LVD,

■watchdog,

■external pulse at the RESET pin,

■illegal address,

■illegal opcode.

A reset causes the reset vector to be fetched from addresses FFFEh and FFFFh in order to be loaded into the PC and with program execution starting from this point.

An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes active.

3.2.1 LVD and Watchdog Reset

The Low Voltage Detector (LVD) generates a reset

when VDD is below VTRH when VDD is rising or VTRL when VDD is falling (refer to Figure 11). This circuitry

is active only when VDD is above VTRM.

During LVD Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

When a watchdog reset occurs, the RESET pin is pulled low permitting the MCU to reset other devices as when Power on/off (Figure 10).

3.2.2 External Reset

The external reset is an active low input signal applied to the RESET pin of the MCU.

As shown in Figure 12, the RESET signal must remain low for 1000ns.

An internal Schmitt trigger at the RESET pin is provided to improve noise immunity.

3.2.3 Illegal Address Detection

An opcode fetch from an illegal address (refer to Figure 3) generates an illegal address reset. Program execution at those addresses is forbidden (especially to protect page 0 registers against spurious accesses).

3.2.4 Illegal Opcode Detection

Illegal instructions corresponding to no valid opcode generate a reset. Refer to ST7 Programming Manual.

Table 5. List of sections affected by RESET and WAIT (Refer to 3.6 for Wait Mode)

Section	RESET	WAIT
Fast bit of the miscellaneous register set to one (24 MHz as external clock)	X
Timer Prescaler reset to zero	X
Timer Counter set to FFFCh	X
All Timer enable bits set to 0 (disabled)	X
Data Direction Registers set to 0 (as Inputs)	X
Set Stack Pointer to 01FFh	X
Force Internal Address Bus to restart vector FFFEh, FFFFh	X
Set Interrupt Mask Bit (I-Bit, CC) to 1 (Interrupt disable)	X
Set Interrupt Mask Bit (I-Bit, CC) to 0 (Interrupt enable)		X
Reset WAIT latch	X
Disable Oscillator (for 4096 cycles)	X
Set Timer Clock to 0	X
Watchdog counter reset	X
Watchdog register reset	X
Port data registers reset	X
Other on-chip peripherals: registers reset	X

20/144

ST72774/ST727754/ST72734

RESET (Cont’d)

Figure 10. Low Voltage Detector Functional Diagram

Figure 11. LVD Reset Signal Output

	RESPOF	VTRH	VTRL
VDD	LVD	VTRM
	RESET		VTRM
	INTERNAL	VDD
	RESET
	FROM	RESET
	WATCHDOG
	RESET

Note: See electrical characteristics section for values of VTRH, VTRL and VTRM

Figure 12. Reset Timing Diagram

tDDR
VDD
OSCIN
tOXOV
fCPU
PC	FFFE	FFFF
	tRL
RESET	4096 CPU
	CLOCK
	CYCLES
WATCHDOG RESET	DELAY
Note: Refer to Electrical Characteristics for values of tDDR, tOXOV and tRL

21/144

ST72774/ST727754/ST72734

3.3 INTERRUPTS

The ST727x4 may be interrupted by one of two different methods: maskable hardware interrupts as listed in Table 6 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 13.

The maskable interrupts must be enabled in order to be serviced. However, disabled interrupts can be latched and processed when they are enabled. When an interrupt has to be serviced, the PC, X, A and CC registers are saved onto the stack and the interrupt mask (I bit of the Condition Code Register) is set to prevent additional interrupts. The Y register is not automatically saved.

The PC is then loaded with the interrupt vector of the interrupt to service and the interrupt service routine runs (refer to Table 6, “Interrupt Mapping,” on page 24 for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the registers to be recovered from the stack and normal processing to resume. Note that the I bit is then cleared if and only if the corresponding bit stored in the stack is zero.

Though many interrupts can be simultaneously pending, a priority order is defined (see Table 6, “Interrupt Mapping,” on page 24). The RESET pin has the highest priority.

If the I bit is set, only the TRAP interrupt is enabled. All interrupts allow the processor to leave the WAIT low power mode.

Software Interrupt. The software interrupt is the executable instruction TRAP. The interrupt is recognized when the TRAP instruction is executed, regardless of the state of the I bit. When the interrupt is recognized, it is serviced according to the flowchart on Figure 13.

ITA, ITB interrupts. The ITA (PD3), ITB (PD4), pins can generate an interrupt when a falling edge occurs on these pins, if these interrupts are enabled with the ITAITE, ITBITE bits respectively in the miscellaneous register and the I bit of the CC register is reset. When an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. It is then serviced according to the flowchart on Figure 13. Software in the ITA or ITB service routine must reset the cause of this interrupt by clearing the ITALAT, ITBLAT or ITAITE, ITBITE bits in the miscellaneous register.

Peripheral Interrupts. Different peripheral interrupt flags are able to cause an interrupt when they are active if both the I bit of the CC register is reset and if the corresponding enable bit is set. If either of these conditions is false, the interrupt is latched and thus remains pending.

The interrupt flags are located in the status register. The Enable bits are in the control register. When an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. It is then serviced according to the flowchart on Figure 13.

The general sequence for clearing an interrupt is an access to the status register while the flag is set followed by a read or write of an associated register. Note that the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.

22/144

ST72774/ST727754/ST72734

INTERRUPTS (Cont’d)

Figure 13. Interrupt Processing Flowchart

FROM RESET

	Y
	TRAP?
	N
	N
	I BIT SET?
	Y
		N
	FETCH NEXT INSTRUCTION	INTERRUPT?
		Y
	N
EXECUTE INSTRUCTION	IRET?	STACK PC, X, A, CC
		SET I BIT
	Y	LOAD PC FROM INTERRUPT VECTOR

RESTORE PC, X, A, CC FROM STACK

THIS CLEARS I BIT BY DEFAULT

VR01172D

23/144

ST72774/ST727754/ST72734

INTERRUPTS (Cont’d)

Table 6. Interrupt Mapping

	Source	Description	Register	Flag	Maskable	Vector Address	Priority
	Block		Label		by I-bit		Order
	RESET	Reset	N/A	N/A	no	FFFEh-FFFFh	Highest
	TRAP	Software	N/A	N/A	no	FFFCh-FFFDh	Priority
	USB	End Suspend Interrupt	USBISTR	ESUSP	yes	FFFAh-FFFBh
	DDC/CI	DDC/CI Interrupt	DDCSR1	**	yes	FFF8h-FFF9h
			DDCSR2
	DDC1/2B	DDC1/2B Interrupt	DDCDCR	EDF	yes	FFF6h-FFF7h
	Port D bit 4	External Interrupt ITB	MISCR	ITBLAT	yes	FFF4h-FFF5h
	Port D bit 3	External Interrupt ITA		ITALAT	yes	FFF2h-FFF3h
		Input Capture 1		ICF1	yes	FFF0h-FFF1h
		Input Capture 2		ICF2
	TIM		TIMSR
		Output Compare 1		OCF1	yes	FFEEh-FFEFh
		Output Compare 2		OCF2
		Timer Overflow		TOF	yes	FFECh-FFEDh
	I2C	I2C Peripheral Inter-	I2CSR1	**	yes	FFEAh-FFEBh
		rupts	I2CSR2
							Lowest
	USB	USB Interrupt	USBISTR	**	yes	FFE6h-FFE7h
							Priority

** Many flags can cause an interrupt, see peripheral interrupt status register description.

24/144

ST72774/ST727754/ST72734

3.4 POWER SAVING MODES

3.4.1 WAIT Mode

This mode is a low power consumption mode. The WFI instruction places the MCU in WAIT mode: The internal clock remains active but all CPU processing is stopped; however, all other peripherals are still running.

Note: In WAIT mode, DMA accesses (DDC, USB) are possible.

During WAIT mode, the I bit in the condition code register is cleared to enable all interrupts, which causes the MCU to exit WAIT mode, causes the corresponding interrupt vector to be fetched, the interrupt routine to be executed and normal processing to resume. A reset causes the program counter to fetch the reset vector and processing starts as for a normal reset.

Table 5 gives a list of the different sections affected by the low power modes. For detailed information on a particular device, please refer to the corresponding part.

3.4.2 HALT Mode

The HALT mode is the MCU lowest power consumption mode. Meanwhile, the HALT mode also stops the oscillator stage completely which is the most critical condition in CRT monitors.

For this reason, the HALT mode has been disabled and its associated HALT instruction is now considered as illegal and will generate a reset.

Figure 14. WAIT Flow Chart

WFI INSTRUCTION

OSCILLATOR		ON
PERIPH. CLOCK		ON
CPU CLOCK		OFF
I-BIT		CLEARED

N

RESET

N

Y

INTERRUPT

Y
		OSCILLATOR		ON
		PERIPH. CLOCK		ON
		CPU CLOCK		ON
		I-BIT		SET
		IF RESET
		4096 CPU CLOCK
		CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is pushed on the stack. The I-Bit is set during the interrupt routine and cleared when the CC register is popped.

25/144

ST72774/ST727754/ST72734

3.5 MISCELLANEOUS REGISTER

MISCELLANEOUS REGISTER (MISCR)

Address: 0009h — Read/Write

Reset Value: 0001 0000 (10h)

7			0
VSYNC	FLY_S	HSYNC	FAST	ITBLAT	ITALAT	ITBITE	ITAITE
SEL	YN	DIVEN

Bit 7= VSYNCSEL DDC1 VSYNC Selection.

This bit is set and cleared by software. It is used to choose the VSYNC signal in DDC1 mode.

0:VSYNCI selected

1:VSYNCI2 selected

Note: VSYNCI 2 is only available for the DDC cell, not for the SYNC processor cell.

Bit 6= FLY_SYN Flyback or Synchro Switch.

This bit is set and cleared by software. It is used to choose the signals the Timing Measurement Unit (TMU) will analyse.

0:horizontal and vertical synchro outputs analysis

1:horizontal and vertical Flyback inputs analysis

Bit 5= HSYNCDIVEN HSYNCDIV Enable.

This bit is set and cleared by software. It is used to enable the output of the HSYNCO output on PC0.

0: HSYNCDIV disabled 1:HSYNCDIV enabled

Bit 4= FAST Fast Mode.

This bit is set and cleared by software. It is used to select the external clock frequency. If the external clock frequency is 12 MHz, this bit must be at 0, else if the external frequency is 24 MHz, this bit must be at 1.

Bit 3= ITBLAT Falling Edge Detector Latch.

This bit is set by hardware when a falling edge occurs on pin ITB/PD4 in Port D. An interrupt is generated if ITBITE=1and the I bit in the CC register = 0. It is cleared by software.

0:No falling edge detected on ITB

1:Falling edge detected on ITB

Bit 2= ITALAT Falling Edge Detector Latch.

This bit is set by hardware when a falling edge occurs on pin ITA/PD3 in Port D. An interrupt is generated if ITAITE=1and the I bit in the CC register = 0. It is cleared by software.

0:No falling edge detected on ITA

1:Falling edge detected on ITA

Bit 1= ITBITE ITB Interrupt Enable. This bit is set and cleared by software.

0:ITB interrupt disabled

1:ITB interrupt enabled

Bit 0= ITAITE ITA Interrupt Enable. This bit is set and cleared by software.

0:ITA interrupt disabled

1:ITA interrupt enabled

26/144

ST72774/ST727754/ST72734

4 ON-CHIP PERIPHERALS

4.1 I/O PORTS

4.1.1 Introduction

The I/O ports allow the transfer of data through digital inputs and outputs, and, for specific pins, the input of analog signals or the Input/Output of alternate signals for on-chip peripherals (DDC, TIMER...).

Figure 15. I/O Pin Typical Circuit

Each pin can be programmed independently as digital input or digital output. Each pin can be an analog input when an analog switch is connected to the Analog to Digital Converter (ADC).

Rail		Data Bus
Common Analog

Alternate enable

Alternate 1

VDD

output

0

P-BUFFER

(if required)

DR

PULL-UP (if required)

latch

Alternate enable

DDR latch

PAD

Analog Enable (ADC)

DDR SEL					Analog
					Switch (if required)

N-BUFFER

DR SEL

1

Alternate Enable

VSS

0

Digital Enable

Alternate Input

Note: This is the typical I/O pin configuration. For cost optimization, each port is customized with a specific configuration.

27/144

5

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Table 7. I/O Pin Functions

DDR	MODE
0	Input
1	Output

4.1.2 Common Functional Description

Each port pin of the I/O Ports can be individually configured under software control as either input or output.

Each bit of a Data Direction Register (DDR) corresponds to an I/O pin of the associated port. This corresponding bit must be set to configure its associated pin as output and must be cleared to configure its associated pin as input (Table 7, “. I/O Pin Functions,” on page 28). The Data Direction Registers can be read and written.

The typical I/O circuit is shown on Figure 15. Any write to an I/O port updates the port data register even if it is configured as input. Any read of an I/O port returns either the data latched in the port data register (pins configured as output) or the value of the I/O pins (pins configured as input).

Remark: when an I/O pin does not exist inside an I/O port, the returned value is a logic one (pin configured as input).

At reset, all DDR registers are cleared, which configures all port’s I/Os as inputs with or without pull-ups (see Table 8 to Table 12 I/O Ports Register Map). The Data Registers (DR) are also initialized at reset.

4.1.2.1 Input mode

When DDR=0, the corresponding I/O is configured in Input mode.

In this case, the output buffer is switched off, the state of the I/O is readable through the Data Register address, but the I/O state comes directly

from the CMOS Schmitt Trigger output and not from the Data Register output.

4.1.2.2 Output mode

When DDR=1, the corresponding I/O is configured in Output mode.

In this case, the output buffer is activated according to the Data Register’s content.

A read operation is directly performed from the Data Register output.

4.1.2.3 Analog input

Each I/O can be used as analog input by adding an analog switch driven by the ADC.

The I/O must be configured in Input before using it as analog input.

The CMOS Schmitt trigger is OFF and the analog value directly input through an analog switch to the Analog to Digital Converter, when the analog channel is selected by the ADC.

4.1.2.4 Alternate mode

A signal coming from a on-chip peripheral can be output on the I/O.

In this case, the I/O is automatically configured in output mode.

This must be controlled directly by the peripheral with a signal coming from the peripheral which enables the alternate signal to be output.

A signal coming from an I/O can be input in a onchip peripheral.

Before using an I/O as Alternate Input, it must be configured in Input mode (DDR=0). So both Alternate Input configuration and I/O Input configuration are the same (with or without pullup). The signal to be input in the peripheral is taken after the CMOS Schmitt trigger or TTL Schmitt trigger for SYNC.

The I/O state is readable as in Input mode by addressing the corresponding I/O Data Register.

28/144

ST72774/ST727754/ST72734

Figure 16. Input Structure for SYNC signals

TTL trigger

Pin								HSYNCI Input
								VSYNCI Input
(no pull-up)
						I/O logic (if existing)

VDD

pull-up

TTL trigger

Pin

CSYNCI Input

HFBACK Input

VFBACK Input

I/O logic (if existing)

4.1.3 Port A

PA7 and PA[2:0] can be defined as Input lines (with pull-up) or as Push-pull Outputs.

Table 8. Port A Description

PA [6:3] can be defined as Input lines (without pullup) or as Output Open drain lines.

PA7 and PA[2:0] can be defined as Input lines (with pull-up) or as Push-pull Outputs.

PA [6:3] can be defined as Input lines (without pullup) or as Output Open drain lines.

	PORT A		I / O	Alternate Function
		Input*	Output	Signal	Condition
	PA0	With pull-up	push-pull	OCMP1	OC1E =1
					(CR2[TIMER])
	PA1	With pull-up	push-pull	-	-
	PA2	With pull-up	push-pull	VSYNCI2	VSYNCSEL=1
					(MISCR)
	PA3	Without pull-up	open-drain	-	-
	PA4	Without pull-up	open-drain	-	-
	PA5	Without pull-up	open-drain	-	-
	PA6	Without pull-up	open-drain	-	-
	PA7	With pull-up	push-pull	BLANKOUT	BLKEN = 1
					(ENR[SYNC])
	*Reset State

29/144

ST72774/ST727754/ST72734

I/O PORTS (Cont’d)

Figure 17. PA0 to PA2, PA7

			Alternate enable
	Alternate		1		VDD
		output
			0		P-BUFFER
	DR				PULL-UP
	latch
BUS			OC1E
	DDR
DATA	latch				PAD
	DDR SEL
					N-BUFFER
	DR SEL	1
				OC1E	VSS
		0
				CMOS Schmitt Trigger

Figure 18. PA3 to PA6
DR		Alternate enable
	Alternate	1
latch
	output
DDR		0	PAD
latch
DDR SEL
BUS			N-BUFFER
DATA
	1
DR SEL		Alternate enable
	0		VSS
Alternate input		CMOS Schmitt Trigger
30/144