ST ST72681 User Manual

ST72681

USB 2.0 high-speed Flash drive controller

Features

■USB 2.0 interface compatible with mass storage device class

–Integrated USB 2.0 PHY supporting USB high speed and full speed

Not For New Design

LQFP48 7x7

–Suspend and Resume operations

■Mass storage controller interface (MSCI)

–Supports 2 KB-page NAND Flash devices including Numonyx, Hynix, Samsung, Toshiba, Micron, Renesas

–Reed-Solomon encoder/decoder on-the-fly correction (4 bytes of a 512-byte block)

–Flash identification support

–Up to 12 MB/s for read and 8 MB/s for write operations in single channel

–Up to 4 NAND Flash supported per channel

■Embedded ST7 8-bit MCU

■Supply management

–3.3 V operation

–Integrated 3.3-1.8 V voltage regulator

■USB 2.0 low-power device compliant

–Less than 100 mA during write operation with two NAND Flash devices

–Less than 500 µA in suspend mode

■AutoRun CDROM partition support

■Bootability support (HDD mode)

■Clock management

–Integrated PLL for generating core+USB 2.0 clocks from external 12 MHz crystal

■Data protection

–Write protect switch control

–Public/private partitions support

■Production tool device configurability:

–USB vendor ID/product ID (VID/PID), serial number and USB strings with foreign language support

–SCSI strings

–One or two LED outputs

–Adjustable NAND Flash bus frequency to reach highest performance

■Code update in the NAND Flash memory

■LQFP48 7x7 ECOPACK® package

■Development support

–Complete reference design including schematics, BOM and Gerber files

■Supports Windows (Vista, XP, 2000, ME), Linux and MacOS. Drivers available for Windows 98 SE

Table 1.	Device summary
	Features	Orderable part numbers
		ST72681/R20		ST72681/R21
	USB interface		USB 2.0 high speed
Number of NAND Flash devices supported (1)		up to 1		up to 4
	R/W speed	11MB/s and 7MB/s		12MB/s and 8MB/s
	Operating voltage		3.0 to 3.6 V
	Operating temperature		0 to +70 °C
	Package	LQFP48 7x7 / Die form

1. Number of NAND Flash devices supported in a single channel.

February 2009	Rev 6	1/34
This is information on a product still in production but not recommended for new designs.		www.st.com

Contents	ST72681

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 4
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
3	Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
4	NAND Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

4.1 NAND Flash support table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 NAND error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2.1 Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2.2 Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Management of bad NAND Flash blocks . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3.1 Bad block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3.3 Late fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4.1 LUT usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5 NAND Flash interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5

Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

5.1 USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 BOT / SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2.1 BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.2 SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.3 Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.1 Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.3 Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.4 CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4 Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6	Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	6.1	LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	6.2	Read only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
7	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17

2/34

ST72681 Contents

7.1	Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	7.1.1	Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.1.2	Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.1.3	Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.1.4	Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	7.1.5	Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18

7.2	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		18
	7.2.1	Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	7.2.2	Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	7.2.3	Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19

7.3	Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.3.1	General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
7.4	Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	7.4.1	RUN and SUSPEND modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	7.4.2	Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

7.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.5.1 General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.6 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

		7.6.1	Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . .	22
		7.6.2	Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
		7.6.3	Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . .	23
	7.7	I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		24
		7.7.1	General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
		7.7.2	Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	7.8	Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
		7.8.1	Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	7.9	Other communication interface characteristics . . . . . . . . . . . . . . . . . . . .		28
		7.9.1	MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28
		7.9.2	Universal serial bus interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . .	29
8	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			31
9	Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			32
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			33

3/34

Introduction	ST72681

1 Introduction

The ST72681 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed interface including PHY and function supports USB 2.0 mass storage device class.

The mass storage controller interface (MSCI) combined with the Reed-Solomon encoder/decoder on-the-fly correction (4-byte on 512-byte data blocks) provides a flexible, high transfer rate solution for interfacing a wide of range NAND Flash memory device types.

The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz frequency for the USB 2.0 PHY.

The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data and patch code are stored in internal RAM.

I/O ports provide functions for EEPROM connection, LEDs and write protect switch control.

The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital part of the circuit.

Figure 1. Device block diagram

12 MHz		8-bit	ROM	RAM
OSC		CPU
			Mass	Reed-	NAND
USB 2.0		USB 2.0	Storage
				Solomon
PHY	Function		Controller	Error	I/F
			Interface	Correction
3.3 V to 1.8 V
voltage			GPIO
regulator

4/34

ST72681	Pin description

2 Pin description

Figure 2 shows the LQFP48 package pinout, while Table 2, Table 3, Table 4, and Table 5 give the pin description.

The legend and abbreviations used in these tables are the following:

●Type

–I = input

–O = output

–S = supply

●Input level: A = Dedicated analog input

●In/Output level

–CT = CMOS 0.3VDD/0.7VDD with input trigger

–TT= TTL 0.8V / 2 V with Schmitt trigger

●Output level

–D8 = 8mA drive

–D4 = 4mA drive

–D2 = 2mA drive

Figure 2. 48-pin LQFP package pinout

	VSS1	VDD331	NC NANDD[0]	NANDD[1] NANDD[2] NANDD[3] NANDD[4] NANDD[5] NANDD[6] NANDD[7]	NANDRnB
			(1)
VDDA	48 47 46 45			44 43 42 41 40 39 38 37		NAND WP
	1				36
OSCIN	2				35	READ ONLY
OSCOUT	3				34	EEPROM SCL
VSSA	4				33	VSS_2
RREF	5				32	VDD33_2
VSSC	6		ST72681		31	NC(1)
VDDC	7				30	NC(1)
VDD3	8				29	RESET
USBDP	9				28	LED2
USBDM	10				27	LED1
VSSBL	11				26	NAND ALE/EEPROM SDA
VDDBL	12				25	VSS_3
	13 14 15 16 17 18 19 20 21 22 23 24
	VDDOUSB	VSS4	VDD334 NANDCE4	NANDCE3 NANDCE2 NANDCE1 NANDRE NANDWE NANDCLE NC	VDD333
				(1)

1. Must remain NOT connected in the application.

5/34

Pin description								ST72681
	Table 2.		Power supply
	Pin		Pin name		Type			Description
	48		VSS_1		S		Ground
	47		VDD33_1		S	I/Os and regulator supply voltage
	33		VSS_2		S		Ground
	32		VDD33_2		S	I/Os and regulator supply voltage
	25		VSS_3		S		Ground
	24		VDD33_3		S	I/Os and regulator supply voltage
	14		VSS_4		S		Ground
	15		VDD33_4		S	I/Os and regulator supply voltage
	13		VDDOUSB		S	USB2 PHY, OSC and PLL power supply output (1.8 V)
	Table 3.		USB 2.0 interface
	Pin		Pin name		Type			Description
	12		VDDBL		S			Supply voltage for buffers and de-serialization flip flops (1.8 V)
	11		VSSBL		S			Ground for buffers and de-serialization flip flops (1.8 V)
	10		USBDM		I/O			USB2 DATA -
	9		USBDP		I/O			USB2 DATA +
	8		VDD3		S			Supply voltage for the FS compliance (3.3 V)
	7		VDDC		S			Supply voltage for DLL & XOR tree (1.8 V)
	6		VSSC		S			Ground for DLL & XOR tree (1.8 V)
	5		RREF		I/O			Ref. resistor for integrated impedance process adaptation
								(11.3 kOhms 1% pull down)
	Table 4.		USB 2.0 and core clock system
	Pin		Pin name		Type			Description
	4		VSSA		S			Ground for oscillator & PLL (1.8 V)
	3		OSCOUT		O			12 MHz oscillator output
	2		OSCIN		I			12 MHz oscillator input
	1		VDDA		S			Supply voltage for oscillator & PLL (1.8 V)

6/34

ST72681									Pin description
	Table 5.		General purpose I/O ports /mass storage I/Os
	Pin		Pin name	Type	Level			Main function
					Input	Outputs		(after reset)
	45		NAND D[0]	I/O	TT	D4	NAND Data [0]
	44		NAND D[1]	I/O	TT	D4	NAND Data [1]
	43		NAND D[2]	I/O	TT	D4	NAND Data [2]
	42		NAND D[3]	I/O	TT	D4	NAND Data [3]
	41		NAND D[4]	I/O	TT	D4	NAND Data [4]
	40		NAND D[5]	I/O	TT	D4	NAND Data [5]
	39		NAND D[6]	I/O	TT	D4	NAND Data [6]
	38		NAND D[7]	I/O	TT	D4	NAND Data [7]
	26		NAND ALE	I/O	TT	D8	NAND Address Latch Enable
	22		NAND CLE	O	TT	D8	NAND Command Latch Enable
	21		NAND WE	O	TT	D8	NAND WRite Enable
	20		NAND RE	O	TT	D8	NAND read enable
	19		NAND CE1	O	TT	D4	NAND Chip Enable 1
	18		NAND CE2	O	TT	D4	NAND Chip Enable 2
	17		NAND CE3	O	TT	D4	NAND Chip Enable 3
	16		NAND CE4	O	TT	D4	NAND Chip Enable 4
	37		NAND RnB	I	TT	D2
							NAND Ready/Busy
	36		NAND WP	O	TT	D2	NAND Write Protect
	35		READ ONLY	I	TT	D2	Read -only switch (“0”: Read/Write; “1”:
							Read only)
	34		EEPROM SCL	O	TT	D2	EEPROM serial clock
	28		LED2	O	TT	D8	Green LED (USB access)
	27		LED1	O	TT	D8	Red LED (NAND memory access)

7/34

Application schematics	ST72681

3 Application schematics

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ST72681/R20 only supports single NAND Flash Chip Enable configuration (one NAND Flash device with one Chip Enable signal). Note that pins NAND_RnB2, NAND_CE2, NAND_CE3 and NAND_CE4 should remain unconnected.

8/34

ST72681	Application schematics

ST72681/R21 can support up to four NAND Flash Chip Enable signals. The application can use one of the following configurations:

●One NAND Flash device with four Chip Enable signals; NAND_CE1, NAND_CE2, NAND_CE3 and NAND_CE4 are used.

●One NAND Flash device with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used.

●One NAND Flash device with one Chip Enable signal; only NAND_CE1 is used.

●Two NAND Flash devices with two Chip Enable signals; NAND_CE1 and NAND_CE2 are used to select the first NAND Flash device and NAND_CE3 and NAND_CE4 to select the second NAND Flash device.

●Two NAND Flash devices with one Chip Enable signal; NAND_CE1 and NAND_CE2 are used to select is used to select the first NAND Flash device and the 2nd NAND Flash device, respectively.

●4 NAND Flash devices with 1Chip Enable signal; NAND_CE1 selects the first NAND Flash device, NAND_CE2 the 2nd NAND Flash device, NAND_CE3 to select the third, and NAND_CE4 to select the fourth NAND Flash device.

9/34

NAND Flash interface	ST72681

4 NAND Flash interface

4.1NAND Flash support table

Table 6.	Known NAND Flash compatibility guide for R20 and R21 devices(1)(2)
		NAND size (Mbytes or Gbytes)		Number of NAND devices
NAND name				supported
			and type
				R20 device	R21 device
Samsung K9F1G08U		128 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9F2G08U		256 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9F4G08U		512 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9K4G08U		512 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9W4G08U		512 MB; SLC2K; Dual CE		-	1 or 2
Samsung K9K8G08U		1 GB; SLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9W8G08U		1 GB; SLC2K; Dual CE		-	1 or 2
Samsung K9WAG08U		2 GB; SLC2K; Dual CE		-	1 or 2
Samsung K9NBG08U		4 GB; SLC2K; Quad CE		-	1
Samsung K9G4G08U		512 MB; MLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9L8G08U		1 GB; MLC2K; Single CE		1	1, 2, 3 or 4
Samsung K9HAG08U		2 GB; MLC2K; Dual CE		-	1 or 2
Samsung K9MBG08U		4 GB; MLC2K; Quad CE		-	1
Toshiba TH58NVG0S3		128	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Toshiba TH58NVG1S3		256	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Toshiba TH58NVG2S3		512	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Toshiba TH58NVG1D4		256	MB; MLC2K; Single CE	1	1, 2, 3 or 4
Toshiba TH58NVG2D4		512	MB; MLC2K; Single CE	1	1, 2, 3 or 4
Toshiba TH58NVG3D4		1 GB; MLC2K; Single CE		1	1, 2, 3 or 4
Numonyx NAND01GW3B		128 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Numonyx NAND02GW3B		256 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Numonyx NAND04GW3B		512 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Numonyx NAND08GW3B		1 GB; SLC2K; Single CE		1	1, 2, 3 or 4
Numonyx NAND04GW3C		512 MB; MLC2K; Single CE		1	1, 2, 3 or 4
Hynix HY27UF081G2M		128	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Hynix HY27UG082G2M		256 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Hynix HY27UG084G2M		512 MB; SLC2K; Single CE		1	1, 2, 3 or 4
Hynix HY27UH084G5M		512 MB; SLC2K; Dual CE		-	1 or 2
Hynix HY27UH088G2M		1 GB; SLC2K; Single CE		1	1, 2, 3 or 4
Hynix HY27UT084G2M		512	MB; MLC2K; Single CE	1	1, 2, 3 or 4
Hynix HY27UU088G5M		1 GB; MLC2K; Dual CE		-	1 or 2
Micron 29F2G08AA		256	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Micron 29F4G08BA		512	MB; SLC2K; Single CE	1	1, 2, 3 or 4
Micron 29F8G08FA		1 GB; SLC2K; Dual CE		-	1 or 2

1.This list is provided as a guide only as it is not possible to automatically guarantee support for all the additions and updates across the listed ranges of manufacturers’ devices.

2.Only NAND Flash devices with 2 Kbyte pages are supported.

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ST72681	NAND Flash interface

4.2NAND error correction

No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error occurrence depends on the Flash cell type (MLC or SLC).

The ST72681 embeds hardware and firmware mechanisms to correct the errors.

4.2.1Hardware error correction

The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly manages 512-byte data packets on the NAND Flash I/O system.

Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC) consisting of 8 words each containing 10 bits.

During write operations to NAND memory, the 512-bytes of data and the ECC are stored together in the same page. The ECC is stored in the corresponding Redundant Area (RA), using 10 bytes.

During read operations, the 512-bytes of data and the 8 ECC words are read back and are passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4 symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).

The hardware cell gives 3 possible results:

●No error detected: the data packet can be used as it is.

●Correctable error detected: the corrected data are available in a specific 512-byte buffer in the Reed-Solomon cell and are ready to use.

●Uncorrectable error detected: data corruption is not repairable.

4.2.2Firmware error management

The firmware defines the error correction possibilities with the corrected data packet.

When data is not repairable, the block is considered as bad and replaced by another one. See below for further information.

4.3Management of bad NAND Flash blocks

NAND Flash device manufacturers deliver their products with factory-marked bad blocks. This marking depends on the manufacturer and the NAND Flash type (page size, memory technology, etc.). The ST72681 supports all bad block markings currently available on the market.

4.3.1Bad block identification

During firmware initialization, the MCU scans the entire NAND Flash configuration to identify bad blocks.

A bad block is defined as follows:

●5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an other page (page 127 for MLC NAND Flash memory; page 1 for SLC NAND Flash memory).

●The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.

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