ST ST72651AR6 User Manual
ST72651AR6
LQFP64 10x10
Low-power, full-speed USB 8-bit MCU with 32 KB Flash, 5 KB
RAM, Flash card interface, timer, PWM, ADC,
■ Memories
I2C, SPI
– Up to 32 KB of High Density Flash (HDFlash)
program memory with read/write protection
– For HDFlash devices, In-Application Pro-
gramming (IAP) via USB and In-Circuit programming (ICP)
– Up to 5 KB of RAM with up to 256 B stack
■ Clock, Reset and Supply Management
– PLL for generating 48 MHz USB clock using a
12 MHz crystal
– Low Voltage Reset (except on E suffix devic-
es)
– Dual supply management: analog voltage de-
tector on the USB power line to enable smart
power switching from USB power to battery
(on E suffix devices).
– Programmable Internal Voltage Regulator for
Memory cards (2.8V to 3.5V) supplying:
Flash Card I/O lines (voltage shifting)
Up to 50 mA for Flash card supply
– Clock-out capability
■ 47 programmable I/O lines
– 15 high sink I/Os (8mA@0.6V / 20mA@1.3V)
– 5 true open drain outputs
– 24 lines programmable as interrupt inputs
■ USB (Universal Serial Bus) Interface
– with DMA for full speed bulk applications com-
pliant with USB 12 Mbs specification (version
2.0 compliant)
– On-Chip 3.3V USB voltage regulator and
transceivers with software power-down
– 5 USB endpoints:
1 control endpoint
2 IN endpoints supporting interrupt and bulk
2 OUT endpoints supporting interrupt and
bulk
– Hardware conversion between USB bulk
packets and 512-byte blocks
■ Mass Storage Interface
– DTC (Data Transfer Coprocessor): Universal
Serial/Parallel communications interface, with
software plug-ins for current and future protocol standards:
Compact Flash - Multimedia Card -
Secure Digital Card - SmartMediaCard Sony Memory Stick - NAND Flash ATA Peripherals
■ 2 Timers
– Configurable Watchdog for system reliability
– 16-bit Timer with 2 output compare functions.
■ 2 Communication Interfaces
– SPI synchronous serial interface
2
C Single Master Interface up to 400 KHz
–I
■ D/A and A/D Peripherals
– PWM/BRM Generator (with 2 10-bit PWM/
BRM outputs)
– 8-bit A/D Converter (ADC) with 8 channels
■ Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■ Development Tools
– Full hardware/software development package
Device Summary
Features ST72651AR6
Program memory 32 Kbytes of Flash program memory
User RAM (stack) - bytes 5 Kbyte (256)
Peripherals USB, DTC, Timer, ADC, SPI, I
Operating Supply 4.0 to 5.5 V (for USB) Dual 3.0 to 5.5 V or 4.0 to 5.5 V (for USB)
Package LQFP64 (10 x10)
Operating Temperature 0 to +70 °C
2
C, PWM, WDT
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Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
-
8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 143
13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 153
15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.1 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD-
WARE WATCHDOG OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.3 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
16.4 I2C MULTIMASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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ST72651AR6
512-byte RAM
Buffer
512-byte RAM
Buffer
DATA
COPROCESSOR
DATA TRANSFER
BUFFER
LEVEL
SHIFTERS
MASS
DEVICE
USB
SIE
ST7 CORE
STORAGE
TRANSFER
(DTC)
ARBITRATION
USB DATA
TRANSFER
BUFFER ACCESS
1 INTRODUCTION
The ST7265x MCU supports volume data exchange with a host (computer or kiosk) via a full
speed USB interface. The MCU is capable of handling various transfer protocols, with a particular
emphasis on mass storage applications.
ST7265x is compliant with the USB Mass Storage
Class specifications, and supports related protocols such as BOT (Bulk Only Transfer) and CBI
(Control, Bulk, Interrupt).
It is based on the ST7 standard 8-bit core, with
specific peripherals for managing USB full speed
data transfer between the host and most types of
FLASH media card:
– A full speed USB interface with Serial Interface
Engine, and on-chip 3.3V regulator and transceivers.
– A dedicated 24 MHz Data Buffer Manager state
machine for handling 512-byte data blocks (this
Figure 1. USB Data Transfer Block Diagram
size corresponds to a sector both on computers
and FLASH media cards).
– A Data Transfer Coprocessor (DTC), able to
handle fast data transfer with external devices.
This DTC also computes the CRC or ECC required to handle Mass storage media.
– An Arbitration block gives the ST7 core priority
over the USB and DTC when accessing the Data
Buffer. In USB mode, the USB interface is serviced before the DTC.
– A FLASH Supply Block able to provide program-
mable supply voltage and I/O electrical levels to
the FLASH media.
Related Documentation
AN1475: Developing an ST7265x Mass Storage
Application
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INTRODUCTION (Cont’d)
512-byte RAM
Buffer
512-byte RAM
Buffer
DATA
COPROCESSOR
DATA TRANSFER
BUFFER
LEVEL SHIFTERS
MASS
DEVICE
ST7 CORE
STORAGE
TRANSFER
(DTC)
ARBITRATION
BUFFER ACCESS
DIGITAL
AUDIO DEVICE
I2C
In addition to the peripherals for USB full speed
data transfer, the ST7265x includes all the necessary features for stand-alone applications with
FLASH mass storage.
– Low voltage reset ensuring proper power-on or
power-off of the device (not on all products)
– Digital Watchdog
– 16-bit Timer with 2 output compare functions (not
on all products - see device summary).
– Serial Peripheral interface (not on all products -
see device summary)
2
– Fast I
C Single Master interface (not on all prod-
ucts - see device summary)
– 8-bit Analog-to-Digital converter (ADC) with 8
multiplexed analog inputs (not on all products see device summary)
The ST72F65x are the Flash versions of the
ST7265x in a LQFP64 package.
– Two 10-bit PWM outputs (not on all products -
see device summary)
Figure 2. Digital Audio Player Application Example in Play Mode
ST72651AR6
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ST72651AR6
8-BIT CORE
ALU
ADDRESS AND DATA BUS
OSCIN
OSCOUT
RESET
DATA
PD[7:0]
(8 bits)
12MHz
f
CPU
CONTROL
RAM
(0.5/5 KBytes)
PROGRAM
(16/32 Kbytes)
MEMORY
16-BIT TIMER*
LVD*
WATCHDOG
V
DDA
V
PP
USBDP
USBDM
USBVCC
* not available on all products (refer to Table 1: Device Summary)
TRANSFER
COPROCESSOR
PORT C
PORT E
PORT D
PE[7:0]
(8 bits)
PC[7:0]
(8 bits)
PB[7:0]
(8 bits)
PA[7:0]
(8 bits)
PORT F
PF[6:0]
(7 bits)
8-BIT ADC*
I2C*
FLASH SUPPLY
V
DDF
V
SSA
POWER SUPPLY
DUAL SUPPLY
USBVSS
MANAGER *
BLOCK
48MHz
PLL
CLOCK
DIVIDER
OSC
USB
V
SSF
USBVDD
V
SS1, VSS2
V
DD1,VDD2
PWM*
PORT B
PORT A
DATA
TRANSFER
BUFFER
(1280 bytes)
DTC S/W RAM
(256 Bytes)
REGULATOR
ARBITRATION
SPI *
INTRODUCTION (Cont’d)
Figure 3. ST7265x Block Diagram
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2 PIN DESCRIPTION
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
V
DDAVDD2
PF6 (HS) / ICCDATA
PF5 (HS)/ICCCLK
RESET
V
PP/
ICCSEL
PE4
OSCOUT
OSCIN
V
SS2VSSA
USBV
DD
V
DDF
V
SSF
DTC/PB0
DTC/PB1
DTC/PB3
USBV
SS
USBDM
USBDP
USBVCC
DTC / PA0
DTC / PA1
DTC / PA2
DTC / PA3
DTC / PA4
DTC / PA5
DTC / PA6
DTC / PA7
DTC/PB5
DTC/PB6
DTC/PB7
PE2 (HS) / DTC
PE1 (HS) / DTC
PE0 (HS) / DTC
PD7
V
SS1
V
DD1
PD0
PD1
PD2
PD3
PD5
PD6
PD4
PE3/DTC
DTC/PB2
DTC/PB4
(HS) high sink capability
eixassociated external interrupt vector
I/O pin supplied by V
DDF
/ V
SSF
ei1
ei0
Figure 4. 48-Pin LQFP Package Pinout
ST72651AR6
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ST72651AR6
DTC / PA2
DTC / PA3
DTC / PA4
DTC / PA5
DTC / PA6
DTC / PA7
SS
/ MCO / (HS) PC0
MISO / DTC / (HS) PC1
MOSI / DTC / (HS) PC2
SCK / DTC / (HS) PC3
V
DD1
V
SS1
DTC / PB6
DTC / PB7
DTC / PA0
DTC / PA1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ei1
ei0
USBV
DD
V
DDF
V
SSF
DTC / PE5 (HS)
DTC / PE6 (HS)
DTC / PE7 (HS)
DTC / PB0
DTC / PB1
DTC / PB2
DTC / PB3
DTC / PB4
DTC / PB5
USBV
SS
USBDM
USBDP
USBVCC
PD7 / AIN3
PD6 / AIN2
PD5/OCMP2
PD4/OCMP1
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
PE3 / PWM0 / AIN7 / DTC
PE2 (HS) / AIN6 / DTC
PE1 (HS) / AIN5 / DTC
PE0 (HS) / AIN4 / DTC
V
DDAVDD2
PF6 (HS)/ICCDATA
PF5 (HS)/ICCCLK
PF4 (HS) / USBEN
PF3 / AIN1
PF2 / AIN0
PF1 (HS) / SDA
PF0 (HS) / SCL
RESET
V
PP
/ICCSEL
PE4 / PWM1
OSCOUT
OSCIN
V
SS2VSSA
(HS) high sink capability
ei
x
associated external interrupt vector
I/O pin supplied by V
DDF
/ V
SSF
ei2
ei2
PIN DESCRIPTION (Cont’d)
Figure 5. 64-Pin LQFP Package Pinout
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PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Type: I = input, O = output, S = supply
V
powered: I/O powered by the alternate sup-
DDF
ply rail, supplied by V
In/Output level: C
T
DDF
and V
SSF
.
= CMOS 0.3VDD/0.7VDD with
input trigger
Output level: HS = High Sink (on N-buffer only)
Port and control configuration:
– Input:float = floating, wpu = weak pull-up, int = in-
terrupt
– Output: OD = open drain, T = true open drain, PP
= push-pull, OP = pull-up enabled by option byte.
Refer to “I/O PORTS” on page 45 for more details
on the software configuration of the I/O ports.
The RESET configuration of each pin is shown in
bold.
Table 1. Device Pin Description
Pin
Pin Name
LQFP64
1USBV
2 USBDM I/O USB bidirectional data (data -)
3 USBDP I/O USB bidirectional data (data +)
4 USBVCC O
5USBV
6V
7V
8 PE5/DTC I/O X C
9 PE6/DTC I/O X C
10 PE7/DTC I/O X C
11 PB0/DTC I/O X CT X X Port B0 DTC
12 PB1/DTC I/O X CT X X Port B1 DTC
13 PB2/DTC I/O X CT X X Port B2 DTC
14 PB3/
SS
DD
DDF
SSF
DTC I/O X CT X X Port B3 DTC
Type
S USB Digital ground
S
SX
SX
Level Port / Control
Input Output
Output
int
wpu
float
2)
HS X
HS X X X Port E6
HS X X X Port E7
X2)XPort E5
Powered
DDF
V
Input
T
T
T
OD
Main
Function
(after reset)
PP
USB power supply, output by the on-chip USB 3.3V
linear regulator.
Note: An external decoupling capacitor (typ. 100nF,
min 47nF) must be connected between this pin and
SS
.
DTC I/O with serial capability
(MMC_CMD)
DTC I/O with serial capability
(MMC_DAT)
DTC I/O with serial capability
(MMC_CLK)
USBV
USB Power supply voltage (4V - 5.5V) also used by
the regulator and PLL
Note: External decoupling capacitors (typ.
4.7µF+100nF, min 2.2µF+100nFmust be connected
between this pin and USBV
Power Line for alternate supply rail. Can be used as
input (with external supply) or output (when using the
on-chip voltage regulator). Note: An external decoupling capacitor (min. 20nF) must be connected to this
pin to stabilize the regulator.
Ground Line for alternate supply rail. Can be used as
input (with external supply) or output (when using the
on-chip voltage regulator)
Alternate Function
ST72651AR6
.
SS
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1
ST72651AR6
Pin
Pin Name
LQFP64
15 PB4/DTC I/O X CT X X Port B4 DTC
16 PB5/DTC I/O X CT X X Port B5 DTC
17 PB6/DTC I/O X CT X X Port B6 DTC
18 PB7/DTC I/O X CT X X Port B7 DTC
19 PA0/DTC I/O X CT X
20 PA1/DTC I/O X CT X X X Port A1 DTC
21 PA2/DTC I/O X CT X X X Port A2 DTC
22 PA3/DTC I/O X CT X X X Port A3 DTC
23 PA4/DTC I/O X CT X X X Port A4 DTC
24 PA5/DTC I/O X CT X X X Port A5 DTC
25 PA6/DTC I/O X CT X X X Port A6 DTC
26 PA7/DTC I/O X CT X X X Port A7 DTC
27 PC0/MCO/SS
28 PC1/DTC/MIS0 I/O X CTHS X X Port C1
29 PC2/DTC/MOSI I/O X CTHS X X Port C2
30 PC3/DTC/SCK I/O X CTHS X X Port C3
31 V
DD1
32 V
SS1
33 PC4/DTC I/O C
34 PC5/DTC I/O C
35 PC6/DTC I/O C
36 PC7/DTC I/O C
37 PD0 I/O CT X
38 PD1 I/O CT X X X Port D1
39 PD2 I/O CT X X X Port D2
40 PD3 I/O CT X X X Port D3
41 PD4/OCMP1 I/O CT X X X Port D4 Timer Output Compare 1
42 PD5/OCMP2 I/O CT X X X Port D5 Timer Output Compare 2
43 PD6/AIN2 I/O CT X X X Port D6 Analog Input 2
44 PD7/AIN3 I/O CT X X X Port D7 Analog Input 3
45 PE0/DTC/AIN4 I/O CT HS X X X Port E0 Analog Input 4
Type
I/O X CT HS X
S Power supply voltage (3V - 5.5V)
S Digital ground
Level Port / Control
Input Output
Output
wpu
float
ei0
ei2
X
X X Port C5 DTC
ei2
X X Port C6 DTC
X X Port C7 DTC
ei1
Powered
DDF
V
Input
T
T
T
T
Main
Function
(after reset)
int
PP
OD
X X Port A0 DTC
XPort C0
X Port C4 DTC
XXPort D0
Alternate Function
Main Clock Output / SPI Slave
1)
Select
DTC I/O with serial capability (DA-
TARQ) / SPI Master In Slave Out
DTC I/O with serial capability (SDAT) /
SPI Master Out Slave In
DTC I/O with serial capability (SCLK) /
SPI Serial Clock
1)
1)
1)
1)
/ DTC
1)
1)
1)
1)
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Doc ID 7215 Rev 4
ST72651AR6
Pin
Pin Name
Type
LQFP64
Level Port / Control
Input Output
Input
Powered
DDF
V
Output
float
wpu
int
OD
Main
Function
(after reset)
PP
Alternate Function
46 PE1/DTC/AIN5 I/O CTHS X X X Port E1 Analog Input 5
47 PE2/DTC/AIN6 I/O C
PE3/AIN7/DTC/
48
PWM0
I/O C
49 PE4/PWM1 I/O C
50 VPP /ICCSEL S
HS X X X Port E2 Analog Input 6
T
T
T
XXXPort E3
X X X Port E4 PWM Output 1
Analog Input 7
1)
0
Flash programming voltage. Must be held low in normal operating mode.
Bidirectional. This active low signal forces the initialization of the MCU. This event is the top priority non
51 RESET
I/O X X
maskable interrupt. This pin is switched low when the
Watchdog has triggered or V
to reset external peripherals.
52 PF0 / SCL I/O C
HS X T Port F0 I2C Serial Clock
T
53 PF1 / SDA I/O CTHS X T Port F1 I2C Serial Data
54 PF2 / AIN0 I/O C
55 PF3 / AIN1 I/O C
T
T
X X Port F2 Analog Input 0
X X Port F3 Analog Input 1
USB Power Management USB Enable
56 PF4 / USBEN I/O CTHS X T Port F4
(alternate function selected by option
bit)
57 PF5 / ICCCLK I/O C
58 PF6 / ICCDATA I/O C
59 V
60 V
61 V
62 V
DD2
DDA
SSA
SS2
S
S Analog supply voltage
S Analog ground
S Digital ground
63 OSCIN I
HS X T Port F5 ICC Clock Output
T
HS X T Port F6 ICC Data Input
T
Main Power supply voltage (3V - 5.5V on devices
without LVD, otherwise 4V - 5.5V).
Input/Output Oscillator pins. These pins connect a 12
MHz parallel-resonant crystal, or an external source
64 OSCOUT O
to the on-chip oscillator.
1)
/ DTC
1)
/ DTC
1)
/ DTC / PWM Output
1)
is low. It can be used
DD
1)
1)
1)
1)
Notes:
1. If the peripheral is present on the device (see Device Summary on page 1)
2. A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register
and depending on the PE5PU bit in the option byte.
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ST72651AR6
VCC
USB
DP
DM
USBV
DD
DTC
USB Port
FLASH
V
DDF
VPP
GND
USB
4.7μF
V
DD
USBVDD
POWER
USB
MANAGEMENT
5V
DP
DM
GND
100nF
12V for
LED2
level translator
Flash prog.
REGULATOR
I/O
LOGIC
=4.0-5.5V
UP TO 5
MULTIMEDIA
OR SD CARDS
CLK DAT CMD
PE7
PE6
V
DD
PE5
(2)
100nF
100nF
1.5KΩ
LED1
(connect to
GND if
not used)
Figure 6. Multimedia Card Or Secure Digital Card Writer Application Example
ST72F65 pin PE5 PE6 PE7
ST7 / DTC
(1) This line shows if the ST72F65 pin is controlled by the
ST7 core or by the DTC.
MultiMedia Card Pin CMD DAT CLK
(1)
DTC DTC DTC
used as a normal I/O by configuring it as such by the option byte.
(2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
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Figure 7. Smartmedia Card Writer Or Flash Drive Application Example
DTC
FLASH
V
DDF
VPP
V
DD
POWER
MANAGEMENT
100nF
12V for
level translator
Flash prog.
REGULATOR
I/O
LOGIC
UP TO 2
SMARTMEDIA
CARDS
PA
PB
V
DD
8
6
I/O
0~7
CTRL
(4)
2
PE
VCC
USB
DP
DM
USBV
DD
USB Port
GND
USB
4.7μF
USBVDD
USB
5V
DP
DM
GND
=4.0-5.5V
100nF
100nF
1.5K
Ω
LED2
LED1
(connect to
GND if
not used)
5
1
ST72651AR6
Table 2. SmartMedia Interface Pin Assignment
SmartMedia Pin I/O0~7 CLE WE ALE RE R/B WP
ST72F65 pin PB0-7 PA0 PA1 PA2 PA3 PA4 PA7 PE1 PE0
ST7 / DTC
(1)
(1): This line shows if the ST72F65 pin is controlled by the
ST7 core or the DTC.
(2): These lines are not controlled by the DTC but by the
user software running on the ST7 core. The ST72F65 pin
choice is at customer discretion. The pins shown here are
only shown as an example.
(3): When a single card is to be handled, PA7 is free for
other functions. When 2 Smartmedia are to be handled,
pins from both cards should be tied together (i.e. CLE1
DTC DTC DTC DTC DTC DTC ST7 ST7 ST7
with CLE2...) except for the CE pins. CE pin from card 1
should be connected to PA6 and CE pin from card 2
should be connect to PA7. Selection of the operating card
is done by ST7 software.
(4) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
used as a normal I/O by configuring it as such by the option byte.
Doc ID 7215 Rev 4
(2)
(2)
CE1
CE2
(2)(3)
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ST72651AR6
DTC
FLASH
V
DDF
VPP
V
DD
POWER
MANAGEMENT
3)
100nF
level
REGULATOR
I/O
LOGIC
PA
PB
CF
8-BIT MEMORY
MODE
6
8
PE
[2]
translator
LED1
VCC
USB
DP
DM
USBV
DD
USB Port
GND
USB
4.7μF
USBVDD
USB
5V
DP
DM
GND
=4.0-5.5V
100nF
100nF
1.5K
Ω
4.7µF
LED2
12V for
Flash prog.
(connect to
GND if
not used)
5
1
4.7K
Ω
Figure 8. Compact Flash Card Writer Application Example
Table 3. Compact Flash Card Writer Pin Assignment
Compact Flash
Card Pin
D0-7 D8-15
, VS2, WAIT,
VS1
, INPACK,
CS1
BVD1
, BVD2
IORD,
IOWR
CE2
ST72F65 pin PB0-7 NC NC V
1)
ST7 / DTC
Notes:
1. This line shows if the ST72F65 pin is controlled by the
ST7 core or by the DTC.
2. These lines are not controlled by the DTC but by the
DTC - - Power Power DTC ST7 DTC DTC ST7 -
user software running on the ST7 core. The choice of
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Doc ID 7215 Rev 4
, REG,
, V
CC
DDF
CSEL,
RESET,
GND,
A3-10
V
ST72F65 pin is at the customer’s discretion. The pins
shown here are given only as an example.
3. As this is a single power supply application, the USBEN
function in not needed. Thus PF4/USBEN pin can be
used as a normal I/O by configuring it as such by the op-
SSF
A0-2 CE1
PE2
PA0-2
+pull-up
4.7kΩ
RE WE CD1
PA6
PA3 PA5
+pull-up
100kΩ
RDY/BSY,
tion byte.
CD2,
WP
NC
Figure 9. Sony Memory Stick Writer Ap3plication Example
VCC
USB
DP
DM
USBV
DD
DTC
USB Port
FLASH
V
DDF
VPP
GND
USB
4.7μF
V
DD
USBVDD
POWER
USB
MANAGEMENT
2)
5V
DP
DM
GND
100nF
12V for
LED2
level translator
Flash prog.
REGULATOR
I/O
LOGIC
=4.0-5.5V
SONY
MEMORY STICK
PC3
PC1
V
DD
PC2
100nF
100nF
1.5KΩ
LED1
(connect to
GND if
not used)
PC0
CD CLK BS DAT
4.7µF
ST72651AR6
MultiMedia Card Pin CMD DAT CLK
ST72F65 pin PE5 PE6 PE7
ST7 / DTC
(1) This line shows if the ST72F65 pin is controlled by the
(1)
ST7 core or by the DTC.
DTC DTC DTC
used as a normal I/O by configuring it as such by the option byte.
(2) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be
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ST72651AR6
0000h
Interrupt & Reset Vectors
HW Registers
0050h
004Fh
(see Table 4)
FFDFh
FFE0h
FFFFh
(see Table 10)
8000h
7FFFh
Program Memory*
5 KBytes RAM*
16 Kbytes
C000h
Reserved
1450h
144Fh
32 Kbytes
512 Bytes RAM*
Short Addressing
Stack (256 Bytes)
0100h
0200h
144Fh
0050h
00FFh
01FFh
16-bit Addressing RAM
RAM (176 Bytes)
(4688 Bytes)
Short Addressing
Stack (256 Bytes)
0100h
0200h
024Fh
0050h
00FFh
01FFh
16-bit Addressing RAM
RAM (176 Bytes)
(80 Bytes)
154Fh
1A4Fh
256 Bytes
1280 Bytes
USB Data Buffer**
DTC RAM (Write protected)
3 REGISTER & MEMORY MAP
As shown in Figure 10, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of 80
bytes of register locations, up to 5 Kbytes of RAM
and up to 32 Kbytes of user program memory. The
RAM space includes up to 256 bytes for the stack
from 0100h to 01FFh.
Figure 10. Memory Map
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the
device.
Related Documentation
AN985: Executing Code in ST7 RAM
* Program memory and RAM sizes are product dependent (see Table –)
** The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in stan-
dalone mode.
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ST72651AR6
Table 4. Hardware Register Memory Map
Address Block Register Label Register name Reset Status Remarks
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
ADC Data Register
ADC Control Status Register
Reserved Area (3 bytes)
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
DTC Control Register
DTC Status Register
DTC Pointer Register
1
PADR
PADDR
PAOR
PBDR
PBDDR
PCDR
PCDDR
PCOR
PDDR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
ADCDR
ADCCSR
SPIDR
SPICR
SPICSR
DTCCR
DTCSR
Reserved
DTCPR
0000h
0001h
0002h
0003h
0004h
0005h Reserved Area (1 byte)
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h Reserved Area (1 byte)
0012h
0013h
0014h WDG WDGCR Watchdog Control Register 7Fh R/W
0015h
to
0017h
0018h DSM PCR Power Control Register 00h R/W
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
ADC
SPI
DTC
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
0xh
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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ST72651AR6
Address Block Register Label Register name Reset Status Remarks
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh Flash Flash Control Status Register 00h R/W
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h USB BUFCSR Buffer Control/Status Register 00h R/W
0048h Reserved Area (1 Byte)
0049h MISCR1 Miscellaneous Register 1 00h R/W
004Ah MISCR2 Miscellaneous Register 2 00h R/W
004Bh Reserved Area (1 Byte)
TIM
ITC
USB
2C 1
I
TCR1
TCR2
TSR
CHR
CLR
ACHR
ACLR
OC1HR
OC1LR
OC2HR
OC2LR
ITSPR0
ITSPR1
ITSPR2
ITSPR3
USBISTR
USBIMR
USBCTLR
DADDR
USBSR
EP0R
CNT0RXR
CNT0TXR
EP1RXR
CNT1RXR
EP1TXR
CNT1TXR
EP2RXR
CNT2RXR
EP2TXR
CNT2TXR
I2CCR
I2CSR1
I2CSR2
I2CCCR
Not used
Not used
I2CDR
Timer Control Register 1
Timer Control Register 2
Timer Status Register
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Output Compare 1 High Register
Timer Output Compare 1 Low Register
Timer Output Compare 2 High Register
Timer Output Compare 2 Low Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
Device Address Register
USB Status Register
Endpoint 0 Register
EP 0 Reception Counter Register
EP 0 Transmission Counter Register
Endpoint 1 Register
EP 1 Reception Counter Register
Endpoint 1 Register
EP 1 Transmission Counter Register
Endpoint 2 Register
EP 2 Reception Counter Register
Endpoint 2 Register
EP 2 Transmission Counter Register
2
I
C Control Register
2
I
C Status Register 1
2
I
C Status Register 2
2
I
C Clock Control Register
2
I
C Data Register
00h
00h
00h
FFh
FCh
FFh
FCh
80h
00h
80h
00h
FFh
FFh
FFh
FFh
00h
00h
06h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
R/W
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ST72651AR6
Address Block Register Label Register name Reset Status Remarks
004Ch MISCR3 Miscellaneous Register 3 00h R/W
004Dh
004Eh
004Fh
PWM
PWM0
1)
BRM10
PWM1
10-bit PWM/BRM registers
80h
00h
80h
Note 1. If the peripheral is present on the device (see Device Summary on page 1)
R/W
R/W
R/W
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ST72651AR6
4 Kbytes
4 Kbytes
2Kbytes
SECTOR 1
SECTOR 0
16 Kbytes
SECTOR 2
8K 16K 32K 60K DV FLASH
FFFFh
EFFFh
DFFFh
3FFFh
7FFFh
1000h
24 Kbytes
MEMORY SIZE
8Kbytes 40 Kbytes
52 Kbytes
9FFFh
BFFFh
D7FFh
4K 10K 24K 48K
4 FLASH PROGRAM MEMORY
4.1 Introduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V
supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.
4.2 Main Features
■ Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the
application is running.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 Structure
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 5). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 Kbytes
(see Figure 11). They are mapped in the upper
part of the ST7 addressing space so the reset and
interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 5. Sectors available in Flash devices
Flash Memory Size
(bytes)
4K Sector 0
8K Sectors 0,1
> 8K Sectors 0,1, 2
Available Sectors
4.4 Read-out Protection
Read-out protection, when selected, provides a
protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
In Flash devices, this protection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.
Read-out protection selection is enabled and removed through the FMP_R bit in the option byte.
The Flash memory is organised in sectors and can
be used for both code and data storage.
Figure 11. Memory Map and Sector Address
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FLASH PROGRAM MEMORY (Cont’d)
ICC CONNECTOR
ICCDATA
ICCCLK
RESET
V
DD
HE10 CONNECTOR TYPE
APPLICATION
POWER SUPPLY
1
246810
975 3
PROGRAMMING TOOL
ICC CONNECTOR
APPLICATION BOARD
ICC Cable
(See Note 3)
10kΩ
V
SS
ICCSEL/VPP
ST7
C
L2
C
L1
OSC1
OSC2
OPTIONAL
See Note 1
See Note 2
APPLICATION
RESET SOURCE
APPLICATION
I/O
(See Note 4)
ST72651AR6
4.5 ICC Interface
ICC needs a minimum of 4 and up to 6 pins to be
connected to the programming tool (see Figure
12). These pins are:
– RESET
–V
: device reset
: device power supply ground
SS
Figure 12. Typical ICC Interface
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V
: programming voltage
PP
– OSC1(or OSCIN): main clock input for exter-
nal source (optional)
: application board power supply (see Fig-
–V
DD
ure 12, Note 3)
Notes:
1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the application RESET circuit in this case. When using a
classical RC network with R>1K or a reset man-
pin. This can lead to con-
agement IC with open drain output and pull-up resistor>1K, no additional components are needed.
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multioscillator capability need to have OSC2
grounded in this case.
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FLASH PROGRAM MEMORY (Cont’d)
4.6 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 12). For more details
on the pin locations, refer to the device pinout description.
4.7 IAP (In-Application Programming)
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the Flash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.
4.8 Related Documentation
For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual
.
4.9 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
70
00000000
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.
Table 6. FLASH Register Map and Reset Values
Address
(Hex.)
002Bh
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Register
Label
FCSR
Reset Value
76543210
00000000
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1
5 CENTRAL PROCESSING UNIT
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C1I1HI0NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH
PCL
15
8
70
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE =
1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
X = Undefined Value
ST72651AR6
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■ Enable executing 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes (with indirect
addressing mode)
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power HALT and WAIT modes
■ Priority maskable hardware interrupts
■ Non-maskable software/hardware interrupts
Figure 13. CPU Registers
5.3 CPU REGISTERS
The six CPU registers shown in Figure 13 are not
present in the memory mapping and are accessed
by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
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ST72651AR6
CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)
Read/Write
Reset Value: 111x1xxx
70
11I1HI0NZ
C
The 8-bit Condition Code register contains the interrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic Management Bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
th
sult 7
bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
Interrupt Management Bits
Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt software priority.
Interrupt Software Priority I1 I0
Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1
These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.
See the interrupt management chapter for more
details.
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CENTRAL PROCESSING UNIT (Cont’d)
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
Subroutine
Interrupt
Event
PUSH Y POP Y IRET
RET
or RSP
@ 01FFh
@ 0100h
Stack Higher Address = 01FFh
Stack Lower Address =
0100h
ST72651AR6
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15 8
00000001
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously
stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
70
SP7 SP6 SP5 SP4 SP3 SP2 SP1
SP0
The stack is used to save the return address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 14).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an
MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 14.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
higher address.
Figure 14. Stack Manipulation Example
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ST72651AR6
OSCIN
OSCOUT
EXTERNAL
CLOCK
NC
OSCIN
OSCOUT
C
OSCIN
C
OSCOUT
6 SUPPLY, RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM
6.1.1 General Description
The MCU accepts either a 12 MHz crystal or an
external clock signal to drive the internal oscillator.
The internal clock (f
nal oscillator frequency (f
) is derived from the inter-
CPU
), which is 12 Mhz in
OSC
Stand-alone mode and 48Mhz in USB mode.
The internal clock (f
) is software selectable us-
CPU
ing the CP[1:0] and CPEN bits in the MISCR1 register.
In USBV
power supply mode, the PLL is active,
DD
generating a 48MHz clock to the USB. In this
mode, f
In V
DD
bled, and the maximum frequency of f
can be configured to be up to 8 MHz.
CPU
mode the PLL and the USB clock are disa-
is 6
CPU
MHz.
The internal clock signal (f
) is also routed to
CPU
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz in the frequency
range specified for f
. The circuit shown in Fig-
osc
ure 16 is recommended when using a crystal, and
Table 7 lists the recommended capacitance. The
crystal and associated components should be
mounted as close as possible to the input pins in
order to minimize output distortion and start-up
stabilisation time.
6.1.2 External Clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as
shown on Figure 15. The t
specifications
OXOV
does not apply when using an external clock input.
The equivalent specification of the external clock
source should be used instead of t
OXOV
(see Sec-
tion 6.5 CONTROL TIMING).
Figure 15. External Clock Source Connections
Figure 16. Crystal Resonator
Table 7. Recommended Values for 12-MHz
Crystal Resonator
R
SMAX
C
OSCIN
C
OSCOUT
Note: R
crystal (see crystal specification).
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SMAX
1
20 Ω 25 Ω 70 Ω
56pF 47pF 22pF
56pF 47pF 22pF
is the equivalent serial resistor of the
Doc ID 7215 Rev 4
6.2 RESET SEQUENCE MANAGER (RSM)
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
t
w(RSTL)out
RUN
t
h(RSTL)in
ACTIVE
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN RUN RUN
RESET
RESET
SOURCE
SHORT EXT.
RESET
LVD
RESET
LONG EXT.
RESET
WATCHDOG
RESET
INTERNAL RESET (min 512 T
CPU
)
VECTOR FETCH
t
w(RSTL)out
PHASE
ACTIVE
PHASE
ACTIVE
PHASE
DELAY
ST72651AR6
6.2.1 Introduction
The reset sequence manager includes three RESET sources as shown in Figure 6.2.2:
■ External RESET source pulse
■ Internal LVD RESET (Low Voltage Detection)
■ Internal WATCHDOG RESET
These sources act on the RESET
pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
Figure 17. RESET Sequences
The basic RESET sequence consists of 3 phases
as shown in Figure 17:
■ Active Phase depending on the RESET source
■ Min 512 CPU clock cycle delay (see Figure 19
and Figure 20
■ RESET vector fetch
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recommended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
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ST72651AR6
f
CPU
COUNTER
RESET
R
ON
V
DD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET
The RESET
output with integrated R
pin is both an input and an open-drain
weak pull-up resistor.
ON
pin
This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state
even in HALT mode.
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteristics section.
If the external RESET
t
w(RSTL)out
(see short ext. Reset in Figure 17), the
signal on the RESET
pulse is shorter than
pin will be stretched. Otherwise the delay will not be applied (see long ext.
Reset in Figure 17).
Figure 18. Reset Block Diagram
Starting from the external RESET pulse recognition, the device RESET
is pulled low during at least t
pin acts as an output that
w(RSTL)out
.
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■
Power-On RESET
■ Voltage Drop RESET
The device RESET
pulled low when V
V
DD<VIT-
(falling edge) as shown in Figure 17.
The LVD filters spikes on V
pin acts as an output that is
DD<VIT+
(rising edge) or
shorter than t
DD
g(VDD)
to avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
Starting from the Watchdog counter underflow, the
device RESET
low during at least t
pin acts as an output that is pulled
w(RSTL)out
.
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RESET SEQUENCE MANAGER (Cont’d)
512 x t
CPU(STAND-ALONE)
RESET
FETCH VECTOR
DELAY
FETCH VECTOR
256 x t
CPU(STAND-ALONE)
256 x t
CPU(USB)
PLL Startup
RESET
time (undefined)
DELAY
400 µs typ.
In stand-alone mode, the 512 CPU clock cycle delay allows the oscillator to stabilize and ensures
that recovery has taken place from the Reset
state.
Figure 19. Reset Delay in Stand-alone Mode
Figure 20. Reset Delay in USB Mode
ST72651AR6
In USB mode the delay is 256 clock cycles counted from when the PLL LOCK signal goes high.
The RESET vector fetch phase duration is 2 clock
cycles.
Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.
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ST72651AR6
V
DDA
V
IT+(LVD)
RESET
V
IT-(LVD)
V
hyst
6.3 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management
features in the application, the Low Voltage Detector function (LVD) generates a static reset when
the V
supply voltage is below a V
DDA
reference
IT-
value. This means that it secures the power-up as
well as the power-down, keeping the ST7 in reset.
The V
than the V
reference value for a voltage drop is lower
IT-
reference value for power-on in order
IT+
to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
Figure 21. Low Voltage Detector vs Reset
The LVD Reset circuitry generates a reset when
is below:
V
DDA
–V
–V
when V
IT+
when V
IT-
DDA
is falling
DDA
is rising
The LVD function is illustrated in Figure 21.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Note: It is recommended to make sure that the
supply voltage rises monotonously when the
V
DDA
device is exiting from Reset, to ensure the application functions properly.
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