ST ST72651AR6 User Manual

ST72651AR6

Low-power, full-speed USB 8-bit MCU with 32 KB Flash, 5 KB RAM, Flash card interface, timer, PWM, ADC, I2C, SPI

■Memories

–Up to 32 KB of High Density Flash (HDFlash) program memory with read/write protection

–For HDFlash devices, In-Application Programming (IAP) via USB and In-Circuit programming (ICP)

–Up to 5 KB of RAM with up to 256 B stack

■Clock, Reset and Supply Management

LQFP64 10x10

■ Mass Storage Interface

–PLL for generating 48 MHz USB clock using a 12 MHz crystal

–Low Voltage Reset (except on E suffix devices)

–Dual supply management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).

–Programmable Internal Voltage Regulator for Memory cards (2.8V to 3.5V) supplying:

Flash Card I/O lines (voltage shifting) Up to 50 mA for Flash card supply

–Clock-out capability

■47 programmable I/O lines

–15 high sink I/Os (8mA@0.6V / 20mA@1.3V)

–5 true open drain outputs

–24 lines programmable as interrupt inputs

■USB (Universal Serial Bus) Interface

–with DMA for full speed bulk applications compliant with USB 12 Mbs specification (version 2.0 compliant)

–On-Chip 3.3V USB voltage regulator and transceivers with software power-down

–5 USB endpoints:

1 control endpoint

2 IN endpoints supporting interrupt and bulk

2 OUT endpoints supporting interrupt and bulk

–Hardware conversion between USB bulk packets and 512-byte blocks

Device Summary

– DTC (Data Transfer Coprocessor): Universal

Serial/Parallel communications interface, with

software plug-ins for current and future proto-

col standards:

Compact Flash - Multimedia Card -

Secure Digital Card - SmartMediaCard -

Sony Memory Stick - NAND Flash -

ATA Peripherals

■2 Timers

–Configurable Watchdog for system reliability

–16-bit Timer with 2 output compare functions.

■2 Communication Interfaces

–SPI synchronous serial interface

–I2C Single Master Interface up to 400 KHz

■D/A and A/D Peripherals

–PWM/BRM Generator (with 2 10-bit PWM/ BRM outputs)

–8-bit A/D Converter (ADC) with 8 channels

■Instruction Set

–8-bit data manipulation

–63 basic instructions

–17 main addressing modes

–8 x 8 unsigned multiply instruction

–True bit manipulation

■Development Tools

–Full hardware/software development package

Features	ST72651AR6
Program memory	32 Kbytes of Flash program memory
User RAM (stack) - bytes	5 Kbyte (256)
Peripherals	USB, DTC, Timer, ADC, SPI, I2C, PWM, WDT
Operating Supply	4.0 to 5.5 V (for USB)	Dual 3.0 to 5.5 V or 4.0 to 5.5 V (for USB)
Package	LQFP64 (10 x10)
Operating Temperature	0 to +70 °C
June 2009	Doc ID 7215 Rev 4	1/161
		1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
5.2	MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
5.3	CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23

6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 POWER SUPPLY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
8.1	INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43
-	WAIT MODE	43
8.2
8.3	HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	44

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 DATA TRANSFER COPROCESSOR (DTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2/161

Doc ID 7215 Rev 4

1

Table of Contents
11.4 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 76
11.5 PWM/BRM GENERATOR (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	88
11.6 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	94
11.7 I²C SINGLE MASTER BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	105
11.8 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	114
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	118
12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	121
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	124
13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	125
13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	126
13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	128
13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	131
13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	132
13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	133
13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	135
13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	139
13.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	142
13.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . .	143
13.128-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	148
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	150
14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	152
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . .	153
15.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	153
15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	154
15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	155
15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	156

16 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

16.1 SPI MULTIMASTER MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARDWARE WATCHDOG OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

16.3 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16.4 I2C MULTIMASTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Doc ID 7215 Rev 4

3/161

1

ST72651AR6

1 INTRODUCTION

The ST7265x MCU supports volume data exchange with a host (computer or kiosk) via a full speed USB interface. The MCU is capable of handling various transfer protocols, with a particular emphasis on mass storage applications.

ST7265x is compliant with the USB Mass Storage Class specifications, and supports related protocols such as BOT (Bulk Only Transfer) and CBI (Control, Bulk, Interrupt).

It is based on the ST7 standard 8-bit core, with specific peripherals for managing USB full speed data transfer between the host and most types of FLASH media card:

–A full speed USB interface with Serial Interface Engine, and on-chip 3.3V regulator and transceivers.

–A dedicated 24 MHz Data Buffer Manager state machine for handling 512-byte data blocks (this

Figure 1. USB Data Transfer Block Diagram

size corresponds to a sector both on computers and FLASH media cards).

–A Data Transfer Coprocessor (DTC), able to handle fast data transfer with external devices. This DTC also computes the CRC or ECC required to handle Mass storage media.

–An Arbitration block gives the ST7 core priority over the USB and DTC when accessing the Data Buffer. In USB mode, the USB interface is serviced before the DTC.

–A FLASH Supply Block able to provide programmable supply voltage and I/O electrical levels to the FLASH media.

Related Documentation

AN1475: Developing an ST7265x Mass Storage

Application

USB

SIE

DATA TRANSFER

USB DATA

TRANSFER

BUFFER

512-byte RAM

ST7 CORE

BUFFER ACCESS

Buffer

ARBITRATION

512-byte RAM

Buffer

DATA

TRANSFER

COPROCESSOR

(DTC)

LEVEL

SHIFTERS

MASS

STORAGE

DEVICE

4/161

Doc ID 7215 Rev 4

1

ST72651AR6

INTRODUCTION (Cont’d)

In addition to the peripherals for USB full speed data transfer, the ST7265x includes all the necessary features for stand-alone applications with FLASH mass storage.

–Low voltage reset ensuring proper power-on or power-off of the device (not on all products)

–Digital Watchdog

–16-bit Timer with 2 output compare functions (not on all products - see device summary).

–Two 10-bit PWM outputs (not on all products - see device summary)

–Serial Peripheral interface (not on all products - see device summary)

–Fast I2C Single Master interface (not on all products - see device summary)

–8-bit Analog-to-Digital converter (ADC) with 8 multiplexed analog inputs (not on all products - see device summary)

The ST72F65x are the Flash versions of the ST7265x in a LQFP64 package.

Figure 2. Digital Audio Player Application Example in Play Mode

DATA TRANSFER

BUFFER

512-byte RAM

Buffer

512-byte RAM

Buffer

BUFFER ACCESS					ST7 CORE
ARBITRATION

		DATA
		TRANSFER
		COPROCESSOR							I2C
		(DTC)

LEVEL SHIFTERS

MASS

DIGITAL

STORAGE AUDIO DEVICE

DEVICE

Doc ID 7215 Rev 4

5/161

1

ST72651AR6

INTRODUCTION (Cont’d)

Figure 3. ST7265x Block Diagram

OSCIN	12MHz
OSCOUT	OSC		CLOCK		PORT A	PA[7:0]
						(8 bits)
			DIVIDER
	48MHz
						PB[7:0]
	PLL				PORT B
			fCPU			(8 bits)
					SPI *
					PORT C	PC[7:0]
						(8 bits)
	DATA				DATA
	TRANSFER	ARBITRATION			TRANSFER
	BUFFER				COPROCESSOR
	(1280 bytes)				DTC S/W RAM
				ADDRESS	(256 Bytes)
					PORT E	PE[7:0]
						(8 bits)
				AND	PWM*
USBDP				DATA
USBDM	USB				PORT F
USBVCC				BUS		PF[6:0]
PD[7:0]
					I2C*	(7 bits)
	PORT D
(8 bits)
	16-BIT TIMER*				8-BIT ADC*
	WATCHDOG					VDDF
					FLASH SUPPLY
RESET	CONTROL				BLOCK	VSSF
	8-BIT CORE				POWER SUPPLY	VDDA
VPP	ALU				REGULATOR	VSSA
	LVD*					VDD1,VDD2
	RAM				DUAL SUPPLY	VSS1, VSS2
					MANAGER *	USBVDD
	(0.5/5 KBytes)
						USBVSS
	PROGRAM
	MEMORY
	(16/32 Kbytes)

* not available on all products (refer to Table 1: Device Summary)

6/161

Doc ID 7215 Rev 4

1

ST72651AR6

2 PIN DESCRIPTION

Figure 4. 48-Pin LQFP Package Pinout

OSCOUT

OSCIN

V V V V (HS)PF6/ ICCDATA (HS)/ICCCLKPF5

RESET

V PE4

PE3/DTC

SS2 SSA DDA DD2

ICCSEL

PP/

USBVSS

48 47 46 45

44 43 42 41 40 39 38 37

PE2 (HS) / DTC

1

36

USBDM

2

35

PE1 (HS) / DTC

USBDP

3

34

PE0 (HS) / DTC

USBVCC

4

33

PD7

USBVDD

5

32

PD6

VDDF

6

31

PD5

PD4

VSSF

7

ei1

30

PD3

DTC/PB0

8

29

DTC/PB1

9

28

PD2

DTC/PB2

10

ei0

27

PD1

DTC/PB3

11

26

PD0

DTC/PB4

12

25

VSS1

13 14 15 16 17 18 19 20 21 22 23 24

DTC/PB5

DTC/PB6

DTC/PB7 /DTCPA0

/DTCPA1 /DTCPA2 /DTCPA3 /DTCPA4

/DTCPA5

/DTCPA6 /DTCPA7

V

DD1

I/O pin supplied by VDDF / VSSF (HS) high sink capability

eix associated external interrupt vector

Doc ID 7215 Rev 4

7/161

1

ST72651AR6

PIN DESCRIPTION (Cont’d)

Figure 5. 64-Pin LQFP Package Pinout

USBVSS

USBDM

USBDP

USBVCC

USBVDD

VDDF

VSSF

DTC / PE5 (HS) DTC / PE6 (HS) DTC / PE7 (HS)

DTC / PB0

DTC / PB1

DTC / PB2

DTC / PB3

DTC / PB4

DTC / PB5

OSCOUT OSCIN V

V

V

V (HS)/ICCDATAPF6 (HS)/ICCCLKPF5

USBEN/(HS)PF4 AIN1/PF3 AIN0/PF2 SDA/(HS)PF1 SCL/(HS)PF0 RESET V

SS2

SSA

DDA

DD2

/ICCSEL

PP

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 1

2

3

4

5

6 7

8 ei1 9

10

11 12

	13
	14	ei0	ei2	ei2
	15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DTC/ PB6 DTC/ PB7 DTC/ PA0 DTC/ PA1 DTC/ PA2 DTC/ PA3 DTC/ PA4 DTC/ PA5 DTC/ PA6 DTC/ PA7 (HS)/ PC0

(HS)/ PC1

(HS)/ PC2

(HS)/ PC3

DD1

V

MCO

/ DTC

/ DTC

/ DTC

SS /

MISO

MOSI

SCK

PE4 / PWM1

49

48 PE3 / PWM0 / AIN7 / DTC 47 PE2 (HS) / AIN6 / DTC

46 PE1 (HS) / AIN5 / DTC 45 PE0 (HS) / AIN4 / DTC

44 PD7 / AIN3

43 PD6 / AIN2

42 PD5/OCMP2

41 PD4/OCMP1

40 PD3

39 PD2

38 PD1

37 PD0

36 PC7

35 PC6

34 PC5

33 PC4

32

VSS1

I/O pin supplied by VDDF / VSSF

(HS)	high sink capability
eix	associated external interrupt vector

8/161

Doc ID 7215 Rev 4

1

ST72651AR6

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:

Type: I = input, O = output, S = supply

VDDF powered: I/O powered by the alternate supply rail, supplied by VDDF and VSSF.

In/Output level: CT = CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = High Sink (on N-buffer only)

Table 1. Device Pin Description

Port and control configuration:

–Input:float = floating, wpu = weak pull-up, int = interrupt

–Output: OD = open drain, T = true open drain, PP

=push-pull, OP = pull-up enabled by option byte.

Refer to “I/O PORTS” on page 45 for more details on the software configuration of the I/O ports.

The RESET configuration of each pin is shown in bold.

Pin

Powered

Level

Port / Control

LQFP64

Type

Input

Output

float

wpu int

OD

PP

Main

V

Pin Name

Input

Output

Function

Alternate Function

DDF

(after reset)

1

USBVSS

S

USB Digital ground

2

USBDM

I/O

USB bidirectional data (data -)

3

USBDP

I/O

USB bidirectional data (data +)

USB power supply, output by the on-chip USB 3.3V

linear regulator.

4

USBVCC

O

Note: An external decoupling capacitor (typ. 100nF,

min 47nF) must be connected between this pin and

USBVSS.

USB Power supply voltage (4V - 5.5V) also used by

the regulator and PLL

5

USBVDD

S

Note: External decoupling capacitors (typ.

4.7µF+100nF, min 2.2µF+100nFmust be connected

between this pin and USBVSS.

Power Line for alternate supply rail. Can be used as

input (with external supply) or output (when using the

6

VDDF

S

X

on-chip voltage regulator). Note: An external decou-

pling capacitor (min. 20nF) must be connected to this

pin to stabilize the regulator.

Ground Line for alternate supply rail. Can be used as

7

VSSF

S

X

input (with external supply) or output (when using the

on-chip voltage regulator)

8

PE5/DTC

I/O

X

CT

HS

X2)

X2)

X

Port E5

DTC I/O with serial capability

(MMC_CMD)

9

PE6/DTC

I/O

X

CT

HS

X

X

X

Port E6

DTC I/O with serial capability

(MMC_DAT)

10

PE7/DTC

I/O

X

CT

HS

X

X

X

Port E7

DTC I/O with serial capability

(MMC_CLK)

11

PB0/DTC

I/O

X

CT

X

X

Port B0

DTC

12

PB1/DTC

I/O

X

CT

X

X

Port B1

DTC

13

PB2/DTC

I/O

X

CT

X

X

Port B2

DTC

14

PB3/DTC

I/O

X

CT

X

X

Port B3

DTC

Doc ID 7215 Rev 4

9/161

1

ST72651AR6

Pin

Powered

Level

Port / Control

LQFP64

Type

Input

Output

float

wpu int

OD

PP

Main

V

Pin Name

Input

Output

Function

Alternate Function

DDF

(after reset)

15

PB4/DTC

I/O

X

CT

X

X

Port B4

DTC

16

PB5/DTC

I/O

X

CT

X

X

Port B5

DTC

17

PB6/DTC

I/O

X

CT

X

X

Port B6

DTC

18

PB7/DTC

I/O

X

CT

X

X

Port B7

DTC

19

PA0/DTC

I/O

X

CT

X

X

X

Port A0

DTC

20

PA1/DTC

I/O

X

CT

X

X

X

Port A1

DTC

21

PA2/DTC

I/O

X

CT

X

X

X

Port A2

DTC

22

PA3/DTC

I/O

X

CT

X

ei0

X

X

Port A3

DTC

23

PA4/DTC

I/O

X

CT

X

X

X

Port A4

DTC

24

PA5/DTC

I/O

X

CT

X

X

X

Port A5

DTC

25

PA6/DTC

I/O

X

CT

X

X

X

Port A6

DTC

26

PA7/DTC

I/O

X

CT

X

X

X

Port A7

DTC

Main Clock Output / SPI Slave

27

PC0/MCO/SS

I/O

X

CT

HS

X

X

Port C0

Select1)

28

PC1/DTC/MIS0

I/O

X

CT

HS

X

X

Port C1

DTC I/O with serial capability (DA-

ei2

TARQ) / SPI Master In Slave Out

1)

29

PC2/DTC/MOSI

I/O

X

CT

HS

X

X

Port C2

DTC I/O with serial capability (SDAT) /

SPI Master Out Slave In

1)

30

PC3/DTC/SCK

I/O

X

CT

HS

X

X

Port C3

DTC I/O with serial capability (SCLK) /

SPI Serial Clock

1)

31

VDD1

S

Power supply voltage (3V - 5.5V)

32

VSS1

S

Digital ground

33

PC4/DTC

I/O

CT

X

X

Port C4

DTC

34

PC5/DTC

I/O

CT

X

ei2

X

Port C5

DTC

35

PC6/DTC

I/O

CT

X

X

Port C6

DTC

36

PC7/DTC

I/O

CT

X

X

Port C7

DTC

37

PD0

I/O

CT

X

X

X

Port D0

38

PD1

I/O

CT

X

X

X

Port D1

39

PD2

I/O

CT

X

X

X

Port D2

40

PD3

I/O

CT

X

ei1

X

X

Port D3

41

PD4/OCMP1

I/O

CT

X

X

X

Port D4

Timer Output Compare 11)

42

PD5/OCMP2

I/O

CT

X

X

X

Port D5

Timer Output Compare 21)

43

PD6/AIN2

I/O

CT

X

X

X

Port D6

Analog Input 21)

44

PD7/AIN3

I/O

CT

X

X

X

Port D7

Analog Input 31)

45

PE0/DTC/AIN4

I/O

CT

HS

X

X

X

Port E0

Analog Input 41)/ DTC

10/161

Doc ID 7215 Rev 4

1

ST72651AR6

Pin

Powered

Level

Port / Control

LQFP64

Type

Input

Output

float

wpu int

OD

PP

Main

V

Pin Name

Input

Output

Function

Alternate Function

DDF

(after reset)

46

PE1/DTC/AIN5

I/O

CT

HS

X

X

X

Port E1

Analog Input 51)/ DTC

47

PE2/DTC/AIN6

I/O

CT

HS

X

X

X

Port E2

Analog Input 61)/ DTC

48

PE3/AIN7/DTC/

I/O

CT

X

X

X

Port E3

Analog Input 71)/ DTC / PWM Output

PWM0

0

1)

49

PE4/PWM1

I/O

CT

X

X

X

Port E4

PWM Output 11)

50

VPP /ICCSEL

S

Flash programming voltage. Must be held low in nor-

mal operating mode.

Bidirectional. This active low signal forces the initiali-

zation of the MCU. This event is the top priority non

51

RESET

I/O

X

X

maskable interrupt. This pin is switched low when the

Watchdog has triggered or VDD is low. It can be used

to reset external peripherals.

52

PF0 / SCL

I/O

CT

HS

X

T

Port F0

I2C Serial Clock1)

53

PF1 / SDA

I/O

CT

HS

X

T

Port F1

I2C Serial Data1)

54

PF2 / AIN0

I/O

CT

X

X

Port F2

Analog Input 01)

55

PF3 / AIN1

I/O

CT

X

X

Port F3

Analog Input 11)

USB Power Management USB Enable

56

PF4 /

USBEN

I/O

CT

HS

X

T

Port F4

(alternate function selected by option

bit)

57

PF5 / ICCCLK

I/O

CT

HS

X

T

Port F5

ICC Clock Output

58

PF6 / ICCDATA

I/O

CT

HS

X

T

Port F6

ICC Data Input

59

VDD2

S

Main Power

supply voltage (3V - 5.5V on devices

without LVD, otherwise 4V - 5.5V).

60

VDDA

S

Analog supply voltage

61

VSSA

S

Analog ground

62

VSS2

S

Digital ground

63

OSCIN

I

Input/Output Oscillator pins. These pins connect a 12

MHz parallel-resonant crystal, or an external source

64

OSCOUT

O

to the on-chip oscillator.

Notes:

1.If the peripheral is present on the device (see Device Summary on page 1)

2.A weak pull-up can be enabled on PE5 input and open drain output by configuring the PEOR register and depending on the PE5PU bit in the option byte.

Doc ID 7215 Rev 4

11/161

1

ST72651AR6

Figure 6. Multimedia Card Or Secure Digital Card Writer Application Example

	4.7μF		100nF
					VDD
	USBVDD
	=4.0-5.5V		USBVDD
USB Port
5V	1.5KΩUSB
		VCC
	100nF		USB		POWER
DP		DP
				MANAGEMENT
DM		DM			(2)
GND		USB
		GND			I/O
					LOGIC
							LED1
							LED2
			DTC	REGULATOR
					FLASH	VPP	12V for
							Flash prog.
							(connect to
				level translator	VDDF		GND if
							not used)
			PE7 PE6 PE5
			CLK DAT CMD		100nF
			VDD
			UP TO 5
			MULTIMEDIA
			OR SD CARDS

MultiMedia Card Pin	CMD	DAT	CLK
ST72F65 pin	PE5	PE6	PE7
ST7 / DTC (1)	DTC	DTC	DTC

(1)This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

(2)As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be

used as a normal I/O by configuring it as such by the option byte.

12/161

Doc ID 7215 Rev 4

1

ST72651AR6

Figure 7. Smartmedia Card Writer Or Flash Drive Application Example

	4.7μF		100nF			VDD
	USBVDD
	=4.0-5.5V		USBVDD
USB Port
5V	1.5KΩUSB
		VCC
	100nF		USB
DP		DP				POWER
DM		DM				MANAGEMENT
GND		USB				(4)
						I/O
		GND
						LOGIC
				REGULATOR
								LED1
				DTC				LED2
				5	1	FLASH	VPP	12V for
			level translator					Flash prog.
								(connect to
		VDDF						GND if
					PE			not used)
			PB	PA
			8	6	2
	100nF
			I/O	CTRL
			0~7
			VDD
			UP TO 2
			SMARTMEDIA
				CARDS

Table 2. SmartMedia Interface Pin Assignment

SmartMedia Pin	I/O0~7	CLE	WE	ALE	RE	R/B			WP(2)	CE1(2)	CE2(2)(3)
ST72F65 pin	PB0-7	PA0	PA1	PA2	PA3	PA4			PA7	PE1	PE0
ST7 / DTC (1)	DTC	DTC	DTC	DTC	DTC	DTC			ST7	ST7	ST7

(1): This line shows if the ST72F65 pin is controlled by the ST7 core or the DTC.

(2): These lines are not controlled by the DTC but by the user software running on the ST7 core. The ST72F65 pin choice is at customer discretion. The pins shown here are only shown as an example.

(3): When a single card is to be handled, PA7 is free for other functions. When 2 Smartmedia are to be handled, pins from both cards should be tied together (i.e. CLE1

with CLE2...) except for the CE pins. CE pin from card 1 should be connected to PA6 and CE pin from card 2 should be connect to PA7. Selection of the operating card is done by ST7 software.

(4) As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.

Doc ID 7215 Rev 4

13/161

1

ST72651AR6

Figure 8. Compact Flash Card Writer Application Example

	4.7μF		100nF		VDD
	USBVDD
	=4.0-5.5V		USBVDD
USB Port
5V	1.5KΩUSB
		VCC
	100nF		USB		POWER
DP		DP
					MANAGEMENT 3)
DM		DM
GND		USB
		GND
					I/O
					LOGIC
					REGULATOR
							LED1
							LED2
				DTC
			1		FLASH	VPP	12V for
			5				Flash prog.
							(connect to
			level		VDDF
			translator				GND if
			PA	PB	PE		not used)
					[2]
					4.7KΩ
			6	8
					4.7µF
				CF	100nF
			8-BIT MEMORY
				MODE

Table 3. Compact Flash Card Writer Pin Assignment

CSEL,

CD2,

VS1, VS2, WAIT,

Compact Flash

IORD,

RESET,

D0-7

D8-15

,

,

IOWR

,

REG,

A0-2

CE1

RE

WE

CD1

RDY/BSY,

CS1

INPACK

Card Pin

BVD1, BVD2

CE2, VCC

GND,

WP

A3-10

PE2

PA6

ST72F65 pin

PB0-7

NC

NC

VDDF

VSSF

PA0-2

+pull-up

PA3

PA5

+pull-up

NC

4.7kΩ

100kΩ

ST7 / DTC 1)

DTC

-

-

Power

Power

DTC

ST7

DTC

DTC

ST7

-

Notes:

1.This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

2.These lines are not controlled by the DTC but by the user software running on the ST7 core. The choice of

ST72F65 pin is at the customer’s discretion. The pins shown here are given only as an example.

3. As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be used as a normal I/O by configuring it as such by the option byte.

14/161

Doc ID 7215 Rev 4

1

ST72651AR6

Figure 9. Sony Memory Stick Writer Ap3plication Example

	4.7μF		100nF
						VDD
	USBVDD
	=4.0-5.5V		USBVDD
USB Port
5V	1.5KΩUSB
		VCC
	100nF			USB		POWER
DP		DP
					MANAGEMENT 2)
DM		DM
GND		USB
		GND				I/O
						LOGIC
								LED1
								LED2
				DTC	REGULATOR
						FLASH	VPP	12V for
								Flash prog.
								(connect to
					level translator	VDDF		GND if
								not used)
			PC0	PC3 PC1 PC2
			CD	CLK BS	DAT	4.7µF
						100nF
					VDD
				SONY
			MEMORY STICK

MultiMedia Card Pin	CMD	DAT	CLK
ST72F65 pin	PE5	PE6	PE7
ST7 / DTC (1)	DTC	DTC	DTC

(1)This line shows if the ST72F65 pin is controlled by the ST7 core or by the DTC.

(2)As this is a single power supply application, the USBEN function in not needed. Thus PF4/USBEN pin can be

used as a normal I/O by configuring it as such by the option byte.

Doc ID 7215 Rev 4

15/161

1

ST72651AR6

3 REGISTER & MEMORY MAP

As shown in Figure 10, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.

The available memory locations consist of 80 bytes of register locations, up to 5 Kbytes of RAM and up to 32 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.

Figure 10. Memory Map

The highest address bytes contain the user reset and interrupt vectors.

IMPORTANT: Memory locations noted “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.

Related Documentation

AN985: Executing Code in ST7 RAM

0050h

0000h

Short Addressing

HW Registers

00FFh

RAM (176 Bytes)

(see Table 4)

004Fh

0100h

Stack (256 Bytes)

0050h

512 Bytes RAM*

01FFh

144Fh

5 KBytes RAM*

0200h

16-bit Addressing RAM

1450h

DTC RAM (Write protected)

(80 Bytes)

154Fh

256 Bytes

024Fh

USB Data Buffer**

1A4Fh

1280 Bytes

0050h

7FFFh

Reserved

Short Addressing

RAM (176 Bytes)

8000h

Program Memory*

00FFh

0100h

32 Kbytes

Stack (256 Bytes)

01FFh

C000h

0200h

16-bit Addressing RAM

16 Kbytes

(4688 Bytes)

144Fh

FFDFh

FFE0h

Interrupt & Reset Vectors

(see Table 10)

FFFFh

*Program memory and RAM sizes are product dependent (see Table –)

**The ST7 core is not able to read or write in the USB data buffer if the ST7265x is running at 6Mz in standalone mode.

16/161

Doc ID 7215 Rev 4

1

						ST72651AR6
	Table 4. Hardware Register Memory Map
	Address	Block	Register Label	Register name	Reset Status	Remarks
	0000h		PADR	Port A Data Register	00h	R/W
	0001h		PADDR	Port A Data Direction Register	00h	R/W
	0002h		PAOR	Port A Option Register	00h	R/W
	0003h		PBDR	Port B Data Register	00h	R/W
	0004h		PBDDR	Port B Data Direction Register	00h	R/W
	0005h			Reserved Area (1 byte)
	0006h		PCDR	Port C Data Register	00h	R/W
	0007h		PCDDR	Port C Data Direction Register	00h	R/W
	0008h		PCOR	Port C Option Register	00h	R/W
	0009h		PDDR	Port D Data Register	00h	R/W
	000Ah		PDDDR	Port D Data Direction Register	00h	R/W
	000Bh		PDOR	Port D Option Register	00h	R/W
	000Ch		PEDR	Port E Data Register	00h	R/W
	000Dh		PEDDR	Port E Data Direction Register	00h	R/W
	000Eh		PEOR	Port E Option Register	00h	R/W
	000Fh		PFDR	Port F Data Register	00h	R/W
	0010h		PFDDR	Port F Data Direction Register	00h	R/W
	0011h			Reserved Area (1 byte)
	0012h	ADC1	ADCDR	ADC Data Register	00h	Read only
	0013h		ADCCSR	ADC Control Status Register	00h	R/W
	0014h	WDG	WDGCR	Watchdog Control Register	7Fh	R/W
	0015h
	to			Reserved Area (3 bytes)
	0017h
	0018h	DSM	PCR	Power Control Register	00h	R/W
	0019h		SPIDR	SPI Data I/O Register	xxh	R/W
	001Ah	SPI	SPICR	SPI Control Register	0xh	R/W
	001Bh		SPICSR	SPI Control/Status Register	00h	R/W
	001Ch		DTCCR	DTC Control Register	00h	R/W
	001Dh	DTC	DTCSR	DTC Status Register	00h	R/W
	001Eh		Reserved
	001Fh		DTCPR	DTC Pointer Register	00h	R/W

Doc ID 7215 Rev 4

17/161

1

ST72651AR6

	Address	Block	Register Label	Register name	Reset Status	Remarks
	0020h		TCR1	Timer Control Register 1	00h	R/W
	0021h		TCR2	Timer Control Register 2	00h	R/W
	0022h		TSR	Timer Status Register	00h	Read Only
	0023h		CHR	Timer Counter High Register	FFh	Read Only
	0024h		CLR	Timer Counter Low Register	FCh	Read Only
	0025h	TIM	ACHR	Timer Alternate Counter High Register	FFh	Read Only
	0026h		ACLR	Timer Alternate Counter Low Register	FCh	Read Only
	0027h		OC1HR	Timer Output Compare 1 High Register	80h	R/W
	0028h		OC1LR	Timer Output Compare 1 Low Register	00h	R/W
	0029h		OC2HR	Timer Output Compare 2 High Register	80h	R/W
	002Ah		OC2LR	Timer Output Compare 2 Low Register	00h	R/W
	002Bh	Flash		Flash Control Status Register	00h	R/W
	002Ch		ITSPR0	Interrupt Software Priority Register 0	FFh	R/W
	002Dh	ITC	ITSPR1	Interrupt Software Priority Register 1	FFh	R/W
	002Eh		ITSPR2	Interrupt Software Priority Register 2	FFh	R/W
	002Fh		ITSPR3	Interrupt Software Priority Register 3	FFh	R/W
	0030h		USBISTR	USB Interrupt Status Register	00h	R/W
	0031h		USBIMR	USB Interrupt Mask Register	00h	R/W
	0032h		USBCTLR	USB Control Register	06h	R/W
	0033h		DADDR	Device Address Register	00h	R/W
	0034h		USBSR	USB Status Register	00h	R/W
	0035h		EP0R	Endpoint 0 Register	00h	R/W
	0036h		CNT0RXR	EP 0 Reception Counter Register	00h	R/W
	0037h	USB	CNT0TXR	EP 0 Transmission Counter Register	00h	R/W
	0038h		EP1RXR	Endpoint 1 Register	00h	R/W
	0039h		CNT1RXR	EP 1 Reception Counter Register	00h	R/W
	003Ah		EP1TXR	Endpoint 1 Register	00h	R/W
	003Bh		CNT1TXR	EP 1 Transmission Counter Register	00h	R/W
	003Ch		EP2RXR	Endpoint 2 Register	00h	R/W
	003Dh		CNT2RXR	EP 2 Reception Counter Register	00h	R/W
	003Eh		EP2TXR	Endpoint 2 Register	00h	R/W
	003Fh		CNT2TXR	EP 2 Transmission Counter Register	00h	R/W
	0040h		I2CCR	I2C Control Register	00h	R/W
	0041h		I2CSR1	I2C Status Register 1	00h	Read only
	0042h		I2CSR2	I2C Status Register 2	00h	Read only
	0043h	I2C 1	I2CCCR	I2C Clock Control Register	00h	R/W
	0044h		Not used
	0045h		Not used
	0046h		I2CDR	I2C Data Register	00h	R/W
	0047h	USB	BUFCSR	Buffer Control/Status Register	00h	R/W
	0048h			Reserved Area (1 Byte)
	0049h		MISCR1	Miscellaneous Register 1	00h	R/W
	004Ah		MISCR2	Miscellaneous Register 2	00h	R/W
	004Bh			Reserved Area (1 Byte)

18/161 Doc ID 7215 Rev 4

1

					ST72651AR6
Address	Block	Register Label	Register name	Reset Status	Remarks
004Ch		MISCR3	Miscellaneous Register 3	00h	R/W
004Dh		PWM0		80h	R/W
004Eh	PWM1)	BRM10	10-bit PWM/BRM registers	00h	R/W
004Fh		PWM1		80h	R/W

Note 1. If the peripheral is present on the device (see Device Summary on page 1)

Doc ID 7215 Rev 4

19/161

1

ST72651AR6

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply.

The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).

The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■Three Flash programming modes:

–Insertion in a programming tool. In this mode, all sectors including option bytes can be programmed or erased.

–ICP (In-Circuit Programming). In this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board.

–IAP (In-Application Programming) In this mode, all sectors except Sector 0, can be programmed or erased without removing the device from the application board and while the application is running.

■ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM

■Read-out protection

■Register Access Security System (RASS) to prevent accidental programming or erasing

4.3 Structure

The Flash memory is organised in sectors and can be used for both code and data storage.

Figure 11. Memory Map and Sector Address

Depending on the overall Flash memory size in the microcontroller device, there are up to three user sectors (see Table 5). Each of these sectors can be erased independently to avoid unnecessary erasing of the whole Flash memory when only a partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes (see Figure 11). They are mapped in the upper part of the ST7 addressing space so the reset and interrupt vectors are located in Sector 0 (F000hFFFFh).

Table 5. Sectors available in Flash devices

	Flash Memory Size	Available Sectors
	(bytes)
	4K	Sector 0
	8K	Sectors 0,1
	> 8K	Sectors 0,1, 2

4.4 Read-out Protection

Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.

In Flash devices, this protection is removed by reprogramming the option. In this case, the entire program memory is first automatically erased and the device can be reprogrammed.

Read-out protection selection is enabled and removed through the FMP_R bit in the option byte.

4K

8K

10K

16K

24K

32K

48K

60K

DV FLASH

MEMORY SIZE

1000h

3FFFh

7FFFh

9FFFh

SECTOR 2

BFFFh

D7FFh						52 Kbytes
DFFFh				2 Kbytes 8 Kbytes 16 Kbytes 24 Kbytes 40 Kbytes
EFFFh					4 Kbytes				SECTOR 1
FFFFh					4 Kbytes				SECTOR 0

20/161 Doc ID 7215 Rev 4

1

ST72651AR6

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICC Interface

ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 12). These pins are:

–RESET: device reset

–VSS: device power supply ground

–ICCCLK: ICC output serial clock pin

–ICCDATA: ICC input/output serial data pin

–ICCSEL/VPP: programming voltage

–OSC1(or OSCIN): main clock input for external source (optional)

–VDD: application board power supply (see Fig- ure 12, Note 3)

Figure 12. Typical ICC Interface

PROGRAMMING TOOL

ICC CONNECTOR

ICC Cable

APPLICATION BOARD

(See Note 3)

APPLICATION CL2

POWER SUPPLY

		OSC2
V
DD

		OPTIONAL
		(See Note 4)										9				7			5			3			1
													10			8			6			4			2
										10kΩ
					CL1
									SS							ICCSEL/VPP			RESET			ICCCLK			ICCDATA
					ST7
OSC1								V

ICC CONNECTOR

HE10 CONNECTOR TYPE

APPLICATION

RESET SOURCE

See Note 2

See Note 1

APPLICATION

I/O

Notes:

1.If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to implemented in case another device forces the signal. Refer to the Programming Tool documentation for recommended resistor values.

2.During the ICC session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor<1K). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1K or a reset man-

agement IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session.

3.The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual.

4.Pin 9 has to be connected to the OSC1 or OSCIN pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multioscillator capability need to have OSC2 grounded in this case.

Doc ID 7215 Rev 4

21/161

1

ST72651AR6

FLASH PROGRAM MEMORY (Cont’d)

4.6 ICP (In-Circuit Programming)

To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool.

Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).

When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see Figure 12). For more details on the pin locations, refer to the device pinout description.

4.7 IAP (In-Application Programming)

This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool).

This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). For example, it is possible to download code from the SPI, SCI, USB or CAN interface and program it in the Flash. IAP mode can be used to program any of the Flash

Table 6. FLASH Register Map and Reset Values

sectors except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.8 Related Documentation

For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual.

4.9 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write

Reset Value: 0000 0000 (00h)

7							0
0	0	0	0	0	0	0	0

This register is reserved for use by Programming Tool software. It controls the Flash programming and erasing operations.

	Address	Register	7	6	5	4	3	2	1	0
	(Hex.)	Label
	002Bh	FCSR
		Reset Value	0	0	0	0	0	0	0	0

22/161

Doc ID 7215 Rev 4

1

ST72651AR6

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.

5.2 MAIN FEATURES

■Enable executing 63 basic instructions

■Fast 8-bit by 8-bit multiply

■17 main addressing modes (with indirect addressing mode)

■Two 8-bit index registers

■16-bit stack pointer

■Low power HALT and WAIT modes

■Priority maskable hardware interrupts

■Non-maskable software/hardware interrupts

5.3 CPU REGISTERS

The six CPU registers shown in Figure 13 are not present in the memory mapping and are accessed by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

Index Registers (X and Y)

These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)

The Y register is not affected by the interrupt automatic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB).

Figure 13. CPU Registers

											7										0
																								ACCUMULATOR
														RESET VALUE = XXh
											7										0
																								X INDEX REGISTER
													RESET VALUE = XXh
											7										0
																								Y INDEX REGISTER
													RESET VALUE = XXh
					PCH			8					7				PCL				0			PROGRAM COUNTER
	15
	RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
											7										0
														1	1	I1	H	I0	N	Z	C			CONDITION CODE REGISTER
				RESET VALUE = 1											1	1 X		1 X		X	X
		15						8													0			STACK POINTER
												7

RESET VALUE = STACK HIGHER ADDRESS

X = Undefined Value

Doc ID 7215 Rev 4

23/161

1

ST72651AR6

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write

Reset Value: 111x1xxx

7							0
1	1	I1	H	I0	N	Z	C

The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.

These bits can be individually tested and/or controlled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.

This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions.

0:No half carry has occurred.

1:A half carry has occurred.

This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.

Bit 2 = N Negative.

This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.

0:The result of the last operation is positive or null.

1:The result of the last operation is negative (that is, the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instructions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.

0:The result of the last operation is different from zero.

1:The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test instructions.

Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.

0:No overflow or underflow has occurred.

1:An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt

The combination of the I1 and I0 bits gives the current interrupt software priority.

Interrupt Software Priority		I1	I0
Level 0	(main)	1	0
Level 1		0	1
Level 2		0	0
Level 3	(= interrupt disable)	1	1

These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more details.

24/161

Doc ID 7215 Rev 4

1

ST72651AR6

CENTRAL PROCESSING UNIT (Cont’d)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

15							8
0	0	0	0	0	0	0	1
7							0
SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0

The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 14).

Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.

Figure 14. Stack Manipulation Example

The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction.

Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.

The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 14.

–When an interrupt is received, the SP is decremented and the context is pushed on the stack.

–On return from interrupt, the SP is incremented and the context is popped from the stack.

A subroutine call occupies two locations and an interrupt five locations in the stack area.

CALL	Interrupt	PUSH Y	POP Y	IRET	RET
Subroutine	Event				or RSP

@ 0100h

SP

SP

SP

Y

CC

CC

CC

A

A

A

X

X

X

SP

PCH

PCH

PCH

SP

PCL

PCL

PCL

PCH

PCH

PCH

PCH

PCH

SP

@ 01FFh PCL

PCL

PCL

PCL

PCL

Stack Higher Address = 01FFh

Stack Lower Address = 0100h

Doc ID 7215 Rev 4

25/161

1

ST72651AR6

6 SUPPLY, RESET AND CLOCK MANAGEMENT

6.1 CLOCK SYSTEM

6.1.1 General Description

The MCU accepts either a 12 MHz crystal or an external clock signal to drive the internal oscillator. The internal clock (fCPU) is derived from the internal oscillator frequency (fOSC), which is 12 Mhz in Stand-alone mode and 48Mhz in USB mode.

The internal clock (fCPU) is software selectable using the CP[1:0] and CPEN bits in the MISCR1 register.

In USBVDD power supply mode, the PLL is active, generating a 48MHz clock to the USB. In this mode, fCPU can be configured to be up to 8 MHz. In VDD mode the PLL and the USB clock are disabled, and the maximum frequency of fCPU is 6 MHz.

The internal clock signal (fCPU) is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%.

The internal oscillator is designed to operate with an AT-cut parallel resonant quartz in the frequency range specified for fosc. The circuit shown in Figure 16 is recommended when using a crystal, and Table 7 lists the recommended capacitance. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time.

Table 7. Recommended			Values	for 12-MHz
Crystal Resonator
RSMAX	20 Ω		25 Ω		70 Ω
COSCIN	56pF		47pF		22pF
COSCOUT	56pF		47pF		22pF

Note: RSMAX is the equivalent serial resistor of the crystal (see crystal specification).

6.1.2 External Clock

An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure 15. The tOXOV specifications does not apply when using an external clock input. The equivalent specification of the external clock

source should be used instead of tOXOV (see Section 6.5 CONTROL TIMING).

Figure 15. External Clock Source Connections

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

Figure 16. Crystal Resonator

OSCIN OSCOUT

COSCIN

COSCOUT

26/161

Doc ID 7215 Rev 4

1

ST72651AR6

6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

The reset sequence manager includes three RESET sources as shown in Figure 6.2.2:

■External RESET source pulse

■Internal LVD RESET (Low Voltage Detection)

■Internal WATCHDOG RESET

These sources act on the RESET pin and it is always kept low during the delay phase.

The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.

Figure 17. RESET Sequences

The basic RESET sequence consists of 3 phases as shown in Figure 17:

■Active Phase depending on the RESET source

■Min 512 CPU clock cycle delay (see Figure 19 and Figure 20

■RESET vector fetch

Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behaviour.

VDD

VIT+(LVD)

VIT-(LVD)

	LVD	SHORT EXT.
	RESET	RESET
	RUN	RUN
	ACTIVE	ACTIVE
		PHASE

LONG EXT.		WATCHDOG
RESET		RESET
RUN	RUN	RUN
ACTIVE		ACTIVE
PHASE		PHASE

tw(RSTL)out

tw(RSTL)out

th(RSTL)in

th(RSTL)in

tw(RSTL)out

DELAY

EXTERNAL

RESET

SOURCE

RESET PIN

WATCHDOG

RESET

WATCHDOG UNDERFLOW

INTERNAL RESET (min 512 TCPU)

VECTOR FETCH

Doc ID 7215 Rev 4

27/161

1

ST72651AR6

RESET SEQUENCE MANAGER (Cont’d)

6.2.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.

A RESET signal originating from an external

source must have a duration of at least th(RSTL)in in order to be recognized. This detection is asynchro-

nous and therefore the MCU can enter reset state even in HALT mode.

The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.

If the external RESET pulse is shorter than

tw(RSTL)out (see short ext. Reset in Figure 17), the signal on the RESET pin will be stretched. Other-

wise the delay will not be applied (see long ext. Reset in Figure 17).

Figure 18. Reset Block Diagram

Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

6.2.3 Internal Low Voltage Detection RESET

Two different RESET sequences caused by the internal LVD circuitry can be distinguished:

■Power-On RESET

■Voltage Drop RESET

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT- (falling edge) as shown in Figure 17.

The LVD filters spikes on VDD shorter than tg(VDD) to avoid parasitic resets.

6.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 17.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.

VDD

INTERNAL

fCPU

RESET

RON

COUNTER

RESET

WATCHDOG RESET

PULSE

GENERATOR

LVD RESET

28/161

Doc ID 7215 Rev 4

1

ST72651AR6

RESET SEQUENCE MANAGER (Cont’d)

In stand-alone mode, the 512 CPU clock cycle delay allows the oscillator to stabilize and ensures that recovery has taken place from the Reset state.

Figure 19. Reset Delay in Stand-alone Mode

In USB mode the delay is 256 clock cycles counted from when the PLL LOCK signal goes high.

The RESET vector fetch phase duration is 2 clock cycles.

RESET
DELAY	512 x tCPU(STAND-ALONE)	FETCH VECTOR

Figure 20. Reset Delay in USB Mode

RESET
DELAY	256 x tCPU(STAND-ALONE)	PLL Startup	256 x tCPU(USB)	FETCH VECTOR
		time (undefined)
	400 µs typ.

Note: For a description of Stand-alone mode and USB mode refer to Section 6.4.

Doc ID 7215 Rev 4

29/161

1

ST72651AR6

6.3 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the VDDA supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down, keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when VDDA is below:

–VIT+ when VDDA is rising

–VIT- when VDDA is falling

The LVD function is illustrated in Figure 21.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.

Note: It is recommended to make sure that the VDDA supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly.

Figure 21. Low Voltage Detector vs Reset

VDDA

Vhyst

VIT+(LVD)

VIT-(LVD)

RESET

30/161

Doc ID 7215 Rev 4

1