ST ST7263B User Manual
查询ST7263B供应商
LOW SPEED USB 8-BIT MCU FAMILY WITH FLASH/ROM,
ST7263B
UP TO 512 BYTES RAM, 8-BIT ADC, WDG, TIMER, SCI
■ Memories
– 4, 8 or 16 Kbytes Program Memory: High
Density Flash (HDFlash) or ROM with Readout and Write Protection
– In-Application Programming (IAP) and In-Cir-
cuit programming (ICP) for HDFlash devices
– 384 or 512 bytes RAM memory (128-byte
stack)
■ Clock, Re set and Supp ly M a nagement
– Run, Wait, Slow and Halt CPU modes
– 12 or 24 MHz Oscillator
– RAM Retention mode
– Optional Low Voltage Detector (LVD)
■ USB (Universal Serial Bus) Interface
– DMA for low speed applications compliant
with USB 1.5 Mbs (version 1.1) and HID specifications (version 1.0)
– Integrated 3.3 V voltage regulator and trans-
ceivers
– Suspend and Resume operations
– 3 Endpoints with programmable In/Out config-
uration
■ 19 I/ O P o rts
– 8 high sink I/Os (10 mA at 1.3 V)
– 2 very high sink true open drain I/Os (25 mA
at 1.5 V)
– 8 lines individually programmable as interrupt
inputs
■ 2 Timers
– Programmable Watchdog
– 16-bit Timer with 2 Input Captures, 2 Output
Compares, PWM output and clock input
■ 2 Communication Interfaces
– Asynchronous Serial Communications Interface (on K4 and K2 versions only)
– I²C Multi Master Interface up to 400 kHz
(on K4 versions only)
■ 1 Analog Peripheral
– 8-bit A/D Converter (ADC) with 8 channels
■ Instruction Set
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
■ Development Tools
– Versatile Development Tools (under Win-
dows) including assembler, li nker, C-compiler, archiver, source level debugger, software
library, hardware emulator, programming
boards and gang programmers
PSDIP32
SO34 (Shrink)
& I²C
Table 1. Device Summary
Features
Program Memory -bytesRAM (stack) - bytes 512 (128) 384 (128)
Peripherals
Operating Supply 4.0 V to 5.5 V
CPU frequency 8 MHz (with 24 MHz oscillator) or 4 MHz (with 12 MHz oscillator)
Operating temperature 0 °C to +70 °C
Packages SO34/SDIP32
ST72F63BK4
16K
(Flash or FASTROM)
Watchdog timer, 16-bit tim-
er, SCI, I²C, ADC, USB
ST7263BK2 ST7263BK1
8K
(Flash, ROM or FASTROM)
Watchdog timer,
16-bit timer, SCI, ADC, USB
4K
(Flash, ROM or FASTROM)
Watchdog, 16-bit timer, ADC,
USB
Rev. 1.5
April 2003 1/132
1
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.1 INTERRUPT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8 POWER SAVIN G MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.3 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.4 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.1WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.216-BIT TIM ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.3SERIAL COMMUNICATIO NS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.4USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
11.5I²C BUS INTERFACE (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
11.68-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.2INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.1PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
13.2ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
132
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Table of Contents
13.3OPERATING CONDITIO NS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
13.4SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
13.5CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
13.6MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.7EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.8I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
13.9CONTROL PIN C HARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
13.10COMMUNICATION INTERF ACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 116
13.118-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.1PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.2THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
14.3SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 124
15.1OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
15.2DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
15.3DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
15.4ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
16.1UNEXPECTED R ESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
16.2HALT MODE POWER CONSUM PTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 130
17 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
To obtain the most recent version of this datasheet,
please check at www.st.com>products>technical literature>datasheet
Please also pay special attention to the Section “IMPORTANT NOTES” on page 130.
3/132
ST7263B
1 INTRODUCTION
The ST7263B Microcontrollers form a sub-family
of the ST7 MCUs dedicated to USB applications.
The devices are based on an industry-standard 8bit core and feature an enhanced instruction set.
They operate at a 24 MHz or 12 MHz oscillator frequency. Under software control, the ST7263B
MCUs may be placed in either Wait or Halt modes,
thus reducing power consumption. Th e enhance d
instruction set and ad dressing modes afford real
programming potential. In additio n to standard 8bit data management, the ST7263B MCUs feature
true bit manipulation, 8x8 unsigned multiplication
and indirect addressing modes. The devices include an ST7 Core, up to 16 K bytes of program
memory, up to 512 bytes of RAM, 19 I/O lines and
the following on-chip peripherals:
– USB low speed interface with 3 endpoints with
programmable in/out configuration using the
DMA architecture with embedded 3.3V voltage
regulator and transceivers (no external components are needed).
– 8-bit Analog-to-Digital converter (ADC) with 8
multiplexed analog inputs
Figure 1. General Block Diagram
INTERNAL
CLOCK
OSCIN
OSCOUT
V
V
RESET
DD
SS
OSCILLATOR
POWER
SUPPLY
WATCHDOG
CONTROL
8-BIT CO RE
ALU
LVD
USB DMA
OSC/3
OSC/4 or OSC/2
(for USB)
– Industry standard asynchronous SCI serial inter-
face (not on all products - see Table 1 Device
Summary)
– Watchdog
– 16-bit Timer featuring an External clock input, 2
Input Captures, 2 Output Compares with Pulse
Generator capabilit ies
– Fast I²C Multi Master interface (not on all prod-
ucts - see device summary)
– Low voltage reset (LVD) ensuring proper power-
on or power-off of the device
The ST7263B devices are ROM versions.
The ST72P63B devices are Factory Advanced
Service Technique ROM (FASTROM) versions:
they are fact ory-prog ra mmed and are not reprogrammable.
The ST72F63B d evices are Flash versions. They
support programming in IAP mode (In-application
programming) via the on-chip USB interface.
I²C*
PORT A
16-BI TTIMER
ADDRESS AND DATA BUS
PORT B
ADC
PORT C
SCI*
(UART)
PA[7:0]
(8 bits)
PB[7:0]
(8 bits)
PC[2:0]
(3 bits)
VPP/TEST
V
DDA
V
SSA
* Not on all products (refer to Tabl e 1: Device S um mary)
PROGRAM
MEMORY
(4K/8K/16K Byte s)
RAM
(384/512 Bytes)
4/132
USB SIE
USBDP
USBDM
USBVCC
2 PIN DESCRI PTION
Figure 2. 34-Pin SO Package Pinout
OSCOUT
OSCIN
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
AIN7/IT8PB7
AIN6/PB6/I T7
AIN5/IT6/PB5
AIN4/IT5/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1
* VPP on Flash versions only
(10mA)
(10mA)
VPP/TEST
(10mA)
(10mA)
(10mA)
(10mA)
(10mA)
ST7263B
V
DDA
V
DD
1
2
3
V
SS
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
USBVCC
USBDP
V
USBDM
SSA
PA0/MCO
PA1
(25mA)
/SDA/ICCDATA
NC
NC
NC
PA2
(25mA)
/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/OCMP1/IT3
PA7/OCMP2/IT4
PB0
(10mA)
/AIN0
Figure 3. 32-Pin SDIP Package Pinout
V
DD
OSCOUT
OSCIN
V
SS
PC2/USBOE
PC1/TDO
PC0/RDI
RESET
AIN7/IT8/PB7
AIN6/IT7/PB6
AIN5/IT6/PB5
AIN4/IT5/PB4
AIN3/PB3
AIN2/PB2
AIN1/PB1/
* VPP on Flash versions only
(10mA)
(10mA)
VPP/TEST*
(10mA)
(10mA)
(10mA)
(10mA)
(10mA)
10
11
12
13
14
15
16
V
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DDA
USBVCC
USBDM
USBDP
V
SSA
PA0/MCO
PA1
(25mA)
/SDA/ICCDATA
NC
NC
PA2
(25mA)
/SCL/ICCCLK
PA3/EXTCLK
PA4/ICAP1/IT1
PA5/ICAP2/IT2
PA6/COMP1/IT3
PA7/COMP2/IT4
PB0
(10mA)
/AIN0
5/132
ST7263B
PIN DESCRIPTION (Cont’d)
RESET
signal forces the initialization of the MCU. This
event is the top priority non maskable interrupt.
This pin is switched low when the Watchdog is triggered or the V
ternal peripherals.
OSCIN/OSCOUT: Input/Output Oscillator pin.
These pins connect a pa rallel-resonant crystal, or
an external source, to the on-chip oscillator.
V
Ground voltages.
V
Ground voltages for analog peripherals.
Table 2. Device Pin Description
(see Note 1): Bidirectional. This active low
is low. It can be used to reset ex-
DD
DD/VSS
DDA/VSSA
(see Note 2): Main Power Supply and
(see Note 2): Power Supply and
Alter na te Fu nct i ons : Several pins of the I/O ports
assume software programmable alternate functions as shown in the pin description.
Note 1: Adding two 100 nF decou pling capacitors
on the Reset pin (respectively connected to
V
DD
and VSS) will significantly improve product el ectromagnetic susceptibility performance.
Note 2: To enhance the reliability of operation, it is
recommended that
V
DDA
and V
be connected to-
DD
gether on the application bo ard. This also applies
V
to
and VSS.
SSA
Pin n°
Pin Name
SO34
SDIP32
11V
2 2 OSCOUT O Oscillator output
3 3 OSCIN I Oscillator input
44V
5 5 PC2/USBOE I/O C
6 6 PC1/TDO I/O C
7 7 PC0/RDI I/O C
8 8 RESET I/O X X Reset
-- 9 NC -- Not connected
9 10 PB7/AIN7/IT8 I/O C
10 11 PB6/AIN6/IT7 I/O C
11 12 V
12 13 PB5/AIN5/IT6 I/O C
13 14 PB4/AIN4/IT5 I/O C
14 15 PB3/AIN3 I/O C
15 16 PB2/AIN2 I/O C
16 17 PB1/AIN1 I/O C
17 18 PB0/AIN0 I/O C
18 19 PA7/OCMP2/IT4 I/O C
19 20 PA6/OCMP1/IT3 I/O C
20 21 PA5/ICAP2/IT2 I/O C
21 22 PA4/ICAP 1/IT1 I/O C
DD
SS
/TEST S Programming supply
PP
Level Port / Control
Input Output
Type
Input
Output
float
S Power supply voltage (4V - 5.5V)
S Digital ground
T
T
T
10mA X XX XPort B7 ADC analog input 7
T
10mA X XX XPort B6 ADC analog input 6
T
10mA X XX XPort B5 ADC analog input 5
T
10mA X XX XPort B4 ADC analog input 4
T
10mA X XXPort B3 ADC analog input 3
T
10mA X XXPort B2 ADC analog input 2
T
10mA X XXPort B1 ADC analog input 1
T
10mA X XXPort B0 ADC Analog Input 0
T
T
T
T
T
int
wpu
X X Port C2 USB Output Enable
X X Port C1 SCI Transmit Data Output*
X X Port C0 SCI Receive Data Input*
X XXPort A7 Timer Output Compare 2
X XXPort A6 Timer Output Compare 1
X XXPort A5 Timer Input Captu re 2
X XXPort A4 Timer Input Captu re 1
OD
ana
Main
Function
(after reset)
PP
Alternate Function
6/132
ST7263B
Pin n°
Pin Name
SO34
SDIP32
22 23 PA3/EXTCLK I/O C
23 24 PA2/SCL/ ICCC LK I/O C
-- 25 NC -- Not connected
24 26 NC -- Not connected
25 27 NC -- Not connected
26 28 PA1/SDA/ICCDATA I/O C
27 29 PA0/MCO I/O C
28 30 V
29 31 USBDP I/O USB bidirectional data (data +)
30 32 USBDM I/O USB bidirectional data (data -)
31 33 USBVCC O USB power supply
32 34 V
SSA
DDA
Level Port / Control
Input Output
Type
Input
Output
float
T
25mA X T Port A2 I²C serial clock*, ICC Clock
T
25mA X T Port A1 I²C serial data*, ICC Data
T
T
S Analog ground
S Analog supply voltage
int
wpu
X X Port A3 Timer External Clock
XXPort A0 Main Clock Output
OD
ana
Main
Function
(after reset)
PP
Alternate Function
Note (*): if the peripheral is present on the device (see Table 1, "Device Summary")
Legend / Abbreviations for Figure 2 and Table 2:
Type: I = input, O = output, S = supply
In/Output lev e l: C
= CMOS 0.3VDD/0.7VDD with input trigger
T
Output level: 10mA = 10mA high sink (on N-buffer only)
25mA = 25mA very high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
– Output : OD = open drain, PP = push-pull, T = True open drain
Refer to “I/O PORTS” on page 25 for more details on the software configuration of the I/O ports.
The RESET con fi g u r a ti o n o f e ac h pin is shown in bold. This configuration is kept as long as the device is
under reset state.
7/132
ST7263B
3 REGISTER & MEMORY MAP
As sho wn in Figure 4, the MCU is capable of ad-
dressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of up to
512 bytes of RAM including 64 bytes of register locations, and up to 16K bytes of user program
memory in which the upper 32 by tes are res erved
for interrupt vectors. The RAM space includes up
to 128 bytes for the stack from 0100h to 017Fh.
Figure 4. Me m ory Map
0000h
003Fh
0040h
01BF/023Fh
01C0/0240h
BFFFh
C000h
FFDFh
FFE0h
FFFFh
HW Registers
(See Table 4)
RAM
(384/512 Bytes)
Reserved
Program Memory*
(4/8/16 KBytes)
Interrupt & Reset Vectors
(See Table 3)
The highest address by tes contain the user re set
and interrupt vectors.
IMPORTANT: Memory locations noted “Reserved” must neve r be ac cess ed. A cce ssing a reserved area can have unpredictable effects on the
device.
0040h
00FFh
0100h
017Fh
0180h
01BF/023Fh
Short Addressing
RAM (192 bytes)
Stack
(128 Bytes)
16-bit Addressing
RAM
C000h
E000h
16 KBytes
8 KBytes
F000h
FFDFh
4 KBytes
* Program memory and RAM sizes are product dependent (see Tabl e 1, "Device Summar y")
Table 3. Interrupt Vector Map
Vector Address Description Masked by Remarks Exit from Halt Mode
FFE0h-FFEDh
FFEEh-FFEFh
FFF0h-FFF1h
FFF2h-FFF3h
FFF4h-FFF5h
FFF6h-FFF7h
FFF8h-FFF9h
FFFAh-FFFBh
FFFCh-FFFDh
FFFEh-FFFFh
USB End Suspend Mode Interrupt Vector
Flash Start Programming Interrupt Vector
TRAP (software) Interrupt Vector
Reserved Area
USB Interrupt Vector
SCI Interrupt Vector
I²C Interrupt Vector
TIMER Interrupt Vector
IT1 to IT8 Interrupt Vector
RESET Vector
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
I- bit
None
None
Internal Interrupt
Internal Interrupt
Internal Interrupt
Internal Interrupt
External Interrupt
External Interrupts
Internal Interrupt
CPU Interrupt
No
No
No
No
Yes
Yes
Yes
No
Yes
8/132
ST7263B
Table 4. Hardware Register Memory Map
Address Block Register Label Register name Reset Status Remarks
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h ITC ITIFRE Interrupt Register 00h R/W
0009h MISC MISCR Miscellaneous Register 00h R/W
000Ah
000Bh
000Ch WDG WDGCR Watchdog Control Register 7Fh R/W
000Dh
to
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
Port A
Port B
Port C
ADC
TIM
SCI
1)
PADR
PADDR
PBDR
PBDDR
PCDR
PCDDR
ADCDR
ADCCSR
TCR2
TCR1
TSR
TIC1HR
TIC1LR
TOC1HR
TOC1LR
TCHR
TCLR
TACHR
TACLR
TIC2HR
TIC2LR
TOC2HR
TOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
Port A Data Register
Port A Data Direction Register
Port B Data Register
Port B Data Direction Register
Port C Data Register
Port C Data Direction Register
Reserved (2 Bytes)
ADC Data Register
ADC control Status register
Reserved (4 bytes)
Timer Control Register 2
Timer Control Register 1
Timer Status Register
Timer Input Capture High Register 1
Timer Input Capture Low Register 1
Timer Output Compare High Register 1
Timer Output Compare Low Register 1
Timer Counter High Register
Timer Counter Low Register
Timer Alternate Counter High Register
Timer Alternate Counter Low Register
Timer Input Capture High Register 2
Timer Input Capture Low Register 2
Timer Output Compare High Register 2
Timer Output Compare Low Register 2
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
00h
00h
00h
00h
1111 x000b
1111 x000b
00h
00h
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
C0h
xxh
00h
x000 0000b
00h
R/W
R/W
R/W
R/W
R/W
R/W
Read only
R/W
R/W
R/W
Read only
Read only
Read only
R/W
R/W
Read only
R/W
Read only
R/W
Read only
Read only
R/W
R/W
Read only
R/W
R/W
R/W
R/W
9/132
ST7263B
Address Block Register Label Register name Reset Status Remarks
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h to
0036h
0032h
0036h
0037h Flash FCSR Flash Control /Status Register 00h R/W
0038h Reserved (1 byte)
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
USB
I²C
1)
USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
I2CDR
I2COAR
I2CCCR
I2CSR2
I2CSR1
I2CCR
USB PID Register
USB DMA address Register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
Reserved (5 bytes)
Reserved (5 Bytes)
I²C Data Register
Reserved
I²C (7 Bits) Slave Address Register
I²C Clock Control Register
I²C 2nd Status Register
I²C 1st Status Register
I²C Control Register
x0h
xxh
x0h
00h
00h
06h
00h
0000 xxxxb
80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb
00h
00h
00h
00h
00h
00h
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
R/W
Note 1. If the peripheral is present on the device (see Table 1, "Device Summary")
10/132
4 FLASH PROGRAM MEMORY
ST7263B
4.1 In troduction
The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external V
supply.
PP
The HDFlash devices can be programmed and
erased off-board (plugge d in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).
The array matrix organ isation allows each sector
to be erased and reprogrammed wi thout affecting
other sectors.
4.2 Main Features
■ Three Flash programming modes:
– Insertion in a programming tool. In this mode,
all sectors including option bytes can be programmed or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be programmed or erased without removing the device from the application board.
– IAP (In-Application Programming) In this
mode, all sectors except Sector 0, can be programmed or erased without removing the device from the appli cation board a nd while the
application is running.
■ ICT (In-Circuit Testing) for downloading and
executing user application test patterns in RAM
■ Read-out protection against piracy
■ Register Access Security System (RASS) to
prevent accidental programming or erasing
4.3 S tructure
Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Tab le 5). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash m emory when only a
partial erasing is required.
The first two sectors have a fixed size of 4 K bytes
(see Figure 5). They are mapped in the upper part
of the ST7 addressing space so the res et and interrupt vectors are located in Sector 0 (F000hFFFFh).
Table 5. Sectors available in Flash devices
Flash Size (bytes) Available Sectors
4K Sector 0
8K Sectors 0,1
> 8K Sectors 0,1, 2
4.3.1 Read-out Protection
Read-out protection, when sele cted, makes it impossible to extract the m emory content from the
microcontroller, thus preventing piracy. Even ST
cannot access the user code.
In flash devices, this prot ection is removed by reprogramming the option. In this case, the entire
program memory is first automatically erased.
Read-out protection selection depends on the device type:
– In Flash devices it is enabled and removed
through the FMP_R bit in the option byte.
– In ROM devices it is enabled by mask option
specified in the Option List.
The Flash memory is organised in sectors and can
be used for both code and data storage.
Figure 5. Me m ory Map and Sec t or A dd re ss
4K 10K 24K 48K
1000h
3FFFh
7FFFh
9FFFh
BFFFh
D7FFh
DFFFh
EFFFh
FFFFh
8K 16K 32K 60K
2Kbytes
8Kbytes 40 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
24 Kbytes
FLASH
MEMORY SIZE
SECTOR 2
52 Kby t es
SECTOR 1
SECTOR 0
11/132
ST7263B
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICC Interface
ICC needs a m ini mum of 4 and up t o 6 pins to b e
connected to the programming tool (see Figure 6).
These pins are:
– RESET
–V
: device reset
: device power supply ground
SS
Figure 6. Typical ICC Interface
PROGRAMMING TOOL
APPLICATION
POWER SUPPLY
OPTIONAL
(See Note 3)
C
L2
DD
V
OSC2
OPTIONAL
(See Note 4)
C
L1
OSC1
ST7
Notes:
1. If the ICCCLK or ICCDATA pins are only use d
as outputs in the application, no sign al iso lation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented i n case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the application reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate th e application RESET circuit in th is case. When using a
classical RC network with R>1K or a reset management IC with open drain output and pul l-up resistor>1K, no additional com ponents are needed.
pin. This can lead to con-
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V
: programming voltage
PP
– OSC1(or OSCIN): main clock in put for exter-
nal source (optional)
: application board power supply (opt ion-
–V
DD
al, see Figure 6, Note 3)
ICC CONNECTOR
975 3
10k
Ω
SS
V
ICCSEL/VPP
ICC Cabl e
RESET
ICCCLK
HE10 CONNECTOR TYPE
1
246810
ICCDATA
APPLICATION BOARD
ICC C ONNECTOR
APPLICATION
RESET SOURCE
See Note 2
See Notes 1 and 5
See Note 1
APPLICATION
I/O
In all cases the user must ensure that no external
reset is generated by the application during the
ICC session.
3. The use of Pin 7 of the ICC connec tor depends
on the Programming Tool architecture. This pin
must be connected when using most ST Programming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.
4. Pin 9 has to be connec ted to the OSC1 or OS CIN pin of the ST7 when the clock is not available
in the application or if the sel ected clock opt ion is
not programmed in t he option byte. ST7 devices
with multi-oscillator capability need to hav e OS C2
grounded in this case.
5. During normal operation, the ICCCLK pin m ust
be pulled-up, internally or externally, to avoid entering ICC mode unexpectedly during a reset.
12/132
FLASH PROGRAM MEMORY (Cont’d)
ST7263B
4.5 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.
Depending on the ICP code downloade d in RAM,
Flash memory programming can be fully customized (number of bytes to prog ram, program locations, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supp orts ICP and the specific microcontroller device, the user needs only to
implement the ICP hardware interface on the application board (see Figure 6). For more details on
the pin locations, refer to the device pinout description.
4.6 IAP (In-Application Programming)
This mode uses a BootLoader program previously
stored in Sector 0 by the user (in IC P mode or by
plugging the device in a programming tool).
This mode is fully controlled by user software. This
allows it to be adapted to the user application, (user-defined strategy for entering programming
mode, choice of c om mun ications protoc ol used t o
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI, USB
or CAN interface and program it in the F lash. IAP
mode can be used to program any of the Flash
sectors except Sector 0, whi ch is write/erase protected to allow recovery in case erro rs occur during the programming operation.
4.6.1 Register Description
FLASH CONTROL/STATUS REGISTER (FCSR)
Read/Write
Reset Value: 0000 0000 (00h)
70
00000000
This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations. For details on customizing
Flash programming method s and In-Circuit Testing, refer to the ST7 Flash Programming Reference Manual.
13/132
ST7263B
5 CENTRAL PROCE SSI NG UNIT
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FEATURES
■ 63 basic instructions
■ Fast 8-bit by 8-bit multiply
■ 17 main addressing modes
■ Two 8-bit index registers
■ 16-bit stack pointer
■ Low power modes
■ Maskable hardware interrupts
■ Non-maskable software interrupt
5.3 CPU REGISTERS
The 6 CPU registers shown in Figure 7 are not
present in the memory mapping and are accessed
by specific instructions.
Figure 7. CPU Registers
70
RESET VALUE = XXh
70
RESET VALUE = XXh
70
RESET VALUE = XXh
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operan ds and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from
the stack).
Program Cou nt er (P C )
The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
15 8
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
15
RESET VALUE = STACK HIGHER ADDRESS
14/132
PCH
RESET VALUE =
7
70
1C11HI NZ
1X11X1XX
70
8
PCL
0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
X = Undefined Value
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
70
111HINZC
The 8-bit Condition Code register c ontains the interrupt mask and four flags represent ative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
because the I bi t is set by hardware at the start of
the routine and reset by the IRET instruction at the
end of the routine. If the I bit is cleared by software
in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the current interrupt routine.
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmeti c,
logical or data manipulation. It is a copy of the 7
bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instruc-
Bit 4 = H
Half carry
.
tions.
This bit is set by hardware when a carry occurs between bits 3 and 4 of t he ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructi ons.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is us eful in BCD arithmetic subroutines .
Bit 1 = Z
This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from
zero.
1: The result of the last operation is zero.
Zero
.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 3 = I
Interrupt mask
This bit is set by hardware when entering in interrupt or by software to disable all interrup ts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are
latched and can be processed whe n I is cleared.
.
Bit 0 = C
Carry/borrow.
This bit is set and cleared b y hardware and software. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.
By default an interrupt routine is not in terruptable
ST7263B
th
15/132
ST7263B
CPU REGISTERS (Cont’d)
STACK POINTER (SP)
Read/Write
Reset Value: 017Fh
15 8
00000001
70
0 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 8).
Since the stack is 128 bytes deep, the 9 most significant bits are forced by hardw are. Following a n
MCU Reset, or after a Reset Stack Pointe r instruction (RSP), the Stack Pointer contains its reset value (the SP6 to SP0 bits are set) which is the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, wi thout indicating the s tack overflow. The previously
stored information is then o ve rwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the retu rn address during a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored
at the first location point ed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 8.
– When an interrupt is received, the SP is decre-
mented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented
and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locat ions i n the sta ck ar ea.
Figure 8. Stack Manipulation Example
@ 0100h
SP
@ 017Fh
CALL
Subroutine
SP
PCH
PCL
Stack Higher Address = 017Fh
Stack Lower Address =
Interrupt
Event
SP
CC
A
X
PCH
PCL
PCH
PCL
0100h
PUSH Y POP Y IRET
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
RET
or RSP
SP
16/132
6 RESET AND CLO CK MANAGEMENT
6.1 RESET
ST7263B
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage
(LVD) reset, a watchdog reset and an external reset at the RESET
pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution startin g
from this point.
6.1.3 External Reset
The external reset is an active low input signal applied to the RESET pin of the MCU.
As shown in Figure 12, the RESET
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET
vided to improve noise immunity.
Figure 9. Low Voltage Detector functional Diagram
An internal circuitry provides a 4096 CPU clock cycle delay from the time that the oscillator becomes
active.
LOW VOLTAGE
DETECTOR
6.1.1 Low Voltage Detector (LVD)
V
DD
Low voltage reset circuitry generates a reset when
V
is:
DD
■ below V
■ below V
During low voltage reset, the RESET
when VDD is rising,
IT+
when VDD is falling.
IT-
pin is held low,
thus permitting the MCU to reset other devices.
The Low Voltage Detector can be disabled by set-
Figure 10. Low Voltage Reset Signal Output
WATCHDOG
V
IT+
ting bit 3 of the option byte.
V
DD
6.1.2 Watchdog Reset
When a watchdog res et oc curs, the RESET
pulled low permitting the MCU to reset other devic-
pin is
RESET
es in the same way as t he low voltage reset ( Fi g-
ure 9).
Note: Hysteresis (V
Figure 11. Temporization timing diagram after an internal Reset
FROM
RESET
IT+-VIT-
) = V
signal must
hys
pin is pro-
RESET
INTERNAL
RESET
V
IT-
V
DD
Addresses
V
IT+
Temporiz ation (40 96 CPU clock cycles)
$FFFE
17/132
ST7263B
RESET (Cont’d)
Figure 12. Reset Timing Diagram
t
DDR
V
DD
OSCIN
t
OXOV
f
CPU
PC
RESET
WATCHDOG RESET
Note: Refer to Electrical Characteristics for values of t
4096 CPU
CYCLES
, t
DDR
CLOCK
DELAY
OXOV
FFFE
, V
IT+
, V
IT-
FFFF
and V
hys
18/132
6.2 CLOCK SYSTEM
ST7263B
6.2.1 General Description
The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (f
rived from the external oscillator frequency (f
CPU
) is de-
OSC
which is divided by 3 (and by 2 or 4 for USB, depending on the externa l clock used). The internal
clock is further divided by 2 by setting the SMS bit
in the Miscellaneous Register.
Using the OSC24/12 bit in the option byte, a 12
MHz or a 24 MHz external clock can b e used to
provide an internal frequency of either 2, 4 or 8
MHz while maintaining a 6 MHz for the USB (re f er
to Figure 15).
The internal clock signal (f
) is also routed to
CPU
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
The internal oscillat or is designed to operate with
an AT-cut parallel resonant quartz or ceramic resonator in the frequency range specified for f
osc
The circuit shown in Figure 14 is recommended
when using a crystal, and Tab le 6, "Recomme nd-
ed Values for 24 MHz Crystal Resonator" list s the
recommended capacitance. The crystal and associated components should be mounted as close as
possible to the input pins in order to minimize output distortion and start-up stabilisation time.
source should be used instead of t
OXOV
tion 6.5 CONTROL TIMING).
Figure 13. External Clock Source Connections
),
OSCIN
EXTERNAL
CLOCK
OSCOUT
NC
Figure 14. Crystal/Ceramic Resonator
.
OSCIN OSCOUT
R
P
C
OSCIN
C
OSCOUT
(see Sec-
Table 6. Recommended Values for 24 MHz
Crystal Resonator
R
SMAX
C
OSCIN
C
OSCOUT
R
P
Note: R
crystal (see crystal specification).
SMAX
20
Ω
56pF 47pF 22pF
56pF 47pF 22pF
1-10 M
Ω
25
1-10 M
Ω
Ω
70
1-10 M
Ω
Ω
is the equivalent serial resistor of the
6.2.2 External Clock
An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as
shown on F igure 13. The t
specifications do
OXOV
not apply when using an external clock input. The
equivalent specification of the external clock
Figure 15. Clock Block Diagram
%2
1
0
OSC24/12
%2
%2
24 or
12 MHz
Crystal
%3
%2
8, 4 or 2 MHz
0
CPU and
peripherals)
1
SMS
6 MHz (USB)
19/132
ST7263B
7 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as
listed in Table 7, "Interrupt Mapping" and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 16.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec tion) .
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– The I bit of the CC register is set to prevent addi-
tional interrupts.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
Table 7, "Interrupt Mapping" for vector address-
es).
The interrupt service routine should finish with the
IRET instruction which c auses the con tents o f the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared a nd the main pro gram will
resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case several interrupts are simultaneously
pending, a hardware priority defines which one will
be serviced first (see Table 7, "Interrupt Map-
ping").
Non-maskable Software Interrupts
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 16.
Interrupts a n d Low Power Mod e
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific mentioned interrupts allow the processor to leave the
Halt low power mode (refer to t he “Exit f rom HALT“
column in Table 7, "Interrupt Mapping").
External Interrupts
The pins ITi/PAk and ITj/P Bk (i=1,2; j= 5,6; k=4,5)
can generate an i nterrupt when a rising edge occurs on this pin. Conversely, the ITl/PAn and ITm/
PBn pins (l=3,4; m= 7,8; n=6,7) can generate an
interrupt when a falling edge occurs on this pin.
Interrupt generation will occur if it is enabl ed with
the ITiE bit (i=1 to 8) in the ITRFRE register and if
the I bit of the CCR is reset.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
register.
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by one of the
two following operations:
– Writing “0” to the corresponding bit in the status
register.
– Accessing the status register while the flag is set
followed by a read or write of an associated register.
Notes:
1. The clearing sequence resets the internal latch.
A pending interrupt (i.e. waiting to be enabled) will
therefore be lost if the clear sequence is executed.
2. All interrupts allow the processor to leave the
Wait low power mode.
3. Exit from Halt mode may only be triggered by an
External Interrupt on one of the ITi ports (PA4-PA7
and PB4-PB7), an end suspend mode Interrupt
coming from USB peripheral, or a reset.
20/132
INTERRUPTS (Cont’d)
Figure 16. I nt errupt Proces s in g Flowchart
FROM RESET
ST7263B
EXECUTE INSTRUCTION
Table 7. Int errupt Mapping
N°
Source
Block
BIT I SET
FETCH NEXT INSTRUCTION
N
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
IRET
Description
Y
Y
N
Register
Label
N
INTERRUPT
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
Priority
Order
Exit
from
HALT
Vector
Address
RESET Reset
TRAP Software Interrupt no FFFCh-FFFDh
N/A
Highest
Priority
yes FFFEh-FFFFh
FLASH Flash Start Programming Interrupt yes FFFAh-FFFBh
USB End Suspend Mode ISTR
1 ITi External Interrupts ITRFRE FFF6h-FFF7h
yes
2 TIMER Timer Peripheral Interrupts TIMSR
3 I²C I²C Peripheral Interrupts
4 SCI SCI Peripheral Interr upts SCISR FFF0h-FFF1h
I²CSR1
I²CSR2
Lowest
Priority
no
FFF8h-FFF9h
FFF4h-FFF5h
FFF2h-FFF3h
5 USB USB Peripheral Interrupts ISTR FFEEh-FFEFh
21/132
ST7263B
INTERRUPTS (Cont’d)
7.1 Interrupt Register
INTERRUPTS REGISTER (ITRFRE)
Address: 0008h — Read/Write
Reset Value: 0000 0000 (00h)
70
IT8E IT7E IT6E IT5E IT4E IT3E IT2 E IT1E
Bit 7:0 = ITiE (i=1 to 8).
Bits
.
Interrupt Enable Control
If an ITiE bit is se t, the corresponding interrupt is
generated when
– a rising edge occurs on the pin PA4/IT1 or PA5/
IT2 or PB4/IT5 or PB5/IT6
or
– a falling edge occurs on the pin PA6/IT3 or PA7/
IT4 or PB6/IT7 or PB7/IT8
No interrupt is generated elsewhere.
Note: Analog input must be disabled for interrupts
coming from port B.
22/132
8 POWER SAVIN G MO DES
8.1 In troduction
ST7263B
To give a large measure of flexibility to the application in terms of power consumption, two main power saving modes are implemented in the ST7.
After a RESET, the normal operating mode is selected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 (f
CPU
).
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
8.2 HALT Mode
The MCU consumes the least amount of power i n
HALT mode. The HALT mode is entered by executing the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals.
When entering HALT mode, the I bit in th e Condition Code Register is cleared. Thus, all external interrupts (ITi or USB end suspend mode) are allowed and if an interrupt occurs, the CPU clock becomes active.
The MCU can exit HALT m ode on reception of either an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillat or is t hen t urned on and a stabilization time is provided before rele asing CPU operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues operation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 17. HAL T Mode Flow C hart
HALT INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
RESET
N
EXTERNAL
INTERRUPT*
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
OFF
OFF
OFF
CLEARED
Y
ON
ON
ON
SET
Note: Before servicing an interrupt, the CC register is
pushed on the stac k. T he I -Bit i s se t du ring the interrupt routine and cleared when the CC register is
popped.
23/132
ST7263B
POWER SAVING MODES (Cont’d)
8.3 SLOW Mode
In Slow mode, the oscillator frequency can be d ivided by 2 as selected by the SMS bit in the Miscellaneous Register. The CPU and peripherals are
clocked at this lower frequency. Slow mode is
used to reduce power consump tion, and enables
the user to adapt the clock frequency to the available supply voltage.
8.4 WAIT Mode
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This pow er s av in g mode is s elected b y calling th e
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is f orced t o 0 to enable
all interrupts. All other registers and mem ory remain unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occu rs, where upon the Program Counter branc hes to the starting
address of the interrupt or Reset service routine.
The MCU will r e main in W AIT mod e unt il a Rese t
or an Interrupt occurs, causing it to wake up.
Refer to Figure 18.
Figure 18. WAIT Mode Flow Chart
WFI INSTRUCTION
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
N
INTERRUPT
Y
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
RESET
ON
ON
OFF
CLEARED
Y
ON
ON
ON
SET
24/132
IF RESET
4096 CPU CLOCK
CYCLES DELAY
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note: Before servicing an interrupt, the CC register is
pushed on the sta ck. The I-Bit is s et d uring the inte rrupt routine and cleared when the CC register is
popped.
9 I/O PORTS
9.1 In troduction
ST7263B
The I/O ports offer different functional modes:
– Transfer of data through digital inputs and out-
puts and for specific pins
– Analog signal input (ADC)
– Alternate signal input/output for the on-chip pe-
ripherals
– External interrupt generation
An I/O port consists o f up to 8 p ins. Each pin can
be programmed independently as a digital input
(with or without interrupt generation) or a digital
output.
9.2 Functional description
Each port is associated to 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/O pin may be programmed using the corre-
sponding register bits in DDR register: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.
Table 8. I/O Pin Functi ons
DDR MODE
0 Input
1 Output
Inpu t Mode s
The input configuration is sele cted by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Note 1: All the inputs are triggered by a Schmitt
trigg er.
Note 2: When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is configured as an output.
Interrupt function
When an I/O is configured as an Input with Interrupt, an event on this I/O can generate an external
Interrupt request to the CPU. The interrupt sensi-
tivity is given independent ly according to the description mentioned in the ITRFRE interrupt register.
Each pin can independently generate an Interrupt
request.
Each external interrupt vector is linked t o a dedicated group of I/O port pins (see Interrupts section). If more than one input pin is selected simultaneously as an interrupt source, this is logically
ORed. For this reason if one of the interrupt pins is
tied low, the other ones are masked.
Output Mode
The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).
In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Therefore, t he prev i ously saved value is restored when the DR register is read.
Note: The interrupt function is disabled in this
mode.
Digital Alternate Func ti on
When an on-chip peripheral is configured to use a
pin, the alternate function is au tomatically selected. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).
When the signal is goi ng to an on-chip peripheral,
the I/O pin ha s to be configured in i nput mode. In
this case, the pin’s state is a lso digitally readable
by addressing the DR register.
Notes:
1. Input pull-up configuration can cause an unex pected value at the input of the alternate peripheral input.
2. When the on-chip peripheral uses a pin as input
and output, this pin must be configured as an input
(DDR = 0).
Warning
: The alternate func tion m us t not be a cti-
vated as long as the p in is config ured as an input
with interrupt in order to avoid generating spurious
interrupts.
25/132
ST7263B
I/O PORTS (Cont ’d)
Analog Alternate Function
When the pin is used as an ADC input the I/O must
be configured as a floating input. The analog mu ltiplexer (controlled by the ADC registers) switches
the analog voltage present o n the selected pin to
the common ana log rail which i s c onnect ed to the
ADC input.
It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it i s recommended not to
have clocking pins locat ed close t o a selected analog pin.
Warning
within the limits stat ed in the A bsolute Max imum
Ratings.
9.3 I/O Port Implementation
The hardware implementation on each I/O port depends on the settings in the DDR register and specific feature of the I/O port such as ADC Input or
true open drain.
: The analog input voltage level must be
26/132
I/O PORTS (Cont ’d)
9.3.1 Port A
Table 9. Port A0, A3, A4, A5, A6, A7 Description
ST7263B
PORT A
Input* Output Signal Condition
I / O Alternate Function
PA0 with pull-up push-pull MCO (Main Clock Output) MCO = 1 (MISCR)
PA3 with pull-up push-pull Timer EXTCLK
PA4 with pull-up
PA5 with pull-up
PA6 with pull-up
PA7 with pull-up
push-pull
push-pull
push-pull
push-pull
Timer ICAP1
IT1 Schmitt triggered input IT1E = 1 (ITIFRE)
Timer ICAP2
IT2 Schmitt triggered input IT2E = 1 (ITIFRE)
Timer OCMP1 OC1E = 1
IT3 Schmitt triggered input IT3E = 1 (ITIFRE)
Timer OCMP2 OC2E = 1
IT4 Schmitt triggered input IT4E = 1 (ITIFRE)
CC1 =1
CC0 = 1 (Timer CR2)
*Reset State
Figure 19. PA0, PA3, PA4, PA5, PA6, PA7 Configuration
ALTERNATE ENABLE
ALTERNATE
OUTPUT
1
0
V
DD
P-BUFFER
DATA BUS
DR SEL
ALTERNATE INPUT
DR
LATCH
DDR
LATCH
DDR SEL
V
PULL-UP
ALTERNATE ENABLE
N-BUFFER
1
0
ALTERNATE ENABLE
CMOS SCHMITT TRIGGER
V
SS
DD
PAD
DIODES
27/132
ST7263B
I/O PORTS (Cont ’d)
Table 10. PA1, PA2 Description
PORT A
Input* Output Signal Condition
I / O Alternate Function
PA1 without pull-up Very High Current open drain SDA (I²C data) I²C enable
PA2 without pull-up Very High Current open drain SCL (I²C clock) I²C enable
*Reset State
Figure 20. PA1, PA2 Configuration
ALTERNATE ENABLE
ALTERNATE
OUTPUT
DR
LATCH
DDR
LATCH
DATA BUS
DDR SEL
1
0
PAD
DR SEL
N-BUFFER
1
0
ALTERNATE ENABLE
CMOS SCHMITT TRIGGER
V
SS
28/132
ST7263B
I/O PORTS (Cont ’d)
9.3.2 Port B
Table 11. Port B Description
PORT B I/O Alternate Function
Input* Output Signal Condition
PB0 without pull-up push-pull Analog input (ADC) CH[2:0] = 000 (ADCCSR)
PB1 without pull-up push-pull Analog input (ADC) CH[2:0] = 001 (ADCCSR)
PB2 without pull-up push-pull Analog input (ADC) CH[2:0]= 010 (ADCCSR)
PB3 without pull-up push-pull Analog input (ADC) CH[2:0]= 011 (ADCCSR)
PB4 without pull-up push-pull
PB5 without pull-up push-pull
PB6 without pull-up push-pull
PB7 without pull-up push-pull
*Reset State
Figure 21. Port B C onfi guration
ALTERNATE EN AB L E
ALTERN AT E
OUTPUT
DR
LATCH
DDR
COMMON ANALOG RAIL
DATA BUS
LATCH
1
0
ANALOG ENABLE
(ADC)
Analog input (ADC) CH[2:0]= 100 (ADCCS R)
IT5 Schmitt triggered input IT4E = 1 (ITIFRE)
Analog input (ADC) CH[2:0]= 101 (ADCCS R)
IT6 Schmitt triggered input IT5E = 1 (ITIFRE)
Analog input (ADC) CH[2:0]= 110 (ADCCS R)
IT7 Schmitt triggered input IT6E = 1 (ITIFRE)
Analog input (ADC) CH[2:0]= 111 (ADCCS R)
IT8 Schmitt triggered input IT7E = 1 (ITIFRE)
V
DD
P-BUFFER
ALTERNATE ENABLE
V
DD
PAD
ALTERN AT E IN PUT
DDR SEL
DR SEL
ANALOG
SWITCH
N-BUFF ER
1
0
DIGITA L EN AB L E
ALTERNATE ENABLE
V
SS
DIODES
29/132
ST7263B
I/O PORTS (Cont ’d)
9.3.3 Port C
Table 12. Port C Description
PORT C
I / O Alternate Function
Input* Output Signal Condition
PC0 with pull-up push-pull RDI (SCI input)
PC1 with pull-up push-pull TDO (SCI output) SCI enable
PC2 with pull-up push-pull
USBOE (USB output enable)
USBOE =1
(MISCR)
*Reset State
Figure 22. P ort C Conf i gu ra ti on
ALTERNATE ENABLE
ALTERNATE
OUTPUT
DR
LATCH
DATA BUS
DDR
LATCH
DDR SEL
1
0
PULL-UP
ALTERNATE EN AB L E
V
DD
P-BUFFER
V
DD
PAD
ALTERNATE INPUT
30/132
DR SEL
N-BUFFER
1
0
ALTERN ATE ENABLE
CMOS SCHMITT TRIGGER
V
SS
DIODES
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