ST ST72623F2, ST72621K4, ST72622L2, ST72621L4, ST72621J4 User Manual

ST7262xxx

PDIP32 shrinkSO34 shrink

LQFP44 PDIP42 shrink

SO20 PDIP20

Low speed USB 8-bit MCU with 3 endpoints, Flash or

ROM memory, LVD, WDG, 10-bit ADC, 2 timers, SCI, SPI

Features

■ Memories

– 8 or 16 Kbyte Program memory

(ROM or Dual voltage FLASH)
with read-write protection

– In-Application and In-Circuit Programming for

FLASH versions

– 384 to 768 bytes RAM (128-byte stack)

■ Clock, Reset and Supply Management

– Enhanced Reset System (Power On Reset)
– Low Voltage Detector (LVD)
– Clock-out capability
– 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal

frequencies)

– 3 Power saving modes

■ USB (Universal Serial Bus) Interface

– DMA for low speed applications compliant

with USB specification (version 2.0):

– Integrated 3.3V voltage regulator and trans-

ceivers
– Suspend and Resume operations
– 3 Endpoints

■ Up to 31 I/O Ports

– Up to 31 multifunctional bidirectional I/O lines
– Up to 12 External interrupts (3 vectors)
– 13 alternate function lines
– 8 high sink outputs

(8 mA@0.4 V/20 mA@1.3 V)
– 2 true open drain pins (N buffer 8 mA@0.4 V)

■ 3 Timers

– Configurable watchdog timer (8 to 500 ms

timeout)
– 8-bit Auto Reload Timer (ART) with 2 Input

Captures, 2 PWM outputs and External Clock
– 8-bit Time Base Unit (TBU) for generating pe-

riodic interrupts cascadable with ART

Device Summary

Features ST72623F2 ST72621K4 ST72622L2 ST72621L4 ST72621J4

Program memory - Kbytes 8 16 8 16 16
RAM (stack) - bytes 384 (128) 768 (128) 384 (128) 768 (128) 768 (128)
Peripherals USB, Watchdog, Low Voltage Detector, 8-bit Auto-Reload timer, Timebase unit, A/D Converter
Serial I/O - SPI + SCI SPI SPI + SCI
I/Os 11212331
Operating Supply 4.0V to 5.5V (Low voltage 3.0V to 5.5V ROM versions available)
Operating Temperature 0°C to +70°C
Packages PDIP20/SO20 PDIP32 SO34 PDIP42/LQFP44

■ Analog Peripheral

– 10-bit A/D Converter with up to 8 input pins.

■ 2 Communications Interfaces

– Asynchronous Serial Communication inter-

face

– Synchronous Serial Peripheral Interface

■ Instruction Set

– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation

■ Nested interrupts

■ Development Tools

– Full hardware/software development package

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1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 PCB LAYOUT RECOMMENDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.7 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.8 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

9.3 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10.2 PWM AUTO-RELOAD TIMER (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.3 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

10.6 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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Table of Contents

10.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

11 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

11.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

11.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

12 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

12.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

12.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

12.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

12.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

12.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

12.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

12.10TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

12.11COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 117

12.1210-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

13 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

14 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 128

14.1 OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 128

14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

14.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

15 IMPORTANT NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.1 A/ D CONVERTER ACCURACY FOR FIRST CONVERSION . . . . . . . . . . . . . . . . . . . . 135

15.2 A/D CONVERTER CONVERSION SPEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

15.3 SCI WRONG BREAK DURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.4 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

15.5 HALT MODE POWER CONSUMPTION WITH ADC ON . . . . . . . . . . . . . . . . . . . . . . . . . 136

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

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ST7262xxx

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSCIN

OSCOUT

RESET

PORT B

USB SIE

PORT A

SCI

PORT C

SPI

PB7:0

(8 bits)

PC7:0

(8 bits)

OSCILLATOR

Internal
CLOCK

CONTROL

RAM

(384,

PA7:0

(8 bits)

V

SS

V

DD

POWER
SUPPLY

PROGRAM

(8 or 16K Bytes)

LVD

10-BIT ADC

MEMORY

WATCHDOG

USBDP

USBDM

USBVCC

PWM ART

USB DMA

V

SSA

V

DDA

PORT D

PD6:0
(7 bits)

TIME BASE UNIT

V

PP

or 768 Bytes)

1 INTRODUCTION

The ST7262 and ST72F62 devices are members
of the ST7 microcontroller family designed for USB
applications.

All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc­tion set.

The ST7262 devices are ROM versions.
The ST72F62 versions feature dual-voltage

FLASH memory with FLASH Programming capa­bility.

Under software control, all devices can be placed
in WAIT, SLOW, or HALT mode, reducing power

Figure 1. General Block Diagram

consumption when the application is in idle or
standby state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

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2 PIN DESCRIPTION

44 43 42 41 40 39 38 37 36 35 34

33
32
31
30
29
28
27
26
25
24
23

12 13 14 15 16 17 18

19 20 21 22

1
2
3
4
5
6
7
8
9
10
11

38
37
36
35
34
33
32
31
30
29
28
27

16

15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

39

40

41

42

PD6
PD5

OSCOUT

OSCIN

IT9 / PC2

IT10 / SCK / PC3

IT11 / SS

/ PC4

IT12 / MISO / PC5

MOSI / PC6

PD1

V

PP

PD2

PD3

PD4

PC7

PD0

V

DDA

USBVCC

PB1 (HS) / RDI

PB0 (HS) / MCO

PA7 / AIN7

PA6 / AIN6

PA5 / AIN5

PA4 / AIN4

PA3 / AIN3 / IT4

PA0 / AIN0 / IT1 / USBOE

RESET

V

SSA

USBDM

USBDP

PA1 / AIN1 / IT2
PA2 / AIN2 / IT3

21

20

17
18
19

IT8 / PWM1 / PB7 (HS)

PC0

PC1

V

DD

V

SS

26
25
24
23
22

PB6 (HS) / PWM0 / IT7 / ICCDATA

PB5 (HS) / ARTIC2 / IT6 / ICCCLK

PB4 (HS) / ARTIC1 / IT5

PB3 (HS) / ARTCLK

PB2 (HS) / TDO

OSCOUT

OSCIN

IT9 / PC2

IT10 / SCK / PC3

IT11 / SS

/ PC4

IT12 / MISO / PC5

MOSI / PC6

PD1

V

PP

PC7

PD0

IT8 / PWM1 / PB7

PC0

PC1

V

DD

V

SS

ARTCLK / PB3 (HS)

IT5 / ARTIC1 / PB4 (HS)

ICCCLK / IT6 / ARTIC2 / PB5 (HS)

ICCDATA /IT7 / PWM0 / PB6 (HS)

N.C.

TDO / PB2 (HS)

PB1 (HS) / RDI

PB0 (HS) / MCO

PA7 / AIN7

PA6 / AIN6

PA5 / AIN5

PA4 / AIN4

PA3 / AIN3 / IT4

PA0 / AIN0 / IT1 / USBOE

RESET

PA1 / AIN1 / IT2

PA2 / AIN2 / IT3

V

DDA

USBVCC

V

SSA

USBDM

USBDP

PD3

PD4

Reserved*

PD6

PD5

PD2

* Pin 39 of the LQFP44 package
must be left unconnected.

Figure 2. 44-pin LQFP and 42-Pin SDIP Package Pinouts

ST7262xxx

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ST7262xxx

28
27
26
25
24
23
22
21
20
19
18

29

30

31

32

PC4 / SS / INT11
PC5 / MISO / IT12

PA4 / AIN4

PA3 / AIN3 / IT4

PA2 / AIN2 / IT3

PA1 / AIN1 / IT2

PA0 / AIN0 / IT1 / USBOE

V

SSA

USBDM

USBVCC

V

DDA

V

PP

RESET

PC6 / MOSI

USBDP

PC7

16

15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

IT10 / SCK / PC3

IT9 / PC2

AIN7 / PA7

MCO / PB0 (HS)

RDI / PB1 (HS)

TDO / PB2 (HS)

ARTCLK / PB3 (HS)

IT5 / ARTIC1 / PB4 (HS)

ICCCLK / IT6 /ARTIC2 / PB5 (HS)

IT8 / PWM1 / PB7 (HS)

V

DD

V

SS

OSCOUT

OSCIN

ICCDATA / IT7 / PWM0 / PB6 (HS)

PA5 / AIN5

AIN6 / PA6

33

34

17

28
27
26
25
24
23
22
21
20
19
18
17

16

15

1
2
3
4
5
6
7
8
9
10
11
12
13
14

29

30

31

32

IT10 / SCK / PC3

IT9 / PC2

AIN7 / PA7

MCO / PB0 (HS)

RDI / PB1 (HS)

TDO / PB2 (HS)

ARTCLK / PB3 (HS)

IT5 / ARTIC1 / PB4 (HS)

ICCCLK / IT6 / ARTIC2 / PB5 (HS)

IT8 / PWM1 / PB7 (HS)

V

DD

V

SS

OSCOUT

OSCIN

ICCDATA / IT7 / PWM0 / PB6 (HS)

AIN6 / PA6

PC4 / SS

/ INT11

PC5 / MISO / IT12

PA4 / AIN4

PA3 / AIN3 / IT4

PA2 / AIN2 / IT3

PA1 / AIN1 / IT2

PA0 / AIN0 / IT1 / USBOE

V

SSA

USBDM

USBVCC

V

DDA

V

PP

RESET

PC6 / MOSI

USBDP

PA5 / AIN5

PC1

PIN DESCRIPTION (Cont’d)

Figure 3. 34-Pin SO and 32-Pin SDIP Package Pinouts

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Figure 4. 20-pin SO20 Package Pinout

14
13
12
11

15

16

17

18

OSCIN

OSCOUT

PB7 (HS) / PWM1 / IT8

PB6 (HS) / PWM0 / IT7/ ICCDATA

USBVCC

V

DD

V

PP

USBDP

1
2
3
4
5
6
7
8
9

10

IT3 / AIN2 / PA2

PB0 (HS) / MCO
PB1 (HS)
PB2 (HS)
PB3 (HS) / ARTCLK
PB4 (HS) / ARTIC1 / IT5

RESET

IT2 / AIN1 / PA1

19

20

USBOE/ IT1 / AIN0/ PA0

V

SS

USBDM

PB5 (HS) / ARTIC2 / IT6 / ICCCLK

14
13
12
11

15

16

17

18

OSCIN

OSCOUT

PB7 (HS) / PWM1 / IT8

PB6 (HS) / PWM0 / IT7/ICCDATA

USBVCC

V

DD

V

PP

USBDP

1
2
3
4
5
6
7
8
9

10

IT5 / ARTIC1 / PB4 (HS)

MCO / PB0 (HS)

PB1 (HS)

PB2 (HS)

RESET

IT2 / AIN1/ PA1

19

20

USBOE / IT1 / AIN0 / PA0

V

SS

USBDM

PB5 (HS) / ARTIC2 / IT6 / ICCCLK

IT3 / AIN2 / PA2

ARTCLK / PB3 (HS)

Figure 5. 20-pin DIP20 Package Pinout

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ST7262xxx

PIN DESCRIPTION (Cont’d)

Legend / Abbreviations:

Type: I = Input, O = Output, S = Supply
Input level: A = Dedicated analog input
Input level: C = CMOS 0.3V

= CMOS 0.3VDD/0.7VDD with input trigger

C

T

Output level: HS = High Sink (on N-buffer only)
Port configuration capabilities:

– Input:float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge

ana = analog

– Output: OD = open drain, T = true open drain (N buffer 8mA@0.4 V), PP = push-pull

Table 1. Device Pin Description

/0.7VDD,

DD

),

Pin n°

DIP42

LQFP44

SO34

SO20

DIP32

Pin Name

DIP20

Level Port / Control

Input Output

Type

Input

Output

float

wpu

int

ana

OD

Main

Function

(after

reset)

PP

Alternate Function

FLASH programming voltage

1 6 29 28 9 14 V

PP

Sx

(12V), must be tied low in user
mode.

27----PD1 I/OC

38----PD0 I/OC

4931---PC7 I/OC

5 103230 - - PC6/MOSI I/OC

T

T

T

T

xxPort D1

xxPort D0

xxPort C7

xxPort C6

SPI Master Out /
Slave In

SPI Master In /

6 11 33 31 - - PC5/MISO/IT12 I/O C

T

xx xPort C5

Slave Out 1) /
Interrupt 12 input

SPI Slave Select

7 123432 - - PC4/SS

/IT11 I/O C

T

xx xPort C4

(active low) 1)/
Interrupt 11 input

8 13 1 1 - - PC3/SCK/IT10 I/O C

9142 2 - -PC2/IT9 I/OC

10 15 3 3 11 16 OSCIN

T

T

xx xPort C3

xx xPort C2 Interrupt 9 input

These pins are used connect an

SPI Serial Clock
Interrupt 10 input

external clock source to the on-

11 16 4 4 12 17 OSCOUT

12 17 5 5 4 9 V

13 18 6 6 8 13 V

SS

DD

14 19 7 - - - PC1 I/O C

1520----PC0 I/OC

S Digital Ground Voltage

S

T

T

PB7/PWM1/IT8/

16 21 8 7 13 18

RX_SEZ/DA-

I/O C

T

TAOUT/DA9

xTPort C1

xTPort C0

HS x \ x Port B7

chip main oscillator.

Digital Main Power Supply Volt­age

ART PWM output 1/
Interrupt 8 input

17 - - N.C. Not Connected

1)

1)

/

8/139

Doc ID 6996 Rev 5

ST7262xxx

Pin n°

DIP42

LQFP44

SO34

SO20

DIP32

Pin Name

DIP20

Level Port / Control

Input Output

Type

Input

Output

float

wpu

int

ana

OD

Main

Function

(after

reset)

PP

Alternate Function

ART PWM output 0/

18 22 9 8 14 19

PB6/PWM0/IT7/
ICCDATA

I/O C

HS x \ x Port B6

T

Interrupt 7 input/In­Circuit Communica­tion Data

ART Input Capture 2/

19 23 10 9 15 20

PB5/ARTIC2/IT6/
ICCCLK

I/O C

HS x / x Port B5

T

Interrupt 6 input/
In-Circuit Communi­cation Clock

20 24 11 10 16 1 PB4/ARTIC1/IT5 I/O C

21 25 12 11 17 2 PB3/ARTCLK I/O C

22 26 13 12 18 3 PB2/TDO I/O C

HS x / x Port B4

T

HS x x Port B3 ART Clock input

T

HS x x Port B2

T

23 27 14 13 19 4 PB1/RDI I/O CTHS x x Port B1

ART Input Capture
1/Interrupt 5 input

SCI Transmit Data

1)

Output
SCI Receive Data

1)

Input

24 28 15 14 20 5 PB0/MCO I/O CTHS x x Port B0 CPU clock output

25 29 16 15 - - PA7/AIN7 I/O C

26 30 17 16 - - PA6/AIN6 I/O C

27 31 18 17 - - PA5/AIN5 I/O C

28 32 19 18 - - PA4/AIN4 I/O C

29 33 20 19 - - PA3/AIN3/IT4 I/O C

30 34 21 20 1 6 PA2/AIN2/IT3 I/O C

31 35 22 21 2 7 PA1/AIN1/IT2 I/O C

32 36 23 22 3 8

33 37 30 29 10 15 RESET

34 38 24 23 - - V

PA0/AIN0/IT1/
USBOE

SSA

I/O C

I/O C

S

T

T

T

T

T

T

T

T

xxxPort A7 ADC Analog Input 7

xxxPort A6 ADC Analog Input 6

xxxPort A5 ADC Analog Input 5

xxxPort A4 ADC Analog Input 4

x\xxPort A3

x\xxPort A2

x\xxPort A1

ADC Analog Input 3/
Interrupt 4 input

ADC Analog Input 2/
Interrupt 3 input

ADC Analog Input 1/
Interrupt 2 input

ADC Analog Input 0/

x\xxPort A0

Interrupt 1 input/
USB Output Enable

Top priority non maskable inter­rupt (active low)

Analog Ground Voltage, must
be connected externally to V

SS

35 39 25 24 5 10 USBDM I/O USB bidirectional data (data -)

36 40 26 25 6 11 USBDP I/O USB bidirectional data (data +)

37 41 27 26 7 12 USBVCC S USB power supply 3.3V output

Analog Power Supply Voltage,

38 42 28 27 - - V

DDA

S

must be connected externally to

.

V

DD

39-----Reserved Must be left unconnected.

401----PD6 I/OC

412----PD5 I/OC

423----PD4 I/OC

T

T

T

xxPort D6

xxPort D5

xxPort D4

.

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ST7262xxx

14
13
12
11

15

16

17

18

USBVCC
USBDP

1
2
3
4
5
6
7
8
9

10

19

20

USBDM

USB Connector

Ground

Ground

ST7262

1.5KOhm pull-up resistor

Pin n°

Pin Name

DIP42

LQFP44

SO34

SO20

DIP32

DIP20

434----PD3 I/OC

445----PD2 I/OC

Level Port / Control

Input Output

Type

Input

Output

T

T

wpu

float

xxPort D3

xxPort D2

int

ana

OD

Main

Function

(after

reset)

PP

Note 1: Peripheral not present on all devices. Refer to “Device Summary” on page 1.

2.1 PCB LAYOUT RECOMMENDATION

In the case of DIP20 devices the user should lay­out the PCB so that the DIP20 ST7262 device and
the USB connector are centered on the same axis
ensuring that the D- and D+ lines are of equal
length. Refer to Figure 6

Figure 6. Recommended PCB Layout for USB Interface with DIP20 package

Alternate Function

10/139

Doc ID 6996 Rev 5

3 REGISTER & MEMORY MAP

0000h

Program Memory

Interrupt & Reset Vectors

HW Registers

BFFFh

0040h

003Fh

(see Table 2)

C000h

FFDFh
FFE0h

FFFFh

(see Table 6)

0340h

Reserved

033Fh

Short Addressing
RAM (zero page)

or Stack

017Fh

0040h

00FFh

768 Bytes RAM

E000h

8 KBytes

(128 Bytes)

16 KBytes

384 Bytes RAM

64 Bytes

01BFh

16-bit Addressing

RAM

Short Addressing
RAM (zero page)

017Fh

0040h

00FFh

448 Bytes

033Fh

16-bit Addressing

RAM

16-bit Addressing

RAM

or Stack

(128 Bytes)

16-bit Addressing

RAM

192 Bytes

192 Bytes

ST7262xxx

As shown in the Figure 7, the MCU is capable of
addressing 64K bytes of memories and I/O regis­ters.

The available memory locations consist of 64
bytes of register locations, 768 bytes of RAM and
up to 16 Kbytes of user program memory. The
RAM space includes up to 128 bytes for the stack
from 0100h to 017Fh.

The highest address bytes contain the user reset
and interrupt vectors.

Figure 7. Memory Map

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re­served area can have unpredictable effects on the
device.

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ST7262xxx

Table 2. Hardware Register Map

Address Block

0000h
0001h

0002h
0003h

0004h
0005h

0006h
0007h

Port A

Port B

Port C

Port D

Register

Label

PADR
PADDR

PBDR
PBDDR

PCDR
PCDDR

PDDR
PDDDR

Register Name

Port A Data Register
Port A Data Direction Register

Port B Data Register
Port B Data Direction Register

Port C Data Register
Port C Data Direction Register

Port D Data Register
Port D Data Direction Register

Reset

Status

1)

00h

00h

1)

00h

00h

1)

00h

00h

1)

00h

00h

0008h ITRFRE1 Interrupt Register 1 00h R/W

0009h MISC Miscellaneous Register 00h R/W

000Ah
000Bh
000Ch

ADC

ADCDRMSB
ADCDRLSB
ADCCSR

ADC Data Register (bit 9:2)
ADC Data Register (bit 1:0)
ADC Control Status Register

00h
00h
00h

000Dh WDG WDGCR Watchdog Control Register 7Fh R/W

000Eh
0010h

0011h
0012h
0013h

SPI

SPIDR
SPICR
SPICSR

SPI Data I/O Register
SPI Control Register
SPI Control Status Register

Reserved Area (3 Bytes)

xxh
0xh
00h

Remarks

2)

R/W

2)

R/W

2)

R/W

2)

R/W

2)

R/W

2)

R/W

2)

R/W

2)

R/W

Read Only
Read Only
R/W

R/W
R/W
Read Only

0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch

001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h

PWM ART

SCI

PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2

SCIERPR
SCIETPR

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2

PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ART Input Capture Control/Status Register
ART Input Capture Register 1
ART Input Capture Register 2

SCI Extended Receive Prescaler register
SCI Extended Transmit Prescaler Register
Reserved Area
SCI Status register
SCI Data register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2

00h
00h
00h
00h
00h
00h
00h
00h
00h

00h
00h

--

C0h

xxh
00h

x000 0000b

00h

R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only

R/W
R/W

Read Only
R/W
R/W
R/W
R/W

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Doc ID 6996 Rev 5

ST7262xxx

Address Block

0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h

0032h

to

0035h

0036h
0037h

0038h FLASH FCSR Flash Control/Status Register 00h R/W

0039h ITRFRE2 Interrupt Register 2 00h R/W

003Ah

to

003Fh

USB

TBU

Register

Label

USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB

TBUCV
TBUCSR

Register Name

USB PID Register
USB DMA Address register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B

Reserved Area (4 Bytes)

TBU Counter Value Register
TBU Control/Status Register

Reserved Area (6 Bytes)

Reset

Status

x0h
xxh
x0h
00h
00h
06h
00h

0000 xxxxb

80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb

00h

00h

Remarks

Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

R/W
R/W

Legend: x=undefined, R/W=read/write
Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura­tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always be kept at their reset value.

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ST7262xxx

4 Kbytes

4 Kbytes

2Kbytes

SECTOR 1
SECTOR 0

16 Kbytes

SECTOR 2

8K 16K 32K 60K

FLASH

FFFFh

EFFFh

DFFFh

3FFFh

7FFFh

1000h

24 Kbytes

MEMORY SIZE

8 Kbytes 40 Kbytes

52 Kbytes

9FFFh

BFFFh

D7FFh

4K 10K 24K 48K

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

The ST7 dual voltage High Density Flash
(HDFlash) is a non-volatile memory that can be
electrically erased as a single block or by individu­al sectors and programmed on a Byte-by-Byte ba­sis using an external V

supply.

PP

The HDFlash devices can be programmed and
erased off-board (plugged in a programming tool)
or on-board using ICP (In-Circuit Programming) or
IAP (In-Application Programming).

The array matrix organisation allows each sector
to be erased and reprogrammed without affecting
other sectors.

4.2 MAIN FEATURES

■ 3 Flash programming modes:

– Insertion in a programming tool. In this mode,

all sectors including option bytes can be pro­grammed or erased.

– ICP (In-Circuit Programming). In this mode, all

sectors including option bytes can be pro­grammed or erased without removing the de­vice from the application board.

– IAP (In-Application Programming) In this

mode, all sectors except Sector 0, can be pro­grammed or erased without removing the de­vice from the application board and while the
application is running.

■ ICT (In-Circuit Testing) for downloading and

executing user application test patterns in RAM

■ Read-out protection

■ Register Access Security System (RASS) to

prevent accidental programming or erasing

4.3 STRUCTURE

The Flash memory is organised in sectors and can
be used for both code and data storage.

Depending on the overall Flash memory size in the
microcontroller device, there are up to three user
sectors (see Table 3). Each of these sectors can
be erased independently to avoid unnecessary
erasing of the whole Flash memory when only a
partial erasing is required.

The first two sectors have a fixed size of 4 Kbytes
(see Figure 8). They are mapped in the upper part
of the ST7 addressing space so the reset and in­terrupt vectors are located in Sector 0 (F000h­FFFFh).

Table 3. Sectors available in Flash devices

Flash Size (bytes) Available Sectors

4K Sector 0
8K Sectors 0,1

> 8K Sectors 0,1, 2

4.3.1 Read-out Protection

Read-out protection, when selected, provides a
protection against Program Memory content ex­traction and against write access to Flash memo­ry. Even if no protection can be considered as to­tally unbreakable, the feature provides a very high
level of protection for a general purpose microcon­troller.

In Flash devices, this protection is removed by re­programming the option. In this case, the entire
program memory is first automatically erased and
the device can be reprogrammed.

Read-out protection selection depends on the de­vice type:

– In Flash devices it is enabled and removed

through the FMP_R bit in the option byte.

– In ROM devices it is enabled by mask option

specified in the Option List.

Figure 8. Memory Map and Sector Address

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Doc ID 6996 Rev 5

FLASH PROGRAM MEMORY (Cont’d)

ICC CONNECTOR

ICCDATA

ICCCLK

RESET

V

DD

HE10 CONNECTOR TYPE

APPLICATION
POWER SUPPLY

1

246810

975 3

PROGRAMMING TOOL

ICC CONNECTOR

APPLICATION BOARD

ICC Cable

(See Note 3)

10kΩ

V

SS

ICCSEL/VPP

ST7

C

L2

C

L1

OSC1

OSC2

OPTIONAL

See Note 1

See Note 2

APPLICATION
RESET SOURCE

APPLICATION

I/O

(See Note 4)

ST7262xxx

4.4 ICC INTERFACE

ICC (In-Circuit Communication) needs a minimum
of four and up to six pins to be connected to the
programming tool (see Figure 9). These pins are:

– RESET
–V

: device reset

: device power supply ground

SS

Figure 9. Typical ICC Interface

– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input/output serial data pin
– ICCSEL/V

: programming voltage

PP

– OSC1(or OSCIN): main clock input for exter-

nal source (optional)

: application board power supply (see Fig-

–V

DD

ure 9, Note 3)

Notes:

1. If the ICCCLK or ICCDATA pins are only used
as outputs in the application, no signal isolation is
necessary. As soon as the Programming Tool is
plugged to the board, even if an ICC session is not
in progress, the ICCCLK and ICCDATA pins are
not available for the application. If they are used as
inputs by the application, isolation such as a serial
resistor has to implemented in case another de­vice forces the signal. Refer to the Programming
Tool documentation for recommended resistor val­ues.

2. During the ICC session, the programming tool
must control the RESET
flicts between the programming tool and the appli­cation reset circuit if it drives more than 5mA at
high level (push pull output or pull-up resistor<1K).
A schottky diode can be used to isolate the appli­cation RESET circuit in this case. When using a
classical RC network with R > 1K or a reset man-

pin. This can lead to con-

Doc ID 6996 Rev 5

agement IC with open drain output and pull-up
resistor > 1K, no additional components are need­ed. In all cases the user must ensure that no exter­nal reset is generated by the application during the
ICC session.

3. The use of Pin 7 of the ICC connector depends
on the Programming Tool architecture. This pin
must be connected when using most ST Program­ming Tools (it is used to monitor the application
power supply). Please refer to the Programming
Tool manual.

4. Pin 9 has to be connected to the OSC1 or OS­CIN pin of the ST7 when the clock is not available
in the application or if the selected clock option is
not programmed in the option byte. ST7 devices
with multioscillator capability need to have OSC2
grounded in this case.

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ST7262xxx

FLASH PROGRAM MEMORY (Cont’d)

4.5 ICP (IN-CIRCUIT PROGRAMMING)

To perform ICP the microcontroller must be
switched to ICC (In-Circuit Communication) mode
by an external controller or programming tool.

Depending on the ICP code downloaded in RAM,
Flash memory programming can be fully custom­ized (number of bytes to program, program loca­tions, or selection serial communication interface
for downloading).

When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe­cific microcontroller device, the user needs only to
implement the ICP hardware interface on the ap­plication board (see Figure 9). For more details on
the pin locations, refer to the device pinout de­scription.

4.6 IAP (IN-APPLICATION PROGRAMMING)

This mode uses a BootLoader program previously
stored in Sector 0 by the user (in ICP mode or by
plugging the device in a programming tool).

This mode is fully controlled by user software. This
allows it to be adapted to the user application, (us­er-defined strategy for entering programming
mode, choice of communications protocol used to
fetch the data to be stored, etc.). For example, it is
possible to download code from the SPI, SCI or
other type of serial interface and program it in the
Flash. IAP mode can be used to program any of
the Flash sectors except Sector 0, which is write/
erase protected to allow recovery in case errors
occur during the programming operation.

4.7 RELATED DOCUMENTATION

For details on Flash programming and ICC proto­col, refer to the ST7 Flash Programming Refer-

ence Manual and to the ST7 ICC Protocol Refer­ence Manual

.

4.8 REGISTER DESCRIPTION

FLASH CONTROL/STATUS REGISTER (FCSR)

Read/Write
Reset Value: 0000 0000 (00h)

70

00000000

This register is reserved for use by Programming
Tool software. It controls the Flash programming
and erasing operations.

16/139

Doc ID 6996 Rev 5

5 CENTRAL PROCESSING UNIT

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

STACK POINTER

CONDITION CODE REGISTER

PROGRAM COUNTER

70

1C1I1HI0NZ

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

70

70

70

0

7

15 8

PCH

PCL

15

8

70

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE =

1X11X1XX

RESET VALUE = XXh

RESET VALUE = XXh

RESET VALUE = XXh

X = Undefined Value

ST7262xxx

5.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

5.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 10. CPU Registers

5.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

These 8-bit registers are used to create effective
addresses or as temporary storage areas for data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol­lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto­matic procedures.

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

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ST7262xxx

CENTRAL PROCESSING UNIT (Cont’d)

Condition Code Register (CC)

Read/Write
Reset Value: 111x1xxx

70

11I1HI0NZ

C

The 8-bit Condition Code register contains the in­terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Arithmetic Management Bits

Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs be-

tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instructions.

0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines.

Bit 2 = N Negative.
This bit is set and cleared by hardware. It is repre-

sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-

th

sult 7

bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

Bit 1 = Z Zero.

This bit is set and cleared by hardware. This bit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.
Bit 0 = C Carry/borrow.

This bit is set and cleared by hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

Interrupt Management Bits

Bit 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the cur-

rent interrupt software priority.

Interrupt Software Priority I1 I0

Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more
details.

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Doc ID 6996 Rev 5

CPU REGISTERS (Cont’d)

PCH
PCL

SP

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

PCL

PCH

X

A

CC

PCH
PCL

SP

SP

Y

CALL

Subroutine

Interrupt

Event

PUSH Y POP Y IRET

RET

or RSP

@ 017Fh

@ 0100h

Stack Higher Address = 017Fh
Stack Lower Address =

0100h

STACK POINTER (SP)

Read/Write
Reset Value: 017Fh

15 8

00000001

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with­out indicating the stack overflow. The previously
stored information is then overwritten and there­fore lost. The stack also wraps in case of an under­flow.

The stack is used to save the return address dur­ing a subroutine call and the CPU context during

70

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.

The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).

Since the stack is 128 bytes deep, the 9 most sig­nificant bits are forced by hardware. Following an

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in­terrupt five locations in the stack area.

MCU Reset, or after a Reset Stack Pointer instruc­tion (RSP), the Stack Pointer contains its reset val­ue (the SP6 to SP0 bits are set) which is the stack
higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

ST7262xxx

Figure 11. Stack Manipulation Example

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ST7262xxx

OSCIN

OSCOUT

EXTERNAL

CLOCK

NC

OSCIN

OSCOUT

C

OSCIN

C

OSCOUT

6 CLOCKS AND RESET

6.1 CLOCK SYSTEM

6.1.1 General Description

The MCU accepts either a Crystal or Ceramic res­onator, or an external clock signal to drive the in­ternal oscillator. The internal clock (f

rived from the external oscillator frequency (f

CPU

) is de-

OSC

by dividing by 3 and multiplying by 2. By setting the
OSC12/6 bit in the option byte, a 12 MHz external
clock can be used giving an internal frequency of 8
MHz while maintaining a 6 MHz clock for USB (re­fer to Figure 14).

The internal clock signal (f

) consists of a

CPU

square wave with a duty cycle of 50%.
It is further divided by 1, 2, 4 or 8 depending on the

Slow Mode Selection bits in the Miscellaneous
register (SMS[1:0])

The internal oscillator is designed to operate with
an AT-cut parallel resonant quartz or ceramic res­onator in the frequency range specified for f

osc

The circuit shown in Figure 13 is recommended
when using a crystal, and Table 4 lists the recom­mended capacitors. The crystal and associated
components should be mounted as close as pos­sible to the input pins in order to minimize output
distortion and start-up stabilization time.

6.1.2 External Clock input

An external clock may be applied to the OSCIN in­put with the OSCOUT pin not connected, as
shown on Figure 12. The t
does not apply when using an external clock input.

),

specifications

OXOV

The equivalent specification of the external clock
source should be used instead of t

OXOV

trical Characteristics).

6.1.3 Clock Output Pin (MCO)

The internal clock (f

) can be output on Port B0

CPU

by setting the MCO bit in the Miscellaneous regis­ter.

Figure 12. External Clock Source Connections

.

(see Elec-

Table 4. Recommended Values for 12 MHz
Crystal Resonator

R

SMAX

C

OSCIN

C

OSCOUT

R

P

Note: R
crystal (see crystal specification).

SMAX

20 Ω 25 Ω 70 Ω

56pF 47pF 22pF
56pF 47pF 22pF

1-10 MΩ 1-10 MΩ 1-10 MΩ

is the equivalent serial resistor of the

Note: When a crystal is used, and to not over­stress the crystal, ST recommends to add a serial
resistor on the OSCOUT pin to limit the drive level
in accordance with the crystal manufacturer’s
specification. Please also refer to Section 12.5.4.

20/139

Figure 13. Crystal/Ceramic Resonator

Doc ID 6996 Rev 5

Figure 14. Clock block diagram

to CPU and

f

CPU

8/4/2/1 MHz

6 MHz (USB)

12 or

peripherals

%2

0

1

OSC12/6

6 MHz

Crystal

x2

Slow

Mode

%

SMS[1:0]

1/2/4/8

%3

(or 4/2/1/0.5 MHz)

MCO pin

LOW VOLTAGE

V

DD

FROM

WATCHDOG

RESET

RESET

INTERNAL

RESET

RESET

6.2 RESET

ST7262xxx

The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.

Three reset modes are provided: a low voltage re­set, a watchdog reset and an external reset at the
RESET

pin.

A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.

An internal circuitry provides a 514 CPU clock cy­cle delay from the time that the oscillator becomes
active.

Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom­mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.

6.2.1 Low Voltage Reset

Low voltage reset circuitry generates a reset when

is:

V

DD

■ below V

■ below V

During low voltage reset, the RESET

when VDD is rising,

IT+

when VDD is falling.

IT-

pin is held low,

thus permitting the MCU to reset other devices.

Notes:

The Low Voltage Detector can be disabled by set­ting the LVD bit of the Option byte.

It is recommended to make sure that the V
voltage rises monotonously when the device is ex­iting from Reset, to ensure the application functions
properly.

6.2.2 Watchdog Reset

When a watchdog reset occurs, the RESET
pulled low permitting the MCU to reset other devic­es as when low voltage reset (Figure 15).

6.2.3 External Reset

The external reset is an active low input signal ap­plied to the RESET

pin of the MCU.
As shown in Figure 18, the RESET
stay low for a minimum of one and a half CPU
clock cycles.

An internal Schmitt trigger at the RESET
vided to improve noise immunity.

Figure 15. Low Voltage Reset functional Diagram

Doc ID 6996 Rev 5

supply

DD

pin is

signal must

pin is pro-

21/139

ST7262xxx

RESET

V

DD

V

IT+

V

IT-

V

DD

Addresses

$FFFE

Temporization

V

IT+

(514 CPU clock cycles)

V

DD

OSCIN

f

CPU

FFFF

FFFE

PC

RESET

t

DDR

t

OXOV

514 CPU

CLOCK

CYCLES

DELAY

Figure 16. Low Voltage Reset Signal Output

Note: Typical hysteresis (V

IT+-VIT-

) of 250 mV is expected.

Figure 17. Temporization Timing Diagram after an internal Reset

Figure 18. Reset Timing Diagram

Note: Refer to Electrical Characteristics for values of t

22/139

Doc ID 6996 Rev 5

DDR

, t

OXOV

, V

IT+

and V

IT-.

ST7262xxx

RESET

R

ON

V

DD

WATCHDOG RESET

LVD RESET

INTERNAL
RESET

PULSE

GENERATOR

200ns

Filter

t

w(RSTL)out

+ 128 f

OSC

delay

Figure 19. Reset Block Diagram

Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Doc ID 6996 Rev 5

23/139

ST7262xxx

“IRET”

RESTORE PC, X, A, CC

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TLI

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Y

N

Y

N

Y

N

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

Interrupt has a higher

software priority

than current one

EXECUTE

INSTRUCTION

INTERRUPT

7 INTERRUPTS

7.1 INTRODUCTION

The CPU enhanced interrupt management pro­vides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level
management:

– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI

This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest­ed) CPU interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 5). The process­ing flow is shown in Figure 20.

When an interrupt request has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers
of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.

Table 5. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main)
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

Low

High

10

Figure 20. Interrupt Processing Flowchart

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Doc ID 6996 Rev 5

INTERRUPTS (Cont’d)

PENDING

SOFTWARE

Different

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

ST7262xxx

Servicing Pending Interrupts

As several interrupts can be pending at the same
time, the interrupt to be taken into account is deter­mined by the following two-step process:

– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware
priority is serviced first.

Figure 21 describes this decision process.

Figure 21. Priority Decision Process

When an interrupt request is not serviced immedi­ately, it is latched and then processed when its
software priority combined with the hardware pri­ority becomes the highest one.

Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci­sion process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex­ternal or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see

Figure 20). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding
vector is loaded in the PC register and the I1 and
I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit
HALT mode.

■ TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI service routine.

■

TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord­ing to the flowchart in Figure 20 as a TLI.
Caution: TRAP can be interrupted by a TLI.

■ RESET

The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high­est hardware priority.
See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vector sources can be serviced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC register). If any of these two condi­tions is false, the interrupt is latched and thus re­mains pending.

■ External Interrupts

External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the ITRFRE2 register.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
these will be logically NANDed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se­quence is executed.

Doc ID 6996 Rev 5

25/139

ST7262xxx

MAIN

IT4

IT2

IT1

TLI

IT1

MAIN

IT0

I1

HARDWARE PRIORITY

SOFTWARE

3
3
3
3
3
3/0

3

11
11
11
11
11

11 / 10

11

RIM

IT2

IT1

IT4

TLI

IT3

IT0

IT3

I0

10

PRIORITY
LEVEL

USED STACK = 10 BYTES

MAIN

IT2

TLI

MAIN

IT0

IT2

IT1

IT4

TLI

IT3

IT0

HARDWARE PRIORITY

3
2
1
3
3
3/0

3

11
00
01
11
11

11

RIM

IT1

IT4

IT4

IT1

IT2

IT3

I1 I0

11 / 10

10

SOFTWARE
PRIORITY
LEVEL

USED STACK = 20 BYTES

INTERRUPTS (Cont’d)

7.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit­ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc­ess shown in Figure 21.

Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.

Figure 22. Concurrent Interrupt Management

7.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 22 and Figure 23 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in­terrupt to be interrupted, unlike the nested mode in

Figure 23. The interrupt hardware priority is given

in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.

Warning: A stack overflow may occur without no­tifying the software of the failure.

Figure 23. Nested Interrupt Management

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Doc ID 6996 Rev 5

INTERRUPTS (Cont’d)

ST7262xxx

7.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGIS­TERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write
Reset Value: 111x 1010 (xAh)

70

11I1 H I0 NZC

Bit 5, 3 = I1, I0 Software Interrupt Priority
These two bits indicate the current interrupt soft-

ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main)
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) 1 1

Low

High

10

These two bits are set/cleared by hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (ISPRx).

They can be also set/cleared by software with the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in­structions (see “Interrupt Dedicated Instruction
Set” table).

*Note: TLI, TRAP and RESET events can interrupt
a level 3 program.

Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)

70

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software
priority of each interrupt vector.

– Each interrupt vector (except RESET and TRAP)

has corresponding bits in these registers where
its own software priority is stored. This corre­spondence is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex­ample: previous=CFh, write=64h, result=44h)

The RESET, TRAP and TLI vectors have no soft­ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre­spond to the TLI can be read and written but they
are not significant in the interrupt process man­agement.

Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be­haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ­ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter­rupt x).

Doc ID 6996 Rev 5

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ST7262xxx

INTERRUPTS (Cont’d)
INTERRUPT REGISTER 1 (ITRFRE1)

Address: 0008h - Read/Write
Reset Value: 0000 0000 (00h)

70

IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E

Bit 7:0 = ITiE Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.

Note: The corresponding interrupt is generated
when:

– a rising edge occurs on the IT5/IT6 pins
– a falling edge occurs on the IT1, 2, 3, 4, 7 and 8

pins

INTERRUPT REGISTER 2 (ITRFRE2)

Address: 0039h - Read/Write
Reset Value: 0000 0000 (00h)

Bit 5:4 = CTL[1:0] IT[10:9]1nterrupt Sensitivity
These bits are set and cleared by software. They

are used to configure the edge and level sensitivity
of the IT10 and IT9 external interrupt pins (this
means that both must have the same sensitivity).

CTL1 CTL0 IT[10:9] Sensitivity

0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge

Bit 3:0 = ITiE Interrupt Enable
0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.

70

CTL3 CTL2 CTL1 CTL0 IT12E IT11E IT10E IT9E

Bit 7:6 = CTL[3:2] IT[12:11] Interrupt Sensitivity
These bits are set and cleared by software. They

are used to configure the edge and level sensitivity
of the IT12 and IT11 external interrupt pins (this
means that both must have the same sensitivity).

CTL3 CTL2 IT[12:11] Sensitivity

0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge

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Doc ID 6996 Rev 5

INTERRUPTS (Cont’d)

Table 6. Interrupt Mapping

ST7262xxx

N°

0 ICP FLASH Start programming NMI interrupt Yes FFFAh-FFFBh
1 USB USB End Suspend interrupt USBISTR Yes FFF8h-FFF9h
2
3 Port B external interrupts IT[8:5] ITRFRE1 Yes FFF4h-FFF5h
4 Port C external interrupts IT[12:9] ITRFRE2 Yes FFF2h-FFF3h
5 TBU Timebase Unit interrupt TBUCSR No FFF0h-FFF1h
6 ART ART/PWM Timer interrupt ICCSR Yes FFEEh-FFEFh
7 SPI SPI interrupt vector SPISR Yes FFECh-FFEDh
8 SCI SCI interrupt vector SCISR No FFEAh-FFEBh
9 USB USB interrupt vector USBISTR No FFE8h-FFE9h

10 ADC A/D End of conversion interrupt ADCCSR No FFE6h-FFE7h

Source

Block

I/O Ports

Description

Reset
TRAP software interrupt No FFFCh-FFFDh

Port A external interrupts IT[4:1] ITRFRE1 Yes FFF6h-FFF7h

Reserved area FFE0h-FFE5h

Register

Label

Priority

Order

Highest

Priority

Lowest
Priority

Exit
from

HALT

Yes FFFEh-FFFFh

Address

Vector

Table 7. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

0032h

0033h

0034h

0035h

Ext. Interrupt Port B Ext. Interrupt Port A USB END SUSP Not Used

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value1111

I1_3

1

I1_7

1

Not Used ADC USB SCI

I1_11

1

I0_3

1

SPI ART TBU Ext. Interrupt Port C

I0_7

1

I0_11

1

I1_2

1

I1_6

1

I1_10

1

I0_2

1

I0_6

1

I0_10

1

I1_13

I1_1

1

I1_5

1

I1_9

1

Not Used Not Used

1

I0_1

111

I0_5

1

I0_9

1

I0_13

1

I1_4

1

I1_8

1

I1_12

1

I0_4

1

I0_8

1

I0_12

1

Doc ID 6996 Rev 5

29/139

ST7262xxx

WFI INSTRUCTION

RESET

INTERRUPT

Y

N

N

Y

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

CLEARED

OFF

CPU CLOCK

OSCILLATOR
PERIPH. CLOCK

I-BIT

ON

ON

SET

ON

FETCH RESET VECTOR

OR SERVICE INTERRUPT

514 CPU CLOCK

CYCLES DELAY

IF RESET

Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter­rupt routine and cleared when the CC register is
popped.

8 POWER SAVING MODES

8.1 INTRODUCTION

There are three Power Saving modes. Slow Mode
is selected by setting the SMS bits in the Miscella­neous register. Wait and Halt modes may be en­tered using the WFI and HALT instructions.

After a RESET the normal operating mode is se­lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 3 and multi­plied by 2 (f

CPU

).

From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.

8.1.1 Slow Mode

In Slow mode, the oscillator frequency can be di­vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.

Figure 24. WAIT Mode Flow Chart

8.2 WAIT MODE

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This power saving mode is selected by calling the
“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and memory re­main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occurs, whereup­on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.

Refer to Figure 24.

30/139

Doc ID 6996 Rev 5