ST ST7261 User Manual

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LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS,

■ Memories

– 4K Program memory (ROM) with read-write

protection.
In-Circuit programming for Flash versions

– 256 bytes RAM memory (128-byte stack)

■ Clock, Re set and Supp ly M a nagement

– Enhanced Reset System (Power On Reset)
– Low Voltage Detector (LVD)
– Clock-out capability
– 6 or 12 MHz Oscillator (8, 4, 2, 1 MHz internal

freq.)

– 3 Power saving modes: Halt, Wait and Slow

■ USB (Universal Serial Bus) Interface

– DMA for low speed applications compliant

with USB 1.5 Mbs specification (v 1.1) and
USB HID specification (v 1.0):

– Integrated 3.3V voltage regulator and trans-

ceivers
– Suspend and Resume operations
– 3 Endpoints

■ 11 I/ O P o rts

– 11 multifunctional bidirectional I/O lines
– Up to 7 External interrupts (2 vectors)
– 8 high sink outputs (8mA@0.4 V/20mA@1.3)

■ 2 Timers

– Configurable watchdog timer (8 to 500ms

timeout)
– 8-bit Time Base Unit (TBU) for generating pe-

riodic interrupts

ST7261

ROM MEMORY, LVD, WDG, TIMER

SO20

PDIP20

■ Instruction Set

– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation

■ Nested interrupts

■ Development Tools

– Full hardware/software development package

Device Summary

Features ST72611F1

Program memory - bytes 4K ROM
RAM (stack) - bytes 256 (128)
Periphe rals USB, W at chdog, Low V oltage De tector, Tim e B ase Unit
I/Os 11
Operating Supply 4.0V to 5.5V
CPU Fre quency Up to 8 MHz (with 6 or 12 MHz oscilla tor)
Operati ng T em perature 0°C to +70°C

Packages PDIP20/SO20

Rev. 2.1

June 2003 1/80

1

Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 PCB LAYOUT RECOMMENDATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 CLOCKS AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.6 INTERRUPT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

8 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.3 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

9 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.2 TIMEBASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.3 USB INTERFACE (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.1CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.2INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.1PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

11.2ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

11.3OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

11.4SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.5CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11.6MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11.7EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

80

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1

Table of Contents

11.8I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

11.9CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.10COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 67

12 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

13 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . 69

13.1OPTION BYTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

13.2DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

13.3DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

14 IMPORTANT NOTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

14.1UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

14.2ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

15 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

16 SILICON IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

17 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

18 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

18.1LVD RESET ON VDD BROWNOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

19 ERRATA SHEET ReVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

To obtain the most recent version of this datasheet,

please check at www.st.com>products>technical literature>datasheet

Please note that an errata sheet can be found at the end of this document on page 77
and pay special attention to the Section “IMPORTANT NOTE” on page 73.

80

3/80

ST7261

1 INTRODUCTION

The ST7261 devices are members of the ST7 mi­crocontroller family designed for USB applications.

All devices are based on a common industry­standard 8-bit core, featuring an enhanced instruc­tion set.

The ST7261 devices are ROM versions. The
FLASH version is supported by the ST72F623F2.

Under software control, all devices can b e placed
in WAIT, SLOW, or HALT mode, reducing po wer

Figure 1. General Block D iagram

Internal

OSCIN

OSCOUT

V

V

RESET

V

DD

SS

OSCILLATOR

LVD

POWER

SUPPLY

CONTROL

8-BIT CORE

ALU

USB DMA

PP

PROGRAM

MEMORY

(4 KBytes)

CLOCK

consumption when the application is in idle or
standby state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro­controllers feature true bit manipulation, 8x8 un­signed multiplication and indirect addressing
modes.

PORT A

ADDRESS AND DATA BUS

PORT B

TIME BASE UNIT

USB SIE

WATCHDOG

PA2:0

(3 bits)

PB7:0

(8 bits)

USBDP

USBDM

USBVCC

4/80

1

RAM

(256 Bytes)

2 PIN DESCRI PTION

Figure 2. 20-pin SO20 Package Pinout

ST7261

IT3/PA2
IT2/PA1

USBOE/IT1/ PA0

V

SS

USBDM

USBDP

USBVCC

V

DD

V

PP

RESET

Figure 3. 20-pin DIP20 Package Pinout

IT5/PB4 (HS)

PB3 (HS)
PB2 (HS)

PB1 (HS)

MCO/PB0 (HS)

IT3/PA2
IT2/PA1

USBOE/IT1/PA0

V

SS

USBDM

10

10

1
2
3
4
5
6
7
8
9

1
2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13
12
11

20
19
18
17
16
15
14
13
12
11

PB0 (HS)/MCO
PB1 (HS)
PB2 (HS)
PB3 (HS)
PB4 (HS)/IT5

PB5 (HS)/IT6
PB6 (HS)/IT7

PB7 (HS)/IT8
OSCOUT
OSCIN

PB5 (HS)/IT6
PB6 (HS)/IT7

PB7 (HS)/IT8
OSCOUT
OSCIN

RESET
V

PP

V

DD

USBVCC
USBDP

5/80

ST7261

PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:

Type: I = input, O = output, S = supply
Input level: A = Dedicated analog input
Input level: C = CMOS 0.3V

= CMOS 0.3VDD/0.7VDD with input trigger

C

T

Output level: HS = high sink (on N-buffer only)
Port configuration capabilities:

– Input: float = floating, wpu = weak pull-up, int = interrupt (\ =falling edge, / =rising edge

ana = analog

– Output: OD = open drain, PP = push-pull

Table 1. Device Pin Description

/0.7VDD,

DD

),

Pin n°

Level Port / Control

Main

Pin Name

Type

SO20

DIP20

914V

PP

Sx

11 16 OSCIN
12 17 OSCOUT

49V
813V

SS
DD

S Digital Ground Voltage

S Digital Main Power Supply Voltage
13 18 PB7/IT8 I/O C
14 19 PB6/IT7 I/O C
15 20 PB5/IT6 I/O C
16 1 PB4/IT5 I/O C
17 2 PB3 I/O C
18 3 PB2 I/O C
19 4 PB1 I/O C
20 5 PB0/MCO I/O C

1 6 PA2/IT3 I/O C
2 7 PA1/IT2 I/O C

3 8 PA0/IT1/USBOE I/O C

10 15 RESET

I/O C

Input Output

Input

Output

float

HS x \ x Port B7 Interrupt 8 input

T

HS x \ x Port B6 Interrupt 7 input

T

HS x / x Port B5 Interrupt 6 input

T

HS x / x Port B4 Interrupt 5 input

T

HS x x Port B3

T

HS x x Port B2

T

HS x x Port B1

T

HS x x Port B0 CPU clock output

T
T
T

T

x\ xPort A2 Interrupt 3 input

X\ xPort A1 Interrupt 2 input
X\ xPort A0

int

wpu

OD

ana

Function

Alternate Function

(after reset)

PP

FLASH programming voltage (12V), must be
tied low in user mode.

These pins are used connect an external
clock source to the on-chip main oscillator.

Interrupt 1 input/USB Output
Enable

Top priority non maskable interrupt (active
low)

5 10 USBDM I/O USB bidirectional data (data -)
6 11 USBDP I/O USB bidirectional data (data +)
7 12 USBVCC S USB power supply 3.3V output

6/80

PIN DESCRIPTION (Cont’d)

2.1 PCB LAYOUT RECOMMENDATION

ST7261

In the case of DIP20 devic es the user should lay­out the PCB so that the DIP20 ST7261 device and

ensuring that the D- and D+ lines are of equal
leng th . Refer to Figure 4

the USB connector are centered on the same axis

Figure 4. Recommended PCB Layout for USB Interface with DIP20 package

USBDM

1
2
3
4
5
6
7
8
9

10

ST7261

20
19
18
17
16
15
14
13
12
11

USBVCC
USBDP

1.5KOhm pull-up resistor

Ground

Ground

USB Connecto r

7/80

ST7261

3 REGISTER & MEMORY MAP

As shown in the Figure 5, the MCU is capable of
addressing 64K bytes of memories and I/O regis­ters.

The available memory locations consist of 64
bytes of register locations, 256 bytes of RAM an d
4 Kbytes of user program memory. The RAM
space includes up to 128 bytes for the sta ck from
0100h to 017Fh.

Figure 5. Me m ory Map

0000h

003Fh
0040h

007Fh
0080h

017Fh
0180h

EFFFh

F000h

FFDFh
FFE0h

FFFFh

HW Registers

(see Table 2)

Reserved

256 Bytes RAM

Reserved

Program Memory

(4 KBytes)

Interrupt & Reset Vectors

See Table 5 on page 21

The highest address by tes contain the user re set
and interrupt vectors.

IMPORTANT: Memory locations marked as “Re­served” must neve r be ac cess ed. A cce ssing a re­seved area c an have unpredictable effects on the
device.

0080h

00FFh

017Fh

Short Addressing RAM

Zero page

(128 Bytes)

Stack or

16-bit Addressing RAM

(128 Bytes)

8/80

Table 2. Hardware Register Map

ST7261

Address Block

0000h
0001h

0002h
0003h

0004h

to

0007h
0008h ITRFRE1 Interrupt Register 1 00h R/W
0009h MISC Miscellaneous Register 00h R/W
000Ah

to

000Ch
000Dh WDG WDGCR Watchdog Control Register 7Fh R/W

000Eh to

0024h
0025h

0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h

Port A

Port B

USB

Register

Label

PADR
PADDR

PBDR
PBDDR

USBPIDR
USBDMAR
USBIDR
USBISTR
USBIMR
USBCTLR
USBDADDR
USBEP0RA
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB

Register Name

Port A Data Register
Port A Data Direction Register

Port B Data Register
Port B Data Direction Register

Reserved Area (4 Bytes)

Reserved Area (2 Bytes)

Reserved Area (23 Bytes)

USB PID Register
USB DMA Address register
USB Interrupt/DMA Register
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
USB Device Address Register
USB Endpoint 0 Register A
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B

Reset

Status

00h
00h

00h
00h

x0h
xxh
x0h
00h
00h
06h
00h

0000 xxxxb

80h
0000 xxxxb
0000 xxxxb
0000 xxxxb
0000 xxxxb

Remarks

R/W
R/W

R/W
R/W.

Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

0032h

to

0035h
0036h

0037h
0038h

to

003Fh

TBU

TBUCV
TBUCSR

Reserved Area (4 Bytes)

TBU Counter Value Register
TBU Control/Status Register

Reserved Area (8 Bytes)

00h

00h

R/W
R/W

9/80

ST7261

4 CENTRAL PROCE SSI NG UNIT

4.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

4.2 MAIN FEATURES

■ Enable executing 63 basic instructions

■ Fast 8-bit by 8-bit multiply

■ 17 main addressing modes (with indirect

addressing mode)

■ Two 8-bit index registers

■ 16-bit stack pointer

■ Low power HALT and WAIT modes

■ Priority maskable hardware interrupts

■ Non-maskable software/hardware interrupts

Figure 6. CPU Registers

4.3 CPU REGISTERS

The 6 CPU registers shown in Figure 6 are not
present in the memory mapping and are accessed
by specifi c ins t r uc tions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg­ister used to hold operan ds and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

These 8-bit registers are used to create effective
addresses or as tempora ry storage areas f or dat a
manipulation. (The Cross-A ssembler generates a
precede instruction (PRE) to indicate that the fol­lowing instruction refers to the Y register.)

The Y register is not affected by the interrupt auto­matic procedures.

Program Cou nt er (P C )

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

70

RESET VALUE = XXh

70

RESET VALUE = XXh

70

RESET VALUE = XXh

15 8

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

15

RESET VALUE = STACK HIGHER ADDRESS

PCH

RESET VALUE =

7

70

1C1I1HI0NZ
1X11X1XX

70

8

PCL

0

ACCUMULATOR

X INDEX REGISTER

Y INDEX REGISTER

PROGRAM COUNTER

CONDITION CODE REGISTER

STACK POINTER

X = Undefined Value

10/80

CENTRAL PROCESSING UNIT (Cont’d)
Condition Code Register (CC)

Read/Write
Reset Value: 111x1xxx

70

11I1HI0NZ

C

This bit is set and cleared by hardware. This bit in­dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test

instructions.

The 8-bit Condition Code register c ontains the in­terrupt masks and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in­structions.

These bits can be individually tested and/or con­trolled by specific instructions.

Arithmetic Management Bits
Bit 4 = H

Half carry

.

This bit is set by hardware when a carry occurs be­tween bits 3 and 4 of t he ALU during an ADD or
ADC instructions. It is reset by hardware during
the same instruction s.

0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc­tion. The H bit is useful in BCD arithmetic subrou­tines .

Bit 2 = N

Negative

.

Bit 0 = C

Carry/borrow.

This bit is set and cleared b y hardware and soft­ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the “bit test and branch”, shift and
rotate instructions.

Interrupt Managem ent B i ts
Bit 5,3 = I1, I0

Interrupt

The combination of the I1 and I0 bits gives the cur­rent interrupt software priority.

Interrupt Software Priorit y I1 I0

Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

This bit is set and cleared by hardware. It is repre­sentative of the result sign of the last arithmetic,
logical or data manipulation. I t’s a copy of the re-

th

sult 7

bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc­tions.

Bit 1 = Z

Zero

.

These two bits are set/cleared b y hardware when
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/POP instructions.

See the interrupt management chapter for more
details.

ST7261

11/80

ST7261

CPU REGISTERS (Cont’d)
STACK POINTER (SP)

Read/Write
Reset Value: 017Fh

15 8

00000001

70

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The Stack Pointer is a 16-bit register which is al­ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 7).

Since the stack is 128 bytes deep, the 9 most sig­nificant bits are forced by hardw are. Following a n
MCU Reset, or after a Reset Stack Pointe r instruc­tion (RSP), the Stack Pointer contains its reset val­ue (the SP6 to SP0 bits are set) which is the stack
higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in­struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, wi th­out indicating the s tack overflow. The prev iously
stored information is then o verwritten and there­fore lost. The stack also wraps in case of an under­flow.

The stack is used to save the retu rn address dur­ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc­tions. In the case of an interrupt, the PCL is stored
at the first location point ed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 7.

– When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

– On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in­terrupt five locat ions i n the sta ck ar ea.

Figure 7. Stack Manipulation Example

@ 0100h

SP

@ 017Fh

CALL

Subroutine

SP

PCH
PCL

Stack Higher Address = 017Fh
Stack Lower Address =

Interrupt

Event

SP

CC

A

X
PCH
PCL
PCH

PCL

0100h

PUSH Y POP Y IRET

SP

Y

CC

A

X
PCH
PCL
PCH

PCL

CC

A

X
PCH
PCL
PCH

PCL

SP

PCH

PCL

RET

or RSP

SP

12/80

5 CLOCKS AND RESET

5.1 CLOCK SYSTEM

ST7261

5.1.1 General Description

The MCU accepts either a Crystal or Ceramic res­onator, or an external clock signal to drive the in­ternal oscillator. The internal clock (f

rived from the external oscillator frequency (f

CPU

) is de-

OSC

by dividing by 3 and multiplying by 2. By setting the
OSC12/6 bit in the option byte, a 12 MHz external
clock can be used giving an internal frequency of 8
MHz while maintaining a 6 MHz clock for USB (re­fer to F igure 10).

The internal clock signal (f

) consists of a

CPU

square wave with a duty cycle of 50%.
It is further divided by 1, 2, 4 or 8 depending on the

Slow Mode Selection bits in the Miscellaneous
regis ter (S MS[1:0])

The internal oscillat or is designed to operate with
an AT-cut parallel resonant quartz or ceramic res­onator in the frequency range specified for f

osc

The circuit shown in Figure 9 is recommended
when using a crystal, and Ta ble 3 lists the recom­mended capacitors. The crystal and associated
components should be mount ed as c lose as pos­sible to the input pins in order to minimize output
distortion and start-up stabilization time.

Figure 8. External Clock Source Connections

),

OSCIN OSCOUT

NC

EXTERNAL

CLOCK

Figure 9. Crystal/Ceramic Resonator

.

OSCOUT

C

OSCOUT

C

OSCIN

OSCIN

Table 3. Recommended Values for 12 MHz
Crystal Resonator

R

SMAX

C

OSCIN

C

OSCOUT

R

P

Note: R
crystal (see crystal specification).

SMAX

20

Ω

56pF 47pF 22pF
56pF 47pF 22pF

1-10 M

Ω

25

1-10 M

Ω

Ω

70

1-10 M

Ω

Ω

is the equivalent serial resistor of the

5.1.2 External Clock input

An external clock may be applied to the OSCIN in­put with the OSCOUT pin not connected, as
shown on F igure 8. The t

specifications does

OXOV

not apply when using an external clock input. The
equivalent specification of the external clock
source should be used instead of t

OXOV

(see Elec-

trical Characteri stic s).

5.1.3 Clock Output Pin (MCO)

The internal clock (f

) can be output on Port B0

CPU

by setting the MCO bit in the Miscellane ous re gis­ter.

Figure 10. Clock block diagram

f

CPU

(or 4/2/1/0.5 MHz)

to CPU and
peripherals

12 or

6 MHz

Crystal

x2

%3

%2

Slow

Mode

%

1/2/4/8

SMS[1:0]

OSC12/6

0

1

8/4/2/1 MHz

MCO pin

6 MHz (USB)

13/80

ST7261

5.2 RESET

The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.

Three reset modes are provided: a low voltage re­set, a watchdog reset and an external reset at th e
RESET

pin.

A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.

An internal circuitry provides a 514 CPU clock c y­cle delay from the time that the oscillator becomes
active.

5.2.1 Low Voltage Reset

Low voltage reset circuitry generates a reset when
V

is:

DD

■ below V

■ below V

During low voltage reset, the RESET

when VDD is rising,

IT+

when VDD is falling.

IT-

pin is held low,

thus permitting the MCU to reset other devices.

The Low Voltage Detector can be disabled by set­ting the LVD bit of the Option byte.

5.2.3 External Reset

The external reset is an active low input signal ap­plied to the RESET
As shown in Figure 14, the RESET

pin of the MCU.

signal must
stay low for a minimum of one and a half CPU
clock cycles.

An internal Schmitt trigger at the RESET

pin is pro-

vided to improve noise immunity.

Figure 11. Low Voltage Reset functional Diagram

RESET

V

DD

Figure 12. Low Voltage Reset Signal Output

V

DD

LOW VOLTAGE

RESET

FROM

WATCHDOG

RESET

V

IT+

INTERNAL

RESET

V

IT-

5.2.2 Watchdog Reset

When a watchdog res et oc curs, the RESET

pin is

RESET

pulled low permitting the MCU to reset other devic­es as when low voltage reset (Figure 11).

Note: Typical hysteresis (V
expected

Figure 13. Temporization Timing Diagram after an internal Reset

V

V

DD

IT+

Temporization

(514 CPU clock cycles)

Addresses

$FFFE

IT+-VIT-

) of 250 mV is

14/80

Figure 14. Reset Timing Diagram

t

DDR

V

DD

OSCIN

t

OXOV

f

CPU

ST7261

PC

RESET

Note: Refer to Electrical Characteristics for values of t
Figure 15. Reset Block Diagram

V

DD

R

ON

RESET

t

w(RSTL)out

200ns

Filter

+ 128 f

delay

OSC

514 CPU

CLOCK

CYCLES

DELAY

, t

OXOV

DDR

PULSE

GENERATOR

FFFE

, V

IT+

FFFF

and V

IT-.

INTERNAL
RESET

WATCHDOG RESET

LVD RESET

Note: The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

15/80

ST7261

6 INTE RRUPTS

6.1 INTRODUCTION

The CPU enhanced interrupt management pro­vides the following features:

■ Hardware interrupts

■ Software interrupt (TRAP)

■ Nested or concurrent interrupt management

with flexible interrupt priority and level
management:

– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 3 non maskable events: RESET, TRAP, TLI

This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed int errupt vector addre sses located at the

high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest­ed) CPU interrupt controller.

6.2 MASKI NG AN D PROC ESSING FLOW

The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Table 4 ). The process­ing flow is shown in Figure 16.

When an interrupt request has to be serviced:
– Normal processing is suspended at the end of

the current instruction execution.

– The PC, X, A and CC registers are saved onto

the stack.

– I1 and I0 bits of CC register are set according t o

the corresponding values in the ISPRx registers
of the serviced interrupt vector.

– The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).

The interrupt service routine should end with the
IRET instruction which causes the cont ents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.

Table 4. Interrupt Software Priority Levels

Interrupt software priority Level I1 I0

Level 0 (main) Low
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1

High

10

Figure 16. Inte rru pt P rocessing Flowchart

RESET

RESTORE PC, X, A, CC

FROM STACK

16/80

PENDING

INTERRUPT

N

FETCH NEX T

INSTRUCTION

Y

“IRET”

N

EXECUTE

INSTRUCTION

Y

THE INTERRUPT
STAYS PENDING

TLI

Interrupt has the same or a

lower software priority

than curren t one

STACK PC, X, A, CC

LOA D I1:0 FROM IN TERR UPT SW REG .

LOAD PC FROM INTERRUPT VECTOR

N

I1:0

softwarepriority

than current one

Interrupt has a higher

Y

INTERRUPTS (Cont’d)

ST7261

Servicing Pe nding Interrup t s

As several interrupts can b e pending at the sam e
time, the interrupt to be taken into account is deter­mined by the following two-step process:

– the highest software priority interrupt is serviced,
– if several interrupts have the same software pri-

ority then the interrupt with the highest hardware
priority is serviced first.

Figure 17 describes this decision process.

Figure 17. Priority Decision Process

PENDING

INTERRUPTS

Same

HIGHEST HARDWARE

PRIORITY SERVICED

SOFTWARE

PRIORITY

HIGHEST SOFTWARE

PRIORITY SERVICED

Different

When an interrupt request is not serviced immedi­ately, it is latched and then processed when its
software priority combined with the hardware pri­ority becomes the highest one.

Note 1: The hardware priority is exclusive while
the software one is not. This allows the previ ous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI can be considered
as having the highest software priority in the deci­sion process.

Different Interrupt Vector Sources

Two interrupt source types are managed by the
CPU interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex­ternal or from internal peripherals).

Non-Maskable Sources

These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see

Figure 16). After stacking the PC, X, A and CC

registers (except for RESET), the corresponding
vector is loaded in the PC re gister and the I 1 and
I0 bits of the CC are set to disable interrupts (level

3). These sources allow the processor to exit
HALT mode.

■ TLI (Top Level Hardware Interrupt)

This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
TLI se rvice routine.

■ TRAP (Non Maskable Software Interrupt)

This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord­ing to the flowchart in Figure 16 as a TLI.
Caution: TRAP can be interrupted by a TLI.

■ RESET

The RESET source has the highest priority in the
CPU. This means that the first current routine has
the highest software priority (level 3) and the high­est hardware priority.
See the RESET chapter for more details.

Maskable Sources

Maskable interrupt vect or sourc es can be serviced
if the corresponding interrupt is e nabled and if its
own interrupt software priority (in ISPRx registers)
is higher than the one currently being serviced (I1
and I0 in CC regist er). If any of these two condi­tions is false, the interrupt is la tched and thus re­mains pending.

■ External Interrupts

External interrupts allow the processor to exit from
HALT low power mode.
External interrupt sensitivity is software selectable
through the ITRFRE2 register.
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a grou p connected to the
same interrupt line are selected simultaneously,
these will b e lo gically NAND ed.

■ Peripheral Interrupts

Usually the peripheral interrupts cause the Device
to exit from HALT mode except those mentioned in
the “Interrupt Mapping” table.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or write to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se­quence is executed.

17/80

ST7261

INTERRUPTS (Cont’d)

6.3 INTERRUPTS AND LOW POWER MODES

All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit­ing HALT mode, the first one serviced can only be
an interrupt with e xit from HALT mode capab ility
and it is selected through the same decision proc­ess shown in Figure 17.

Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.

Figure 18. Concurren t Int errupt Manag e m ent

IT2

IT1

IT4

IT2

RIM

IT1

IT3

TLI

IT0

TLI

IT1

HARDWARE PRIORITY

MAIN

11 / 10

6.4 CONCURRENT & NESTED MANAGEMENT

The following Figure 18 and Figure 19 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in­terrupt to be interrupted, unlike the nested mode in

Figure 19. The interrupt hardware priority is given

in this order from the l owest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.

Warning: A stack overflow may occur without no­tifying the software of the failure.

SOFTWARE
PRIORITY
LEVEL

IT0

IT3

IT4

MAIN

3
3
3
3
3
3
3/0

I1

11
11
11
11
11
11

10

I0

USED STACK = 10 BYTES

Figure 19. Nested Interrupt Management

IT2

IT1

IT4

IT1

IT2

RIM

HARDWARE PRIORITY

MAIN

IT4

IT3

TLI

IT0

TLI

11 / 10

18/80

IT4

IT0

IT3

IT1

SOFTWARE
PRIORITY
LEVEL

IT2

10

MAIN

I1 I0

3
3
2
1
3
3
3/0

11
11
00
01
11
11

USED STACK = 20 BYTES

INTERRUPTS (Cont’d)

ST7261

6.5 INTERRUPT REGISTER DESCRIPTION

INTERRUPT SOFTWARE PRIORITY REGIS­TERS (ISPRX)

CPU CC REGISTER INTERRUPT BITS

Read/Write
Reset Value: 111x 1010 (xAh)

70

11I1 H I0 NZC

Bit 5, 3 = I1, I0

Software Inter r u p t Prio rity

These two bits indicate the current interrupt soft­ware priority.

Interrupt Software Priority Level I1 I0

Level 0 (main)
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) 1 1

Low

High

10

These two bits are set/cleared by ha rdware whe n
entering in interrupt. The loaded value is given by
the corresponding bits in the interrupt software pri­ority registers (ISPRx).

They can be also set/cleared by sof tw are wi th th e
RIM, SIM, HALT, WFI, IRET and PUSH/POP in­structions (see “Interrupt Dedicated Instruction
Set” table).

*Note: TLI, TRAP and RESET events ca n i nterr upt
a level 3 program.

Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)

70

ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0

ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4

ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8

ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12

These four registers contain the interrupt software
priority of each interrupt vector.

– Each interrupt ve ctor (except R ESET and TRAP)

has corresponding bits in these registers where
its own software priority is stored. This corre­spondance is shown in the following table.

Vector address ISPRx bits

FFFBh-FFFAh I1_0 and I0_0 bits*

FFF9h-FFF8h I1_1 and I0_1 bits

... ...

FFE1h-FFE0h I1_13 and I0_13 bits

– Each I1_x and I0_x bit value in the ISPRx regis-

ters has the same meaning as the I1 and I0 bits
in the CC register.

– Level 0 can not be written (I1_x=1, I0_x=0). In

this case, the previously stored value is kept. (ex­ample: previous=CFh, write=64h, result=44h )

The RESET, TRAP and TLI v ectors have no sof t­ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.

*Note: Bits in the ISPRx registers which corre­spond to the TLI can be read and written but they
are not significant in the interrupt process man­agement.

Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the following be­haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new software priority is higher than the previ­ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the inter­rupt x).

19/80

ST7261

6.6 Interrupt Register
INTERRUPT REGISTER 1 (ITRFRE1)

Address: 0008h - Read/Write
Reset Value: 0000 0000 (00h)

70

IT8E IT7 E IT6E IT5E IT4E IT3E I T2E IT1E

Bit 7:0 = ITiE

Interrupt Enable

0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.

Note: The corresponding interrupt is generated
when:

– a rising edge occurs on the IT5/IT6 pins
– a falling edge occurs on the IT1, 2, 3, 4, 7 and 8

pins

INTERRUPT REGISTER 2 (ITRFRE2)

Address: 0039h - Read/Write
Reset Value: 0000 0000 (00h)

Bit 5:4 = CTL[1:0]

IT[10:9]1nterrupt Sensitivity

These bits are set and cleared by so ftware. They
are used to configure the edge and level sensitivity
of the IT10 and IT9 external interrupt pins (this
means that both must have the same sensitivity).

CTL1 CTL0 IT[10:9] Sensitivity

0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge

Bit 3:0 = ITiE

Interrupt Enable

0: I/O pin free for general purpose I/O
1: ITi external interrupt enabled.

70

CTL3 CT L2 CTL1 CTL0 IT12E IT11E IT10E IT9E

Bit 7:6 = CTL[3:2]

IT[12:11] Interrupt Sensitivity

These bits are set and cleared by software. They
are used to configure the edge and level sensitivity
of the IT12 and IT11 external interrupt pins (this
means that both must have the same sensitivity).

CTL3 CTL2 IT[12:11] Sensitivity

0 0 Falling edge and low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge

20/80

INTERRUPTS (Cont’d)
Table 5. Int errupt Mapping

ST7261

N°

0 NOT USED FFFAh-FFFBh
1 USB USB End Suspend interrupt vector USBISTR Yes FFF8h-FFF9h
2
3 Port B external interrupts IT[8:5] Yes FFF4h-FFF5h
4 NOT USED FFF2h-FFF3h
5 TBU Timebase Unit interrupt vector TBUCSR No FFF0h-FFF1h
6 NOT USED FFEEh-FFEFh
7 NOT USED FFECh-FFEDh
8 NOT USED FFEAh-FFEBh
9 USB USB interrupt vector USBISTR No FFE8h-FFE9h

10 NOT USED FFE6h-FFE7h

Source

Block

I/O Ports

Description

Reset Vector Yes FFFEh-FFFFh
TRAP software interrupt vector No FFFCh-FFFDh

Port A external interrupts IT[3:1]

Register

Label

ITRFRE1

Exit

from

HALT

Yes FFF6h-FFF7h

Address

Vector

Table 6. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

76543210

Priority

Order

Highest

Priority

Lowest

Priority

0032h

0033h

0034h

0035h

Ext. Interrupt Port B Ext. Interrupt Port A USB END SUSP Not Used

ISPR0

Reset Value

ISPR1

Reset Value

ISPR2

Reset Value

ISPR3

Reset Value1111

I1_3

1

I1_7

1

Not Used ADC USB SCI

I1_11

1

I0_3

1

SPI ART TBU Ext. Interrupt Port C

I0_7

1

I0_11

1

I1_2

1

I1_6

1

I1_10

1

I0_2

1

I0_6

1

I0_10

1

I1_13

I1_1

1

I1_5

1

I1_9

1

Not Used Not Used

1

I0_1

111

I0_5

1

I0_9

1

I0_13

1

I1_4

1

I1_8

1

I1_12

1

I0_4

1

I0_8

1

I0_12

1

21/80

ST7261

7 POWER SAVIN G MO DES

7.1 INTRODUCTION

There are three Power Saving modes. Slow Mode
is selected by setting the SMS bits in the Miscella­neous register. Wait and Halt modes may be en­tered using the WFI and HALT instructions.

After a RESET the normal operating mode is se­lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator fre quency divided by 3 and multi­plied by 2 (f

CPU

).

From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.

7.1.1 Slow Mode

In Slow mode, the oscillator frequency can be d i­vided by a value defined in the Miscellaneous
Register. The CPU and peripherals are clocked at
this lower frequency. Slow mode is used to reduce
power consumption, and enables the user to adapt
clock frequency to available supply voltage.

7.2 WAIT MODE

WAIT mode places the MCU in a low power con­sumption mode by stopping the CPU.
This pow er s av in g mode is s elected b y calling th e

“WFI” ST7 software instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is forced to 0, to enable
all interrupts. All other registers and mem ory re­main unchanged. The MCU remains in WAIT
mode until an interrupt or Reset occu rs, where up­on the Program Counter branc hes to the starting
address of the interrupt or Reset service routine.
The MCU will r e main in W AIT mod e unt il a Rese t
or an Interrupt occurs, causing it to wake up.

Refer to Figure 20.

Figure 20. WAIT Mode Flow Chart

WFI INSTRUCTION

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK

I-BIT

N

INTERRUPT

Y

N

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT

FETCH RESET VECTOR

OR SERVICE INTERRUPT

RESET

IF RESET

514 CPU CLOCK

CYCLES DELAY

ON

ON

OFF
CLEARED

Y

ON

ON

ON
SET

22/80

Note: Before servicing an interrupt, the CC register is
pushed on the sta ck. The I-Bit is s et d uring the inte r­rupt routine and cleared when the CC register is
popped.

ST7261

POWER SAVING MODES (Cont’d)

7.3 HALT MODE

The HALT mode is the MCU lowest power con­sumption mode. The HALT mode is entered by ex­ecuting the HALT instruction. The internal oscilla­tor is then turned off, causing all internal process­ing to be stopped, including the operation of the
on-chip peripherals.

When entering HALT mode, the I bit in the Condi­tion Code Register is cleared. Thus, any of the ex­ternal interrupts (ITi or US B end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.

The MCU can exit HALT m ode on reception of ei­ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillat or is t hen t urned on and a stabi­lization time is provided before rele asing CPU op­eration. The stabilization time is 514 CPU clock cy­cles.
After the start up delay, the CPU continues opera­tion by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.

Figure 21. HAL T Mode Flow C hart

HALT INSTRUCTION

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK

I-BIT

N

RESET

N

EXTERNAL

INTERRUPT*

Y

OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT

OFF

OFF

OFF
CLEARED

Y

ON

ON

ON
SET

514 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is
pushed on the stac k. T he I -Bit i s se t du ring the inter­rupt routine and cleared when the CC register is
popped.

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ST7261

8 I/O PORTS

8.1 INTRODUCTION

The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs

and for specific pins:

– Analog signal input (ADC)
– Alternate signal input/output for the on-chip pe-

ripherals.
– External interrupt generation
An I/O port i s com pos ed of up to 8 pins. E ach pin

can be programmed independently as digital input
or digital output.

8.2 FUNCTIONAL DESCRIPTION

Each port is associated with 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
Each I/O pin may be programmed using the corre-

sponding register bits in DDR regi ster: bit x corre­sponding to pin x of the port. The same corre­spondence is used for the DR register.

Table 7. I/O Pin Functi ons

DDR MODE

0 Input
1 Output

8.2.1 Input Modes

The input configuration is sele cted by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Notes:

1. All the inputs are triggered by a Schmitt trigger.

2. When switching from input mode to output

mode, the DR reg ister should be written f irst to
output the correct value as soon as the port is
configured as an output.

Interrupt function

When an external interrupt function of an I/O pin, is
enabled using the ITFRE registers, an event on
this I/O can generate an external Interrupt request
to the CPU. The interrupt sensitivity i s programma-

ble, the options are given in the description of the
ITRFRE interrupt registers.

Each pin can independently generate an Interrupt
request.

Each external interrupt vector is linked t o a dedi­cated group of I/O port pins (see Interrupts sec­tion). If more than one input pin is selected simul­taneously as interrupt source, this is logically AN­Ded and inverted. For this reason, if an event oc­curs on one of the in terrupt pins, it masks the other
ones.

8.2.2 Output Mode

The pin is configured in output mode by setting the
corresponding DDR register bit (see Table 7).

In this mode, writing “0” or “1” to the DR register
applies this digital value to the I/O pin through the
latch. Then reading the DR register returns the
previously stored value.

Note: In this mode, the interrupt function is disa­bled.

8.2.3 Alternate Functions
Digital Alternate Func ti ons

When an on-chip peripheral is configured to use a
pin, the alternate function is au tomatically select­ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automatically configured in output mode (push-pull
or open drain according to the peripheral).

When the signal is goi ng to an on-chip peripheral,
the I/O pin ha s to be configured in i nput mode. In
this case, the pin state is also digitally readable by
addressing the DR register.

Notes:

1. Input pull-up configuration can cause an unex ­pected value at the alternate peripheral input.

2. When the on-chip peripheral uses a pin as input
and output, this pin must be c onfigured as an
input (DDR = 0).

Warning

: Alternate functions of peripherals must

must not be activated when the external interrupts
are enabled on the same pin, in order to avoid
generating spurious interrupts.

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