ST72561xx-Auto
8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™, active CAN
Features
■Memories
–16 K to 60 K High Density Flash (HDFlash) or ROM with read-out protection capability. In-application programming and in-circuit programming for HDFlash devices
–1 to 2 K RAM
–HDFlash endurance: 100 cycles, data retention 20 years at 55 °C
■Clock, reset and supply management
–Low power crystal/ceramic resonator oscillators and bypass for external clock
–PLL for 2 x frequency multiplication
–5 power saving modes: halt, auto wake up from halt, active halt, wait and slow
■Interrupt management
–Nested interrupt controller
–14 interrupt vectors plus TRAP and RESET
–TLI top level interrupt (on 64-pin devices)
–Up to 21 ext. interrupt lines (on 4 vectors)
■Up to 48 I/O ports
–Up to 48 multifunctional bidirectional I/Os
–Up to 36 alternate I/O functions
–Up to 6 high sink outputs
■5 timers
–16-bit timer with 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
–8-bit timer with 1 or 2 input captures, 1 or 2 output compares, PWM and pulse generator modes
–8-bit PWM auto-reload timer with 1 or 2 input captures, 2 or 4 independent PWM output channels, output compare and time base interrupt, external clock with event detector
–Main clock controller with real-time base and clock output
–Window watchdog timer
LQFP32 7x7mm |
LQFP44 10x10mm |
LQFP64 10x10mm |
LQFP64 14x14mm |
■Up to 4 communications interfaces
–SPI synchronous serial interface
–Master/ slave LINSCI™ asynchronous serial interface
–Master only LINSCI™ asynchronous serial interface
–CAN 2.0B active
■Analog peripheral (low current coupling)
–10-bit A/D converter with up to 16 inputs
–Up to 9 robust ports (low current coupling)
■Instruction set
–8-bit data manipulation
–63 basic instructions, 17 main addressing modes
–8 x 8 unsigned multiply instruction
■Development tools
–Full hardware/ software development package
Table 1. Device summary
Reference |
Part number |
ST72561K4-Auto, ST72561K6-Auto,
ST72561K7-Auto, ST72561K9-Auto,
ST72561J4-Auto, ST72561J6-Auto,
ST72561xx- ST72561J7-Auto, ST72561J9-Auto,
Auto ST72561R4-Auto, ST72561R6-Auto,
ST72561R7-Auto, ST72561R9-Auto,
ST72561AR4-Auto, ST72561AR6-Auto,
ST72561AR7-Auto, ST72561AR9-Auto
January 2011 |
Doc ID 12370 Rev 8 |
1/324 |
www.st.com
Contents |
ST72561-Auto |
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Contents
1 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
20 |
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1.1 |
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
22 |
2 |
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
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3 |
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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3.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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3.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
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3.3 |
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
32 |
3.3.1 Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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3.4 |
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
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3.5 |
ICP (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
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3.6 |
IAP (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
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3.7 |
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
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3.8 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
35 |
4 |
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.2 Index registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.3 Program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.4 Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.5 Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 |
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
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5.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
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5.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
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5.3 |
Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
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5.4 |
Multi-oscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
42 |
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5.5 |
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
5.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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5.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6 System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.6.1 Low voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6.2 Auxiliary voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.6.3 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.6.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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6.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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6.2 |
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
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6.3 |
Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
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6.4 |
Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
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6.5 |
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
6.5.1 CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.2 Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 55
6.6 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.6.1 I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.6.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 |
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
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7.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
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7.2 |
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
63 |
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7.3 |
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
64 |
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7.4 |
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
65 |
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7.5 |
Active halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
67 |
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7.6 |
Auto wake-up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
68 |
7.6.1 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8 |
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
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8.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
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8.2 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
8.2.1 Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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8.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4 I/O port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.4.1 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 8.4.2 Interrupt ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.4.3 Pull-up input port (CANTX requirement) . . . . . . . . . . . . . . . . . . . . . . . . 79
8.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9 |
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
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9.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
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9.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
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9.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
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9.4 |
Using halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
84 |
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9.5 |
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . |
84 |
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9.6 |
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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9.7 |
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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9.8 |
Using halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . . |
87 |
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9.9 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
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9.10 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
9.10.1 Control register (WDGCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.10.2 Window Register (WDGWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10 |
Main clock controller with real time clock MCC/RTC . . . . . . . . . . . . . . |
89 |
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10.1 |
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.2 |
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.3 |
Real time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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10.4 |
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
90 |
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10.5 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
90 |
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10.6 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
90 |
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10.6.1 MCC control/status register (MCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . |
90 |
11 |
PWM auto-reload timer (ART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.3 Counter and prescaler Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.4 Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2.5 Independent PWM signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.2.6 Output compare and Time base interrupt . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.7 External clock and event detector mode . . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.8 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.9 External interrupt capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
12 |
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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12.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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12.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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12.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
105 |
12.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.3 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.5 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.6 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.7 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.8 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.9 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.7.3 Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.7.4 Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.5 Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 122 12.7.6 Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 122 12.7.7 Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 122
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12.7.8 |
Output compare 2 high register (OC2HR) . . . . . . . . . . . . . |
. . . . . . . . . 122 |
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12.7.9 |
Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . |
. . . . . . . . . 123 |
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12.7.10 |
Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 123 |
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12.7.11 |
Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 123 |
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12.7.12 |
Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . |
. . . . . . . . 123 |
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12.7.13 |
Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . |
. . . . . . . . 124 |
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12.7.14 |
Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . |
. . . . . . . . 124 |
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12.7.15 |
Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . |
. . . . . . . . 124 |
13 |
8-bit timer (TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 126 |
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.3.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.3.2 Input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.3.3 Output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.3.4 Forced compare output capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.3.5 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.3.6 Pulse width modulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
13.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 13.6 Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 13.7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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13.7.1 Control register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 139 |
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13.7.2 Control register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
140 |
|
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13.7.3 |
Control/status register (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
141 |
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13.7.4 Input capture 1 register (IC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
142 |
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13.7.5 Output compare 1 register (OC1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
142 |
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13.7.6 Output compare 2 register (OC2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
|
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13.7.7 |
Counter register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
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13.7.8 Alternate counter register (ACTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
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13.7.9 Input capture 2 register (IC2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
143 |
|
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13.8 8-bit timer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
144 |
|
14 |
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
145 |
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
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14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 14.3.3 Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.3.4 Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.3.5 Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.3.6 Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
14.4 Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 14.5 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
14.5.1 Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 14.5.2 Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 14.5.3 Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
14.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 14.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
14.8.1 Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 14.8.2 Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 14.8.3 Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
15 |
LINSCI serial communication interface (LIN master/slave) . . . . . . . . |
158 |
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15.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
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15.2 |
SCI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
158 |
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15.3 |
LIN features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
159 |
|
15.4 |
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
159 |
|
15.5 |
SCI mode - functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
160 |
15.5.1 Conventional baud rate generator mode . . . . . . . . . . . . . . . . . . . . . . . 160 15.5.2 Extended prescaler mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.3 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15.5.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 15.5.6 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.5.7 Receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 166 15.5.8 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
15.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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15.8 SCI mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
15.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.8.4 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.8.5 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.8.6 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 174 15.8.7 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 175
15.9LIN mode - functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
15.9.1 |
Entering LIN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
175 |
15.9.2 |
LIN transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
15.9.3 |
LIN reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
177 |
15.9.4 |
LIN error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
15.9.5 |
LIN baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
182 |
15.9.6 |
LIN slave baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
182 |
15.9.7 |
LINSCI clock tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
183 |
15.9.8 |
Clock deviation causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
184 |
15.9.9 |
Error due to LIN synch measurement . . . . . . . . . . . . . . . . . . . . . . . . . |
185 |
15.9.10 |
Error due to baud rate quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . |
185 |
15.9.11 |
Impact of clock deviation on maximum baud rate . . . . . . . . . . . . . . . . |
185 |
15.10 LIN mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
15.10.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.10.2 Control Register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.10.3 Control Register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 15.10.4 Control register 3 (SCICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.10.5 LIN divider registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.6 LIN prescaler register (LPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.7 LIN prescaler fraction register (LPFR) . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.10.8 LIN header length register (LHLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
16 |
LINSCI serial communication interface (LIN master only) . . . . . . . . |
195 |
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16.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
195 |
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16.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
195 |
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16.3 |
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
196 |
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16.4 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
197 |
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16.4.1 Serial data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 198 |
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16.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.4.4 Conventional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 16.4.5 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.4.6 Receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 203 16.4.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.7 SCI synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 16.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 16.8.4 Control Register 3 (SCICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 16.8.5 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.8.6 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.8.7 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 214 16.8.8 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 214
17 |
beCAN controller (beCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
216 |
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17.1 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
216 |
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17.2 |
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
216 |
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17.3 |
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
218 |
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17.4 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
221 |
|
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17.4.1 |
Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 221 |
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17.4.2 |
Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 222 |
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17.4.3 |
Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
224 |
|
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17.4.4 |
Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
227 |
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17.4.5 |
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
229 |
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17.4.6 |
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
230 |
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17.5 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
232 |
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17.6 |
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
232 |
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17.7 |
beCAN cell limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
233 |
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17.7.1 |
FIFO corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
233 |
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17.8 |
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
238 |
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17.8.1 Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
238 |
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17.8.2 CAN transmit status register (CTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.8.3 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.8.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18 |
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
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18.1 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
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18.2 |
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
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18.3 |
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
18.3.1 Digital A/D conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 18.3.2 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.3.4 ADCDR consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
18.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
18.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 18.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
19 |
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
264 |
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19.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
264 |
19.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 19.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.5 Indirect (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 19.1.6 Indirect indexed (short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 19.1.7 Relative mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
19.2 Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
19.2.1 Using a prebyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
20 |
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
272 |
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20.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
272 |
20.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
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20.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 20.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
20.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
20.2.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 20.2.2 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 20.2.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
20.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
20.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 20.3.2 Operating conditions with low voltage detector (LVD) . . . . . . . . . . . . . 275 20.3.3 Auxiliary voltage detector (AVD) thresholds . . . . . . . . . . . . . . . . . . . . . 276
20.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
20.4.1 Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 20.4.2 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
20.5 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
20.5.1 Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 280 20.5.2 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
20.6 Auto wakeup from halt oscillator (AWU) . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
20.7.1 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 20.7.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
20.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
20.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 283 20.8.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 20.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 284
20.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
20.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 20.9.2 Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
20.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
20.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 20.10.2 ICCSEL/ VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
20.11 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 20.12 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 295
20.12.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 20.12.2 CAN - controller area network interface . . . . . . . . . . . . . . . . . . . . . . . . 297
20.13 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
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Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
302 |
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21.1 |
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 302 |
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21.2 |
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
302 |
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21.3 |
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
304 |
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21.4 |
Packaging for automatic handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
304 |
22 Device configuration and ordering information . . . . . . . . . . . . . . . . . 306
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 22.2 Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
22.2.1 Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 22.2.2 Flash ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
22.3 Transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
23 |
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
314 |
24 |
Important notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
315 |
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24.1 All devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
315 |
24.1.1 RESET pin protection with LVD enabled . . . . . . . . . . . . . . . . . . . . . . . 315 24.1.2 Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . 315 24.1.3 External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 24.1.4 Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 24.1.5 Header time-out does not prevent wake-up from mute mode . . . . . . . 318 24.1.6 CAN FIFO corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
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24.2 |
Flash/FastROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
320 |
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24.2.1 LINSCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. 320 |
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24.2.2 16-bit and 8-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
321 |
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24.3 |
ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
321 |
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24.3.1 16-bit timer PWM mode buffering feature change . . . . . . . . . . . . . . . . |
321 |
25 |
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
322 |
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3. Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 4. Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5. Sectors available in Flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6. Flash control/status register address and reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7. Interrupt software priority selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8. ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9. Effect of low power modes on SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 10. Interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 11. Reset source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 12. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 13. Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 14. Interrupt priority bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 15. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 16. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 17. Interrupt sensitivity - ei3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 18. Interrupt sensitivity - ei2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 19. Interrupt sensitivity - ei1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 20. Interrupt sensitivity - ei0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 21. Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 22. MCC/RTC low power mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 23. AWUPR prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 24. AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 25. DR register value and output pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 26. I/O port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 27. I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 28. Configuration of PB7:6, PC0, PC3, PC7:5, PD3:2, PD5, PE7:0, PF7:0 . . . . . . . . . . . . . . . 77 Table 29. Configuration of PA0, 2, 4, 6; PB0, 2,4; PC1; PD0,6 (with pull-up) . . . . . . . . . . . . . . . . . . 78 Table 30. Configuration of PA1, 3, 5, 7; PB1,3,5; PC2; PD1, 4, 7 (without pull-up) . . . . . . . . . . . . . . 78 Table 31. Configuration of PC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 32. Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 33. Effect of low power modes on I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 34. I/O port interrupt control/wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 35. I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 36. Effect of low power modes on WDG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 37. Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 38. Effect of low power modes on MCC/RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 39. MCC/RTC Interrupt control wake-up capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 40. CPU clock frequency in SLOW mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 41. Time base selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 42. Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 43. Counter clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 44. PWM frequency vs resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 45. PWMx output level and polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 46. PWM auto-reload timer register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 47. Effect of low power modes on 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 48. Timer interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
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Table 49. Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 50. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 51. 16-bit timer register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 52. Effect of low power modes on TIM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 53. TIM8 interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 54. Timer modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 55. Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 56. Effect of low power modes on SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Table 57. SPI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 58. SPI master mode SCK frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 59. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 60. Character formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 61. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 62. SCI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 63. PR prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 64. Transmitter rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 65. Receiver rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Table 66. LIN mode configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 67. LDIV mantissa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 68. LDIV fraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 69. LHL mantissa coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 70. LHL fraction coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 71. LINSCI1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 72. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 73. Effect of low power modes on SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 74. SCI interrupt control and wake-up capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 75. LIN sync break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Table 76. SCI clock on SCLK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 77. PR prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 78. Transmitter rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 79. Receiver rate divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 80. Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 81. LINSCI2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Table 82. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 83. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 84. While loop timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Table 85. LEC error types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 86. Filter page selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 87. beCAN control and status page - register map and reset values . . . . . . . . . . . . . . . . . . . 257 Table 88. beCAN mailbox pages - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Table 89. beCAN filter configuration page - register map and reset values . . . . . . . . . . . . . . . . . . . 258 Table 90. Effect of low power modes on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 91. A/D clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 92. ADC channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Table 93. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Table 94. Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Table 95. CPU addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Table 96. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 1) 267 Table 97. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 2) 267 Table 98. Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Table 99. Supply current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 100. Clock source current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
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Table 101. Peripheral consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Table 102. General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Table 103. External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Table 104. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Table 105. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Table 106. AWU oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Table 107. RAM supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Table 108. Dual voltage HDFlash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Table 109. EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 110. EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 111. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table 112. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table 113. I/O characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 114. Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Table 115. RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 116. ICCSEL/VPP pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Table 117. 8-bit PWM-ART auto reload timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 118. 8-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Table 119. 16-bit timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Table 120. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Table 121. CAN characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Table 122. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 123. ADC accuracy with fCPU = 8 MHz, fADC = 4 MHz RAIN < 10kW, VDD = 5V. . . . . . . . . . . . 300 Table 124. Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 125. Alternate function remapping 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 126. Alternate function remapping 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 127. OSCTYPE selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 128. OSCRANGE selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 129. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
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Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2. LQFP 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 3. LQFP 44-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 4. LQFP 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. Memory map and sector address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 7. Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 8. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 9. Stack manipulation example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 11. Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 12. RESET sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 13. Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 14. Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 15. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 16. Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 17. Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 18. Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 19. Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 20. Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 21. External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22. Power saving mode transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 23. SLOW mode clock transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 24. WAIT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 25. HALT timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 26. HALT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 27. ACTIVE HALT timing overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 28. ACTIVE HALT mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 29. AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 30. AWUF halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 31. AWUFH mode flow-chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 32. I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 33. Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 34. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 35. Approximate timeout duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 36. Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 37. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 38. Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 39. PWM auto-reload timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 40. Output compare control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 41. PWM auto-reload timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 42. PWM signal from 0% to 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 43. External event detector example (3 counts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 44. Input capture timing diagram, fCOUNTER = fCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 45. Input capture timing diagram, fCOUNTER = fCPU / 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 46. ART external interrupt in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 47. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 48. 16-bit read sequence: (from counter or alternate counter register) . . . . . . . . . . . . . . . . . 106
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Figure 49. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 50. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 51. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 52. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 53. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 54. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 55. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 56. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 57. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 58. Pulse width modulation mode timing example with 2 output compare functions . . . . . . . 115 Figure 59. Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 60. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 61. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 62. Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 63. Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 64. Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 65. Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 66. Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 67. Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 68. One pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 69. Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 70. Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 71. Single master/ single slave application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 72. Generic SS timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Figure 73. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 74. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 75. Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 152 Figure 76. Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 77. SCI block diagram (in conventional baud rate generator mode). . . . . . . . . . . . . . . . . . . . 160 Figure 78. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 79. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 80. LIN characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 81. SCI block diagram in LIN slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 82. LIN header reception timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Figure 83. LIN synch field measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 84. LDIV read / write operations when LDUM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 85. LDIV read / write operations when LDUM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 86. Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Figure 87. LSF bit set and clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 88. SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 89. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 90. SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 91. SCI example of synchronous and asynchronous transmission . . . . . . . . . . . . . . . . . . . . 206 Figure 92. SCI data clock timing diagram (M = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Figure 93. SCI data clock timing diagram (M = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Figure 94. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Figure 95. CAN block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 96. beCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 97. beCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 98. beCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 99. beCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 100. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
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Figure 101. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 102. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 103. Filtering mechanism - example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 104. CAN error state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Figure 105. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Figure 106. CAN frames (part 1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Figure 107. CAN frames (part 2/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Figure 108. Event flags and interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Figure 109. FIFO corruption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 110. Workaround 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 111. Critical window timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 112. Reception of a sequence of frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 113. Reception at maximum CAN baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 114. Workaround 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 115. CAN register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Figure 116. Page mapping for CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Figure 117. ADC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Figure 118. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Figure 119. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 120. fCPU maximum vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Figure 121. LVD startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Figure 122. Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Figure 123. Typical application with a crystal or ceramic resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Figure 124. PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Figure 125. AWU oscillator freq. @ TA 25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Figure 126. Connecting unused I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 127. RPU vs VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 128. IPU vs VDD with VIN = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 129. Typical VOL at VDD = 5V (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 130. Typical VOL at VDD = 5V (high-sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 131. Typical VOH at VDD = 5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 132. Typical VOL vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 133. Typical VOL vs VDD (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 134. Typical VOH vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Figure 135. RESET pin protection when LVD is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 136. RESET pin protection when LVD is enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 137. RESET RPU vs VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Figure 138. Two typical applications with ICCSEL/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Figure 139. SPI slave timing diagram with CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Figure 140. SPI slave timing diagram with CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Figure 141. SPI master timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Figure 142. RAIN max vs fADC with CAIN = 0pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Figure 143. Recommended CAIN/RAIN values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Figure 144. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Figure 145. Power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Figure 146. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Figure 147. 64-pin low profile quad flat package (14x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Figure 148. 32-pin low profile quad flat package (7x7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Figure 149. 44-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Figure 150. 64-pin low profile quad flat package (10 x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Figure 151. pin 1 orientation in tape and reel conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Figure 152. ST72F561xx-Auto Flash commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . 310
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Figure 153. ST72P561xxx-Auto FastROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . 311 Figure 154. ST72561xx-Auto ROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Figure 155. Header reception event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Figure 156. LINSCI interrupt routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
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Description |
ST72561-Auto |
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The ST72561xx-Auto devices are members of the ST7 microcontroller family designed for automotive mid-range applications with CAN (Controller Area Network) and LIN (Local Interconnect Network) interface.
All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
Table 2. |
Product overview |
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Features |
ST72561(AR/R/J/K)9 |
ST72561(AR/R/J/K)7 |
ST72561(AR/R/J/K)6 |
ST72561(AR/R/J/K)4 |
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Program memory - |
60K |
48K |
32K |
16K |
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bytes |
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RAM (stack) - bytes |
2K (256) |
2K (256) |
1K (256) |
1K (256) |
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Operating supply |
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4.5V to 5.5V |
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CPU frequency |
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External resonator oscillator w/ PLLx2/8 MHz |
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Maximum |
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-40°C to +125°C |
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temperature range |
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Packages |
LQFP64 10x10mm (AR), LQFP44 10x10mm (J), LQFP32 7x7mm (K) LQFP64 14x14 (R) |
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ST72561-Auto |
Description |
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Figure 1. |
Device block diagram |
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option |
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OSC1 |
PLL x 2 |
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PWM |
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OSC2 |
OSC |
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ART |
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/2 |
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8-Bit |
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TIMER |
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16-Bit |
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TIMER |
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PORT A |
PA7:0 |
VDD |
POWER |
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(8 bits)1 |
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VSS |
SUPPLY |
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PORT B |
PB7:0 |
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(8 bits)1 |
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PORT C |
PC7:0 |
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ADDRESS |
(8 bits)1 |
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RESET |
CONTROL |
PORT D |
PD7:0 |
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TLI1 |
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(8 bits)1 |
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8-BIT CORE |
AND |
PORT E |
PE7:0 |
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(8 bits)1 |
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ALU |
DATA |
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(8 bits)1 |
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PORT F |
PF7:0 |
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PROGRAM |
BUS |
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SPI |
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MEMORY |
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(16 - 60 Kbytes) |
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LINSCI2 |
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(LIN master) |
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RAM |
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LINSCI1 |
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(1 - 2 Kbytes) |
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(LIN master/slave) |
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WINDOW |
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MCC |
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WATCHDOG |
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(Clock Control) |
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CAN |
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(2.0B ACTIVE) |
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1. On some devices only (see Table 2: Product overview)
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Description |
ST72561-Auto |
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Figure 2. LQFP 64-pin package pinout
OSC1
OSC2 ARTIC1 / PA0 PWM0 / PA1
PWM1 / (HS) PA2 PWM2 / PA3
PWM3 / PA4 VSS_3
VDD_3
ARTCLK / (HS)PA5 ARTIC2 / (HS) PA6 T8_OCMP2 / PA7 T8_ICAP2 / PB0 T8_OCMP1 / PB1 T8_ICAP1 / PB2 MCO / PB3
PF7 |
PF6 |
/PD7AIN11 |
/PD6AIN10 |
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RESET |
/PD5LINSCI2 TDO |
V |
V |
V |
V |
/PD4LINSCI2 RDI |
(HS)/PD3 LINSCI2 SCK |
PF5 |
TLI |
PF4 |
/PF3AIN9 |
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DD0 |
DDA |
SS 0 |
SSA |
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ei3 |
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ei3 |
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ei3 |
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ei0 |
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ei1 |
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ei1 |
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ei2 |
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ei1 |
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AIN12 / PE0 |
AIN13 / PE1 |
ICCCLK / AIN0 / PB4 |
AIN14 / PE2 |
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AIN15 / PE3 |
ICCDATA / AIN1 / PB5 |
(*)T16 OCMP1 / AIN2 / PB6 |
SS2 |
DD2 |
(*)T16 OCMP2 / AIN3 / PB7 |
(*)T16 ICAP1 / AIN4 / PC0 |
(*)T16 ICAP2 / (HS) PC1 |
T16 EXTCLK / (HS) PC2 |
PE4 |
NC |
PP |
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V |
V |
ICCSEL/V |
PD2 / LINSCI1_TDO
PD1 / LINSCI1_RDI
PF2 / AIN8
PF1 / AIN7
PF0
PE7
PD0 / SPI_SS / AIN6
VDD_1
VSS_1
PC7 / SPI_SCK
PC6 / SPI_MOSI
PC5 / SPI_MISO
PE6 / AIN5
PE5
PC4 / CAN_TX
PC3 / CAN_RX
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
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Description |
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Figure 3. LQFP 44-pin package pinout
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1 |
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SCK |
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/PD7AIN11 /PD6AIN10 |
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RESET /PD5LINSCI2 TDO V |
V |
V |
V /PD4LINSCI2 RDI |
(HS)PD3 / LINSCI2_ |
PF5 |
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DD0 |
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DDA |
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SS 0 |
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SSA |
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OSC1 |
44 43 42 41 40 39 38 37 36 35 34 |
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1 |
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ei3 |
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ei3 |
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OSC2 |
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ei3 |
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PWM0 / PA1 |
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PWM1 / (HS) PA2 |
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PWM2 / PA3 |
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ei0 |
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ei3 |
29 |
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PWM3 / PA4 |
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6 |
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ARTCLK / (HS)PA5 |
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7 |
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ARTIC2 / (HS) PA6 |
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T8_OCMP1 / PB1 |
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T8_ICAP1 / PB2 |
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10 |
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ei1 |
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ei2 |
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24 |
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MCO / PB3 |
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11 |
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ei1 |
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12 13 14 15 16 17 18 19 20 21 22 |
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PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PF2 / AIN8
PF1 / AIN7
PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PE6 / AIN5
PC4 / CAN_TX
PC3 / CAN_RX
|
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|
SS2 |
DD2 |
|
ICCCLK / AIN0PB4/ |
ICCDATA / AIN1PB5/ |
(*)T16 OCMP1 / AIN2PB6/ |
V |
V (*)T16 OCMP2 / AIN3PB7/ (*)T16 ICAP1 / AIN4PC0/ (*)T16 ICAP2 / (HS)PC1 T16 EXTCLK / (HS)PC2 PE4 |
ICCSEL/VPP |
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
Doc ID 12370 Rev 8 |
23/324 |
Description |
ST72561-Auto |
|
|
Figure 4. LQFP 32-pin package pinout
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1 |
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PD5/ LINSCI2 TDO V |
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V PD4/ LINSCI2 RDI |
SCK |
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RESET |
V |
V |
PD3(HS) / LINSCI2_ |
||
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DD0 |
DDA |
SS0 |
SSA |
|
OSC1 |
|
32 31 30 29 28 27 26 25 |
|||||
1 |
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ei3 |
24 |
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OSC2 |
2 |
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23 |
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ei3 |
|||
PWM0 / PA1 |
3 |
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22 |
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PWM1 / (HS) PA2 |
4 |
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ei0 |
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21 |
ARTCLK / (HS) PA5 |
5 |
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20 |
T8_OCMP1 / PB1 |
6 |
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19 |
T8_ICAP1 / PB2 |
7 |
ei1 |
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ei2 |
18 |
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MCO / PB3 |
8 |
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ei1 |
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17 |
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|||
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9 |
10 11 12 13 14 15 16 |
PD2 / LINSCI1_TDO PD1 / LINSCI1_RDI PD0 / SPI_SS / AIN6 PC7 / SPI_SCK PC6 / SPI_MOSI PC5 / SPI_MISO PC4 / CAN_TX
PC3 / CAN_RX
ICCCLK / AIN0 / PB4 ICCDATA / AIN1 / PB5 T16 OCMP1 / AIN2 / PB6 T16 OCMP2 / AIN3 / PB7 T16 ICAP1 / AIN4 / PC0 |
T16 ICAP2 / (HS) PC1 |
T16 EXTCLK / (HS) PC2 |
PP |
ICCSEL/V |
(HS) 20mA high sink capability
eix associated external interrupt vector
(*) : by option bit:
T16_ICAP1 can be moved to PD4
T16_ICAP2 can be moved to PD1
T16_OCMP1 can be moved to PD3
T16_OCMP2 can be moved to PD5
For external pin connection guidelines, refer to Chapter 20: Electrical characteristics.
24/324 |
Doc ID 12370 Rev 8 |
ST72561-Auto |
Description |
|
|
List of abbreviations used in Table 3 |
|
Type: |
I = input, O = output, S = supply |
In/Output level: |
CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger |
|
TT= TTL 0.8V / 2V with Schmitt trigger |
Output level: |
HS = 20mA high sink (on N-buffer only) |
|
Port and control configuration: |
Input: |
float = floating, wpu = weak pull-up, int = interrupt, ana = analog, |
|
RB = robust |
Output: |
OD = open drain, PP = push-pull |
Refer to Chapter 8: I/O ports for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.
Table 3. |
|
Device pin description |
|
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||||
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Pin n° |
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Level |
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|
Port |
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Main |
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Type |
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LQFP64 |
|
LQFP44 |
|
LQFP32 |
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
||||
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wpu int |
OD |
PP |
(after |
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reset) |
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1 |
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1 |
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1 |
OSC1(2) |
I |
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External clock input or resonator |
||
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oscillator inverter input |
|
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2 |
|
2 |
|
2 |
OSC2(2) |
I/O |
|
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|
Resonator oscillator inverter output |
||
3 |
|
- |
|
- |
PA0 / ARTIC1 |
I/O |
CT |
|
X |
ei0 |
|
X |
X |
Port A0 |
ART input capture 1 |
||
4 |
|
3 |
|
3 |
PA1 / PWM0 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A1 |
ART PWM output 0 |
|
5 |
|
4 |
|
4 |
PA2 (HS) / PWM1 |
I/O |
CT |
HS |
X |
ei0 |
|
X |
X |
Port A2 |
ART PWM output 1 |
||
6 |
|
5 |
|
- |
PA3 / PWM2 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A3 |
ART PWM output 2 |
|
7 |
|
6 |
|
- |
PA4 / PWM3 |
I/O |
CT |
|
X |
ei0 |
|
X |
X |
Port A4 |
ART PWM output 3 |
||
8 |
|
- |
|
- |
VSS_3 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
|
|
9 |
|
- |
|
- |
VDD_3 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
||
10 |
|
7 |
|
5 |
PA5 (HS) / ARTCLK |
I/O |
CT |
HS |
X |
|
ei0 |
|
X |
X |
Port A5 |
ART external clock |
|
11 |
|
8 |
|
- |
PA6 (HS) / ARTIC2 |
I/O |
CT |
HS |
X |
ei0 |
|
X |
X |
Port A6 |
ART input capture 2 |
||
12 |
|
- |
|
- |
PA7 / T8_OCMP2 |
I/O |
CT |
|
X |
|
ei0 |
|
X |
X |
Port A7 |
TIM8 output capture 2 |
|
13 |
|
- |
|
- |
PB0 /T8_ICAP2 |
I/O |
CT |
|
X |
ei1 |
|
X |
X |
Port B0 |
TIM8 input capture 2 |
||
14 |
|
9 |
|
6 |
PB1 /T8_OCMP1 |
I/O |
CT |
|
X |
|
ei1 |
|
X |
X |
Port B1 |
TIM8 output capture 1 |
|
15 |
|
10 |
|
7 |
PB2 / T8_ICAP1 |
I/O |
CT |
|
X |
ei1 |
|
X |
X |
Port B2 |
TIM8 input capture 1 |
||
16 |
|
11 |
|
8 |
PB3 / MCO |
I/O |
CT |
|
X |
|
ei1 |
|
X |
X |
Port B3 |
Main clock out (fOSC2) |
|
17 |
|
- |
|
- |
PE0 / AIN12 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E0 |
ADC analog input 12 |
|
18 |
|
- |
|
- |
PE1 / AIN13 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E1 |
ADC analog input 13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC clock |
ADC |
19 |
|
12 |
|
9 |
PB4 / AIN0 / ICCCLK |
I/O |
CT |
|
X |
ei1 |
RB |
X |
X |
Port B4 |
analog |
||
|
|
|
input |
||||||||||||||
|
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|
input 0 |
|
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|
|
|
|
Doc ID 12370 Rev 8 |
25/324 |
Description |
|
|
|
|
|
|
|
|
|
|
|
|
|
ST72561-Auto |
||||||
|
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|
Table 3. |
|
|
Device pin description (continued) |
|
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|||||||||
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Pin n° |
|
|
|
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|
|
Level |
|
|
Port |
|
|
Main |
|
|
||||
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Type |
|
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|
LQFP64 |
|
LQFP44 |
|
LQFP32 |
|
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
||||||
|
|
|
|
|
|
wpu |
int |
OD |
PP |
(after |
|
|
||||||||
|
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reset) |
|
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|
|||
20 |
|
- |
|
- |
|
PE2 / AIN14 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E2 |
ADC analog input 14 |
|||
21 |
|
- |
|
- |
|
PE3 / AIN15 |
I/O |
TT |
|
X |
X |
|
RB |
X |
X |
Port E3 |
ADC analog input 15 |
|||
|
|
|
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|
|
|
|
|
ICC data |
ADC |
22 |
|
13 |
|
10 |
|
PB5 / AIN1 / ICCDATA |
I/O |
C |
|
X |
|
ei1 |
RB |
X |
X |
Port B5 |
analog |
|||
|
|
|
|
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|
T |
|
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|
input |
input 1 |
|
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PB6 / AIN2 / |
|
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|
|
|
|
|
|
|
TIM16 |
ADC |
||
23 |
|
14 |
|
11 |
|
I/O |
C |
|
X |
X |
|
RB |
X |
X |
Port B6 |
output |
analog |
|||
|
|
|
|
|
|
T16_OCMP1 |
|
T |
|
|
|
|
|
|
|
|
compare 1 |
input 2 |
||
|
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||
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||
24 |
|
15 |
|
- |
|
VSS_2 |
S |
|
|
|
|
|
|
|
|
Digital ground voltage |
||||
25 |
|
16 |
|
- |
|
VDD_2 |
S |
|
|
|
|
|
|
|
|
Digital main supply voltage |
||||
|
|
|
|
|
|
PB7 /AIN3 / |
|
|
|
|
|
|
|
|
|
|
TIM16 |
ADC |
||
26 |
|
17 |
|
12 |
|
I/O |
C |
|
X |
X |
|
RB |
X |
X |
Port B7 |
output |
analog |
|||
|
|
|
|
|
|
T16_OCMP2 |
|
T |
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compare 2 |
input 3 |
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PC0 / AIN4 / |
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TIM16 |
ADC |
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27 |
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18 |
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13 |
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I/O |
C |
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X |
X |
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RB |
X |
X |
Port C0 |
input |
analog |
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T16_ICAP1 |
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T |
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capture 1 |
input 4 |
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28 |
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19 |
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14 |
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PC1 (HS) / |
I/O |
C |
HS |
X |
ei2 |
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X |
X |
Port C1 |
TIM16 input capture 2 |
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T16_ICAP2 |
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T |
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29 |
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20 |
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15 |
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PC2 (HS) / |
I/O |
C |
HS |
X |
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ei2 |
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X |
X |
Port C2 |
TIM16 external clock |
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T16_EXTCLK |
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T |
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input |
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30 |
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21 |
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- |
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PE4 |
I/O |
TT |
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X |
X |
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X |
X |
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Port E4 |
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31 |
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- |
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- |
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NC |
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Not Connected |
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32 |
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22 |
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16 |
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VPP |
I |
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Flash programming voltage.Must |
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be tied low in user mode |
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33 |
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23 |
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17 |
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PC3 / CANRX |
I/O |
CT |
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X |
X |
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X |
X |
Port C3 |
CAN receive data input |
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34 |
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24 |
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18 |
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PC4 / CANTX |
I/O |
CT |
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X |
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X(3) |
Port C4 |
CAN transmit data |
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output |
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35 |
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- |
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- |
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PE5 |
I/O |
TT |
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X |
X |
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X |
X |
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Port E5 |
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36 |
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25 |
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- |
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PE6 / AIN5 |
I/O |
TT |
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X |
X |
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X |
X |
X |
Port E6 |
ADC analog input 5 |
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37 |
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26 |
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19 |
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PC5 /MISO |
I/O |
CT |
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X |
X |
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X |
X |
Port C5 |
SPI master in/slave out |
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38 |
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27 |
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20 |
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PC6 / MOSI |
I/O |
CT |
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X |
X |
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X |
X |
Port C6 |
SPI master out/slave in |
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39 |
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28 |
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21 |
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PC7 /SCK |
I/O |
CT |
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X |
X |
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X |
X |
Port C7 |
SPI serial clock |
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40 |
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- |
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- |
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VSS_1 |
S |
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Digital ground voltage |
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41 |
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- |
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- |
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VDD_1 |
S |
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Digital main supply voltage |
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SPI slave |
ADC |
42 |
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29 |
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22 |
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PD0 / |
SS/ |
AIN6 |
I/O |
C |
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X |
ei3 |
X |
X |
X |
Port D0 |
analog |
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T |
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select |
input 6 |
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26/324 |
Doc ID 12370 Rev 8 |
ST72561-Auto |
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Description |
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Table 3. |
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Device pin description (continued) |
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Pin n° |
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Level |
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Port |
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Main |
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Type |
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LQFP64 |
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LQFP44 |
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LQFP32 |
Pin name |
Input |
Output |
float |
Input(1) |
ana |
Output |
function |
Alternate function |
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wpu |
int |
OD |
PP |
(after |
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reset) |
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43 |
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- |
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- |
PE7 |
I/O |
TT |
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X |
X |
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X |
X |
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Port E7 |
44 |
|
- |
|
- |
PF0 |
I/O |
TT |
|
X |
X |
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X |
X |
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Port F0 |
45 |
|
30 |
|
- |
PF1 / AIN7 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F1 |
ADC analog input 7 |
46 |
|
31 |
|
- |
PF2 / AIN8 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F2 |
ADC analog input 8 |
47 |
|
32 |
|
23 |
PD1 / SCI1_RDI |
I/O |
CT |
|
X |
|
ei3 |
|
X |
X |
Port D1 |
LINSCI1 receive data |
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input |
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48 |
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33 |
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24 |
PD2 / SCI1_TDO |
I/O |
CT |
|
X |
X |
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X |
X |
Port D2 |
LINSCI1 transmit data |
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output |
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49 |
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- |
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- |
PF3 / AIN9 |
I/O |
TT |
|
X |
X |
|
X |
X |
X |
Port F3 |
ADC analog input 9 |
50 |
|
- |
|
- |
PF4 |
I/O |
TT |
|
X |
X |
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X |
X |
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Port F4 |
51 |
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- |
|
- |
TLI |
I |
CT |
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X |
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X |
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Top level interrupt input pin |
|
52 |
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34 |
|
- |
PF5 |
I/O |
TT |
|
X |
X |
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X |
X |
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Port F5 |
53 |
|
35 |
|
25 |
PD3 (HS) / SCI2_SCK |
I/O |
C |
HS |
X |
X |
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X |
X |
Port D3 |
LINSCI2 serial clock |
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T |
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output |
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54 |
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36 |
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26 |
PD4 / SCI2_RDI |
I/O |
CT |
|
X |
|
ei3 |
|
X |
X |
Port D4 |
LINSCI2 receive data |
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input |
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55 |
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37 |
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27 |
VSSA |
S |
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Analog ground voltage |
|
56 |
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38 |
|
28 |
VSS_0 |
S |
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Digital ground voltage |
|
57 |
|
39 |
|
29 |
VDDA |
I |
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Analog reference voltage for ADC |
|
58 |
|
40 |
|
30 |
VDD_0 |
S |
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Digital main supply voltage |
|
59 |
|
41 |
|
31 |
PD5 / SCI2_TDO |
I/O |
CT |
|
X |
X |
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|
X |
X |
Port D5 |
LINSCI2 transmit data |
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output |
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60 |
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42 |
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32 |
RESET |
I/O |
CT |
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Top priority non maskable |
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interrupt. |
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61 |
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43 |
|
- |
PD6 / AIN10 |
I/O |
CT |
|
X |
ei3 |
X |
X |
X |
Port D6 |
ADC analog input 10 |
|
62 |
|
44 |
|
- |
PD7 / AIN11 |
I/O |
CT |
|
X |
|
ei3 |
X |
X |
X |
Port D7 |
ADC analog input 11 |
63 |
|
- |
|
- |
PF6 |
I/O |
TT |
|
X |
X |
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|
X |
X |
|
Port F6 |
64 |
|
- |
|
- |
PF7 |
I/O |
TT |
|
X |
X |
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X |
X |
|
Port F7 |
1.In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2.OSC1 and OSC2 pins connect a crystal/ceramic resonator, or an external source to the on-chip oscillator; see Chapter 1: Description and Section 20.5: Clock and timing characteristics for more details.
3.Input mode can be used for general purpose I/O, output mode only for CANTX.
On the chip, each I/O port has eight pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption.
Doc ID 12370 Rev 8 |
27/324 |
Register and memory map |
ST72561-Auto |
|
|
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory.
The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.The highest address bytes contain the user reset and interrupt vectors.
Caution: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 5. |
Memory map |
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0000h |
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0080h |
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HW Registers |
Short Addressing |
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(see Table 4) |
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007Fh |
00FFh |
RAM (zero page) |
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0080h |
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RAM |
0100h |
256 bytes Stack |
1000h |
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(2048/1024 bytes) |
01FFh |
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60 Kbytes |
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|||
087Fh |
|
0200h |
16-bit Addressing |
4000h |
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48 Kbytes |
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||||||
0880h |
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||||||||
Reserved |
|
RAM |
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0FFFh |
047Fh |
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8000h |
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1000h |
Program Memory |
or 087Fh |
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32 Kbytes |
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FFDFh |
(60K, 48K, 32K, 16K) |
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C000h |
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FFE0h |
Interrupt & Reset Vectors |
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16 Kbytes |
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FFFFh |
(see Table 16) |
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FFDFh |
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Table 4. |
Hardware register map |
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||
Address |
Block |
Register |
Register name |
Reset |
Remarks(1) |
|
label |
status |
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|||
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0000h |
|
PADR |
Port A Data Register |
00h(2) |
R/W(3) |
|
0001h |
Port A |
PADDR |
Port A Data Direction Register |
00h |
R/W(3) |
|
0002h |
|
PAOR |
Port A Option Register |
00h |
R/W(3) |
|
0003h |
|
PBDR |
Port B Data Register |
00h(2) |
R/W(3) |
|
0004h |
Port B |
PBDDR |
Port B Data Direction Register |
00h |
R/W(3) |
|
0005h |
|
PBOR |
Port B Option Register |
00h |
R/W(3) |
|
0006h |
|
PCDR |
Port C Data Register |
00h(2) |
R/W(3) |
|
0007h |
Port C |
PCDDR |
Port C Data Direction Register |
00h |
R/W(3) |
|
0008h |
|
PCOR |
Port C Option Register |
00h |
R/W(3) |
|
0009h |
|
PDDR |
Port D Data Register |
00h(2) |
R/W(3) |
|
000Ah |
Port D |
PDDDR |
Port D Data Direction Register |
00h |
R/W(3) |
|
000Bh |
|
PDOR |
Port D Option Register |
00h |
R/W(3) |
|
000Ch |
|
PEDR |
Port E Data Register |
00h(2) |
R/W(3) |
|
000Dh |
Port E |
PEDDR |
Port E Data Direction Register |
00h |
R/W(3) |
|
000Eh |
|
PEOR |
Port E Option Register |
00h |
R/W(3) |
28/324 |
Doc ID 12370 Rev 8 |
ST72561-Auto |
|
Register and memory map |
||||
|
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|
Table 4. |
Hardware register map (continued) |
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|||
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Address |
Block |
Register |
Register name |
Reset |
Remarks(1) |
|
label |
status |
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000Fh |
|
PFDR |
Port F Data Register |
00h(2) |
R/W(3) |
|
0010h |
Port F |
PFDDR |
Port F Data Direction Register |
00h |
R/W(3) |
|
0011h |
|
PFOR |
Port F Option Register |
00h |
R/W(3) |
|
0012h |
|
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to |
Reserved Area (15 bytes) |
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||
0020h |
|
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|
0021h |
|
SPIDR |
SPI Data I/O Register |
xxh |
R/W |
|
0022h |
SPI |
SPICR |
SPI Control Register |
0xh |
R/W |
|
0023h |
|
SPICSR |
SPI Control/Status Register |
00h |
R/W |
|
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|
0024h |
FLASH |
FCSR |
Flash Control/Status Register |
00h |
R/W |
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0025h |
|
ISPR0 |
Interrupt Software Priority Register 0 |
FFh |
R/W |
|
0026h |
|
ISPR1 |
Interrupt Software Priority Register 1 |
FFh |
R/W |
|
0027h |
ITC |
ISPR2 |
Interrupt Software Priority Register 2 |
FFh |
R/W |
|
0028h |
ISPR3 |
Interrupt Software Priority Register 3 |
FFh |
R/W |
||
|
||||||
0029h |
|
EICR0 |
External Interrupt Control Register 0 |
00h |
R/W |
|
002Ah |
|
EICR1 |
External Interrupt Control Register 1 |
00h |
R/W |
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002Bh |
AWU |
AWUCSR |
Auto Wake up f. Halt Control/Status Register |
00h |
R/W |
|
002Ch |
AWUPR |
Auto Wake Up From Halt Prescaler |
FFh |
R/W |
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002Dh |
CKCTRL |
SICSR |
System Integrity Control / Status Register |
0xh |
R/W |
|
002Eh |
MCCSR |
Main Clock Control / Status Register |
00h |
R/W |
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002Fh |
WWDG |
WDGCR |
Watchdog Control Register |
7Fh |
R/W |
|
0030h |
WDGWR |
Watchdog Window Register |
7Fh |
R/W |
||
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||||||
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0031h |
|
PWMDCR3 |
Pulse Width Modulator Duty Cycle Register |
00h |
R/W |
|
|
3 |
|||||
0032h |
|
PWMDCR2 |
00h |
R/W |
||
|
PWM Duty Cycle Register 2 |
|||||
0033h |
|
PWMDCR1 |
00h |
R/W |
||
|
PWM Duty Cycle Register 1 |
|||||
0034h |
|
PWMDCR0 |
00h |
R/W |
||
|
PWM Duty Cycle Register 0 |
|||||
0035h |
PWM |
PWMCR |
00h |
R/W |
||
PWM Control register |
||||||
0036h |
ARTCSR |
00h |
R/W |
|||
ART |
Auto-Reload Timer Control/Status Register |
|||||
0037h |
ARTCAR |
00h |
R/W |
|||
|
Auto-Reload Timer Counter Access Register |
|||||
0038h |
|
ARTARR |
00h |
R/W |
||
|
Auto-Reload Timer Auto-Reload Register |
|||||
0039h |
|
ARTICCSR |
00h |
R/W |
||
|
ART Input Capture Control/Status Register |
|||||
003Ah |
|
ARTICR1 |
00h |
Read Only |
||
|
ART Input Capture Register 1 |
|||||
003Bh |
|
ARTICR2 |
00h |
Read Only |
||
|
ART Input Capture register 2 |
|||||
|
|
|
|
|
||
|
|
|
|
|
|
|
003Ch |
|
T8CR2 |
Timer Control Register 2 |
00h |
R/W |
|
003Dh |
|
T8CR1 |
Timer Control Register 1 |
00h |
R/W |
|
003Eh |
|
T8CSR |
Timer Control/Status Register |
00h |
Read Only |
|
003Fh |
8-BIT |
T8IC1R |
Timer Input Capture 1 Register |
xxh |
Read Only |
|
0040h |
T8OC1R |
Timer Output Compare 1 Register |
00h |
R/W |
||
TIMER |
||||||
0041h |
T8CTR |
Timer Counter Register |
FCh |
Read Only |
||
|
||||||
0042h |
|
T8ACTR |
Timer Alternate Counter Register |
FCh |
Read Only |
|
0043h |
|
T8IC2R |
Timer Input Capture 2 Register |
xxh |
Read Only |
|
0044h |
|
T8OC2R |
Timer Output Compare 2 Register |
00h |
R/W |
|
|
|
|
|
|
|
|
0045h |
|
ADCCSR |
Control/Status Register |
00h |
R/W |
|
0046h |
ADC |
ADCDRH |
Data High Register |
00h |
Read Only |
|
0047h |
|
ADCDRL |
Data Low Register |
00h |
Read Only |
|
|
|
|
|
|
|
Doc ID 12370 Rev 8 |
29/324 |
Register and memory map |
|
|
ST72561-Auto |
|||
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|
|
|
|
Table 4. |
Hardware register map (continued) |
|
|
|
||
|
|
|
|
|
|
|
Address |
Block |
Register |
Register name |
Reset |
|
Remarks(1) |
label |
status |
|
||||
|
|
|
|
|
||
|
|
|
|
|
|
|
0048h |
|
SCI1ISR |
SCI1 Status Register |
C0h |
|
Read Only |
0049h |
|
SCI1DR |
SCI1 Data Register |
xxh |
|
R/W |
004Ah |
LINSCI1 |
SCI1BRR |
SCI1 Baud Rate Register |
00h |
|
R/W |
004Bh |
SCI1CR1 |
SCI1 Control Register 1 |
xxh |
|
R/W |
|
(LIN |
|
|||||
004Ch |
SCI1CR2 |
SCI1 Control Register 2 |
00h |
|
R/W |
|
Master/Slave) |
|
|||||
004Dh |
SCI1CR3 |
SCI1Control Register 3 |
00h |
|
R/W |
|
004Eh |
|
SCI1ERPR |
SCI1 Extended Receive Prescaler Register |
00h |
|
R/W |
004Fh |
|
SCI1ETPR |
SCI1 Extended Transmit Prescaler Register |
00h |
|
R/W |
|
|
|
|
|
|
|
0050h |
|
|
Reserved Area (1 byte) |
|
|
|
|
|
|
|
|
|
|
0051h |
|
T16CR2 |
Timer Control Register 2 |
00h |
|
R/W |
0052h |
|
T16CR1 |
Timer Control Register 1 |
00h |
|
R/W |
0053h |
|
T16CSR |
Timer Control/Status Register |
00h |
|
R/W |
0054h |
|
T16IC1HR |
Timer Input Capture 1 High Register |
xxh |
|
Read Only |
0055h |
|
T16IC1LR |
Timer Input Capture 1 Low Register |
xxh |
|
Read Only |
0056h |
|
T16OC1HR |
Timer Output Compare 1 High Register |
80h |
|
R/W |
0057h |
16-BIT |
T16OC1LR |
Timer Output Compare 1 Low Register |
00h |
|
R/W |
0058h |
T16CHR |
Timer Counter High Register |
FFh |
|
Read Only |
|
TIMER |
|
|||||
0059h |
T16CLR |
Timer Counter Low Register |
FCh |
|
Read Only |
|
|
|
|||||
005Ah |
|
T16ACHR |
Timer Alternate Counter High Register |
FFh |
|
Read Only |
005Bh |
|
T16ACLR |
Timer Alternate Counter Low Register |
FCh |
|
Read Only |
005Ch |
|
T16IC2HR |
Timer Input Capture 2 High Register |
xxh |
|
Read Only |
005Dh |
|
T16IC2LR |
Timer Input Capture 2 Low Register |
xxh |
|
Read Only |
005Eh |
|
T16OC2HR |
Timer Output Compare 2 High Register |
80h |
|
R/W |
005Fh |
|
T16OC2LR |
Timer Output Compare 2 Low Register |
00h |
|
R/W |
|
|
|
|
|
|
|
0060h |
|
SCI2SR |
SCI2 Status Register |
C0h |
|
Read Only |
0061h |
|
SCI2DR |
SCI2 Data Register |
xxh |
|
R/W |
0062h |
LINSCI2 |
SCI2BRR |
SCI2 Baud Rate Register |
00h |
|
R/W |
0063h |
SCI2CR1 |
SCI2 Control Register 1 |
xxh |
|
R/W |
|
0064h |
(LIN Master) |
SCI2CR2 |
SCI2 Control Register 2 |
00h |
|
R/W |
0065h |
|
SCI2CR3 |
SCI2 Control Register 3 |
00h |
|
R/W |
0066h |
|
SCI2ERPR |
SCI2 Extended Receive Prescaler Register |
00h |
|
R/W |
0067h |
|
SCI2ETPR |
SCI2 Extended Transmit Prescaler Register |
00h |
|
R/W |
|
|
|
|
|
|
|
30/324 |
Doc ID 12370 Rev 8 |