ST ST6255C, ST6265C, ST6265B User Manual
safe reset, auto-reload timer, EEPROM and SPI
(See end of Datasheet for Ordering Information)
PDIP28
PS028
CDIP28W
SS0P28
Features
■ 3.0 to 6.0V supply operating range
■ 8 MHz maximum clock frequency
■ -40 to +125°C operating temperature range
■ Run, Wait and Stop modes
■ 5 interrupt vectors
■ Look-up table capability in program memory
■ Data storage in program memory:
user selectable size
■ Data RAM: 128 bytes
■ Data EEPROM: 128 bytes (not in ST6255C)
■ User programmable options
■ 21 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
■ 8 I/O lines can sink up to 30 mA to drive LEDs or
TRIACs directly
– 8-bit Timer/Counter with 7-bit programmable
prescaler
■ 8-bit Auto-reload timer with 7-bit programmable
prescaler (AR Timer)
■ Digital watchdog
■ Oscillator safe guard (not in ST6265B ROM
devices)
■ Low voltage detector for safe reset (not in
ST6265B ROM devices)
■
8-bit A/D converter with 13 analog inputs
■ 8-bit synchronous peripheral interface (SPI)
■ On-chip clock oscillator can be driven by quartz
crystal, ceramic resonator or RC network
■ User configurable power-on reset
■ One external non-maskable interrupt
■ ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
ST6255C ST6265C
ST6265B
8-bit MCUs with ADC,
Table 1. Device summary
OTP/EPROM/ROM
Partnumber
ST6255C 3884 ST6265C 3884 128
ST6265B 3884 128
program memory
(Bytes)
EEPROM
(Bytes)
March 2009 Rev 3 1/84
Table of Contents
Document
Page
ST6255C ST6265C
ST6265B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 17
3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.5 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.1 OTP/EPROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.2 FASTROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.3 ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
84
2/84
1 GENERAL DESCRIPTION
TEST
NMI
INTERRUPT
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY
OSCILLATOR
RESET
DATA ROM
USER
SELECTABLE
DATA RAM
PORT A
PORT B
TIMER
DIGITAL
8 BIT CORE
TEST/V
PP
8-BIT
A/D CONVERTER
PA0..PA7 / Ain
PB0..PB5 / 30 mA Sink
VDDVSSOSCin OSCout RESET
WATCHDOG
MEMORY
PB6 / ARTimin / 30 mA Sink
PORT C
PC2 / Sin / Ain
PC3 / Sout / Ain
SPI (SERIAL
PERIPHERAL
INTERFACE)
AUTORELOAD
TIMER
PC4 / Sck / Ain
PB7 / ARTimout / 30 mA Sink
128 Bytes
3884 bytes
(ST62T55C, T65C,
DATA EEPROM
128 Bytes
PC0 / Ain
PC1 / Tim1 / Ain
(ST62T65C/E65C)
E65C)
1.1 INTRODUCTION
ST6255C ST6265C ST6265B
The ST6255C, and ST6265C devices are low cost
members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip peripherals.
The ST62E65C is the erasable EPROM version of
the ST62T65C OTP device, which may be used to
emulate the ST62T55C and ST62T65C OTP devices, as well as the respective ST6255C and
ST6265C ROM devices.
OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options de-
Figure 1. Block Diagram
j
fined in the programmable option byte of the OTP/
EPROM versions.
OTP devices offer all the advantages of user programmability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit programmable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T55C), a
serial port communication interface, an 8-bit A/D
Converter with 13 analog inputs and a Digital
Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
3/84
ST6255C ST6265C ST6265B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PB0
PB1
V
PP
/TEST
PB2
PB3
Ain / PA0
V
DD
PB4
PB5
ARTIMin/PB6
PC0/Ain
PC1/TIM1/Ain
PC2/Sin/Ain
PC3/Sout/Ain
PC4/Sck/Ain
PA7/Ain
PA6/Ain
PA5/Ain
PA4/Ain
PA3/Ain
28
27
26
25
24
23
22
21
ARTIMout/PB7
V
SS
Ain/PA1
Ain/PA2
NMI
RESET
OSCout
OSCin
1.2 PIN DESCRIPTIONS
V
and VSS. Power is supplied to the MCU via
DD
these two pins. V
is the ground connection.
V
SS
OSCin and OSCout. These pins are internally
connected to the on-chip oscillator circuit. A quartz
crystal, a ceramic resonator or an external clock
signal can be connected between these two pins.
The OSCin pin is the input pin, the OSCout pin is
the output pin.
RESET
. The active-low RESET pin is used to re-
start the microcontroller.
TEST/V
. The TEST must be held at VSS for nor-
PP
mal operation. If TEST pin is connected to a
+12.5V level during the reset phase, the EPROM/
OTP programming Mode is entered.
NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non
maskable interrupt to the MCU. The NMI input is
falling edge sensitive. It is provided with an on-chip
pullup resistor (if option has been enabled), and
Schmitt trigger characteristics.
PA0-PA7. These 8 lines are organized as one I/O
port (A). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, analog inputs for the A/D converter.
PB0-PB5. These 6 lines are organized as one I/O
port (B). Each line may be configured under software control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs.
PB0-PB5 can also sink 30mA for direct LED
driving.
is the power connection and
DD
PB6/ARTIMin, PB7/ARTIMout. These pins are either Port B I/O bits or the Input and Output pins of
the AR TIMER. To be used as timer input function
PB6 has to be programmed as input with or without pull-up. A dedicated bit in the AR TIMER Mode
Control Register sets PB7 as timer output function.
PB6-PB7 can also sink 30mA for direct LED driving.
PC0-PC4. These 5 lines are organized as one I/O
port (C). Each line may be configured under software control as input with or without internal pullup resistor, interrupt generating input with pull-up
resistor, analog input for the A/D converter, opendrain or push-pull output.
PC1 can also be used as Timer I/O bit while
PC2-PC4 can also be used as respectively Data
in, Data out and Clock I/O pins for the on-chip SPI
to carry the synchronous serial I/O signals.
Figure 2. Pin Configuration
4/84
1.3 MEMORY MAP
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS
ACCUMULATOR
DATA RAM
BANK SELECT
WINDOW SELECT
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
DATA READ-ONLY
WINDOW
RAM / EEPROM
BANKING AREA
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
0-63
DATA SPACE
0000h
0FF0h
0FFFh
MEMORY
MEMORY
DATA READ-ONLY
MEMORY
ST6255C ST6265C ST6265B
1.3.1 Introduction
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three memory spaces is
described in the following paragraphs.
Figure 3. Memory Addressing Diagram
Briefly, Program space contains user program
code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for subroutine and interrupt service routine nesting.
5/84
ST6255C ST6265C ST6265B
0000h
RESERVED
*
USER
PROGRAM MEMORY
3872 BYTES
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED
*
RESERVED
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
(*) Reserved areas should be filled with 0FFh
0080h
007Fh
MEMORY MAP (Cont’d)
1.3.2 Program Space
Program Space comprises the instructions to be
executed, the data required for immediate addressing mode instructions, the reserved factory
test area and the user vectors. Program Space is
addressed via the 12-bit Program Counter register
(PC register).
Program Memory Protection
The Program Memory in OTP or EPROM devices
can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.
In the EPROM parts, READOUT PROTECTION
option can be deactivated only by U.V. erasure
that also results into the whole EPROM context
erasure.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelectronics,
to gain access to the OTP contents. Returned
parts with a protection set can therefore not be accepted.
Figure 4. Program Memory Map
6/84
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space comprises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently contains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
Data RAM/EEPROM
In ST62T55C, ST62T65C and ST62E65C devices, the data space includes 60 bytes of RAM, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the
interrupt option register and the Data ROM Window register (DRW register).
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located between addresses 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. Additional RAM/EEPROM Banks
Device RAM EEPROM
ST62T55C 1 x 64 bytes ST62T65C/E65C 1 x 64 bytes 2 x 64 bytes
ST6255C ST6265C ST6265B
Table 2. Data Memory Space
RAM and EEPROM
DATA ROM WINDOW AREA
X REGISTER 080h
Y REGISTER 081h
V REGISTER 082h
W REGISTER 083h
DATA RAM 60 BYTES
PORT A DATA REGISTER 0C0h
PORT B DATA REGISTER 0C1h
PORT C DATA REGISTER 0C2h
RESERVED 0C3h
PORT A DIRECTION REGISTER 0C4h
PORT B DIRECTION REGISTER 0C5h
PORT C DIRECTION REGISTER 0C6h
RESERVED 0C7h
INTERRUPT OPTION REGISTER 0C8h*
DATA ROM WINDOW REGISTER 0C9h*
RESERVED
PORT A OPTION REGISTER 0CCh
PORT B OPTION REGISTER 0CDh
PORT C OPTION REGISTER 0CEh
RESERVED 0CFh
A/D DATA REGISTER 0D0h
A/D CONTROL REGISTER 0D1h
TIMER PRESCALER REGISTER 0D2h
TIMER COUNTER REGISTER 0D3h
TIMER STATUS CONTROL REGISTER 0D4h
AR TIMER MODE CONTROL REGISTER 0D5h
AR TIMER STATUS/CONTROL REGISTER1 0D6h
AR TIMER STATUS/CONTROL REGISTER2 0D7h
WATCHDOG REGISTER 0D8h
AR TIMER RELOAD/CAPTURE REGISTER 0D9h
AR TIMER COMPARE REGISTER 0DAh
AR TIMER LOAD REGISTER 0DBh
OSCILLATOR CONTROL REGISTER 0DCh*
MISCELLANEOUS 0DDh
RESERVED
SPI DATA REGISTER 0E0h
SPI DIVIDER REGISTER 0E1h
SPI MODE REGISTER 0E2h
RESERVED
DATA RAM/EEPROM REGISTER 0E8h*
RESERVED 0E9h
EEPROM CONTROL REGISTER 0EAh
RESERVED
ACCUMULATOR 0FFh
* WRITE ONLY REGISTER
000h
03Fh
040h
07Fh
084h
0BFh
0CAh
0CBh
0DEh
0DFh
0E3h
0E7h
0EBh
0FEh
7/84
ST6255C ST6265C ST6265B
DATA ROM
WINDOW REGISTER
CONTENTS
DATA SPACE ADDRESS
40h-7Fh
IN INSTRUCTION
PROGRAM SPACE ADDRESS
765432 0
543210
543210
READ
1
67891011
0
1
VR01573C
12
1
0
DATA SPACE ADDRESS
:
:
59h
000
0
1
00
1
11
Example:
(DWR)
DWR=28h
11
0000000
1
ROM
ADDRESS:A19h
11
13
0
1
MEMORY MAP (Cont’d)
1.3.5 Data Window Register (DWR)
The Data read-only memory window is located from
address 0040h to address 007Fh in Data space. It
allows direct reading of 64 consecutive bytes located anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program
memory can therefore be used to store either instructions or read-only data. Indeed, the window
can be moved in steps of 64 bytes along the program memory by writing the appropriate code in the
Data Window Register (DWR).
The DWR can be addressed like any RAM location
in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the
64-byte read-only data window (from address 40h
to address 7Fh of the Data space) in program
memory in 64-byte steps. The effective address of
the byte to be read as data in program memory is
obtained by concatenating the 6 least significant
bits of the register address given in the instruction
(as least significant bits) and the content of the
DWR register (as most significant bits), as illustrated in Figure 5 below. For instance, when address-
ing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be
written to prior to the first access to the Data readonly memory window area.
Data Window Register (DWR)
Address: 0C9h — Write Only
70
- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0
Bits 6, 7 = Not used.
Bit 5-0 = DWR5-DWR0: Data read-only memory
Window Register Bits. These are the Data read-
only memory Window bits that correspond to the
upper bits of the data read-only memory space.
Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to
address this register.
Note: Care is required when handling the DWR
register as it is write only. For this reason, the
DWR contents should not be changed while executing an interrupt service routine, as the service
routine cannot save and then restore the register’s
previous contents. If it is impossible to avoid writing to the DWR during the interrupt service routine,
an image of the register must be saved in a RAM
location, and each time the program writes to the
DWR, it must also write to the image register. The
image register must be written first so that, if an interrupt occurs between the two instructions, the
DWR is not affected.
Figure 5. Data read-only memory Window Memory Addressing
8/84
ST6255C ST6265C ST6265B
MEMORY MAP (Cont’d)
1.3.6 Data RAM/EEPROM Bank Register (DRBR)
Address: E8h — Write only
70
---
DRBR
4
--
DRBR1DRBR
0
Bit 7-5 = These bits are not used
Bit 4 - DRBR4. This bit, when set, selects RAM
Page 2.
Bit 3-2 - Reserved. These bits are not used.
Bit 1 - DRBR1. This bit, when set, selects
EEPROM Page 1, when available.
Bit 0 - DRBR0. This bit, when set, selects
EEPROM Page 0, when available.
The selection of the bank is made by programming
the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should
be set at a time.
The DRBR register can be addressed like a RAM
Data Space at the address E8h; nevertheless it is
a write only register that cannot be accessed with
single-bit operations. This register is used to select
the desired 64-byte RAM/EEPROM bank of the
Data Space. The bank number has to be loaded in
the DRBR register and the instruction has to point
to the selected location as if it was in bank 0 (from
00h address to 3Fh address).
This register is not cleared during the MCU initialization, therefore it must be written before the first
access to the Data Space bank region. Refer to
the Data Space description for additional information. The DRBR register is not modified when an
interrupt or a subroutine occurs.
Notes:
Care is required when handling the DRBR register
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing interrupt service routine, as the service routine cannot save and then restore its previous content. If it
is impossible to avoid the writing of this register in
interrupt service routine, an image of this register
must be saved in a RAM location, and each time
the program writes to DRBR it must write also to
the image register. The image register must be
written first, so if an interrupt occurs between the
two instructions the DRBR is not affected.
In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel,
producing errors.
Care must also be taken not to change the
E²PROM page (when available) when the parallel
writing mode is set for the E²PROM, as defined in
EECTL register.
Table 3. Data RAM Bank Register Set-up
DRBR ST62T55C ST62T65C/E65C
00 None None
01 Not Available EEPROM Page 0
02 Not Available EEPROM Page 1
08 Not Available Not Available
10h RAM Page 2 RAM Page 2
other Reserved Reserved
9/84
ST6255C ST6265C ST6265B
MEMORY MAP (Cont’d)
1.3.7 EEPROM Description
EEPROM memory is located in 64-byte pages in
data space. This memory may be used by the user
program for non-volatile data storage.
Data space from 00h to 3Fh is paged as described
in Table 4. EEPROM locations are accessed di-
rectly by addressing these paged sections of data
space.
The EEPROM does not require dedicated instructions for read or write access. Once selected via the
Data RAM Bank Register, the active EEPROM
page is controlled by the EEPROM Control Register (EECTL), which is described below.
Bit E20FF of the EECTL register must be reset prior
to any write or read access to the EEPROM. If no
bank has been selected, or if E2OFF is set, any access is meaningless.
Programming must be enabled by setting the
E2ENA bit of the EECTL register.
The E2BUSY bit of the EECTL register is set when
the EEPROM is performing a programming cycle.
Any access to the EEPROM when E2BUSY is set
is meaningless.
Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time.
Writing to the EEPROM may be carried out in two
modes: Byte Mode (BMODE) and Parallel Mode
(PMODE). In BMODE, one byte is accessed at a
time, while in PMODE up to 8 bytes in the same
row are programmed simultaneously (with consequent speed and power consumption advantages,
the latter being particularly important in battery
powered circuits).
General Notes:
Data should be written directly to the intended ad-
dress in EEPROM space. There is no buffer memory between data RAM and the EEPROM space.
When the EEPROM is busy (E2BUSY = “1”)
EECTL cannot be accessed in write mode, it is
only possible to read the status of E2BUSY. This
implies that as long as the EEPROM is busy, it is
not possible to change the status of the EEPROM
Control Register. EECTL bits 4 and 5 are reserved
and must never be set.
Care is required when dealing with the EECTL register, as some bits are write only. For this reason,
the EECTL contents must not be altered while executing an interrupt service routine.
If it is impossible to avoid writing to this register
within an interrupt service routine, an image of the
register must be saved in a RAM location, and
each time the program writes to EECTL it must
also write to the image register. The image register
must be written to first so that, if an interrupt occurs between the two instructions, the EECTL will
not be affected.
Table 4. Row Arrangement for Parallel Writing of EEPROM Locations
Dataspace
addresses.
Banks 0 and 1.
Byte01234567
ROW7 38h-3Fh
ROW6 30h-37h
ROW5 28h-2Fh
ROW4 20h-27h
ROW3 18h-1Fh
ROW2 10h-17h
ROW1 08h-0Fh
ROW0 00h-07h
Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.
The number of available 64-byte banks (1 or 2) is device dependent.
Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest
power-consumption.
10/84
MEMORY MAP (Cont’d)
Additional Notes on Parallel Mode:
If the user wishes to perform parallel programming, the first step should be to set the E2PAR2
bit. From this time on, the EEPROM will be addressed in write mode, the ROW address and the
data will be latched and it will be possible to
change them only at the end of the programming
cycle or by resetting E2PAR2 without programming the EEPROM. After the ROW address is
latched, the MCU can only “see” the selected
EEPROM row and any attempt to write or read
other rows will produce errors.
The EEPROM should not be read while E2PAR2
is set.
As soon as the E2PAR2 bit is set, the 8 volatile
ROW latches are cleared. From this moment on,
the user can load data in all or in part of the ROW.
Setting E2PAR1 will modify the EEPROM registers corresponding to the ROW latches accessed
after E2PAR2. For example, if the software sets
E2PAR2 and accesses the EEPROM by writing to
addresses 18h, 1Ah and 1Bh, and then sets
E2PAR1, these three registers will be modified simultaneously; the remaining bytes in the row will
be unaffected.
Note that E2PAR2 is internally reset at the end of
the programming cycle. This implies that the user
must set the E2PAR2 bit between two parallel programming cycles. Note that if the user tries to set
E2PAR1 while E2PAR2 is not set, there will be no
programming cycle and the E2PAR1 bit will be unaffected. Consequently, the E2PAR1 bit cannot be
set if E2ENA is low. The E2PAR1 bit can be set by
the user, only if the E2ENA and E2PAR2 bits are
also set.
Notes: The EEPROM page shall not be changed
through the DRBR register when the E2PAR2 bit
is set.
ST6255C ST6265C ST6265B
EEPROM Control Register (EECTL)
Address: EAh — Read/Write
Reset status: 00h
70
E2O
D7
FF
D5 D4
Bit 7 = D7: Unused.
Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.
If this bit is set the EEPROM is disabled (any access
will be meaningless) and the power consumption of
the EEPROM is reduced to its lowest value.
Bit 5-4 = D5-D4: Reserved. MUST be kept reset.
Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.
Once in Parallel Mode, as soon as the user software
sets the E2PAR1 bit, parallel writing of the 8 adjacent registers will start. This bit is internally reset at
the end of the programming procedure. Note that
less than 8 bytes can be written if required, the undefined bytes being unaffected by the parallel programming cycle; this is explained in greater detail in
the Additional Notes on Parallel Mode overleaf.
Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE
ONLY. This bit must be set by the user program in
order to perform parallel programming. If E2PAR2
is set and the parallel start bit (E2PAR1) is reset,
up to 8 adjacent bytes can be written simultaneously. These 8 adjacent bytes are considered as a
row, whose address lines A7, A6, A5, A4, A3 are
fixed while A2, A1 and A0 are the changing bits, as
illustrated in Figure 4. E2PAR2 is automatically reset at the end of any parallel programming procedure. It can be reset by the user software before
starting the programming procedure, thus leaving
the EEPROM registers unchanged.
Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON-
LY. This bit is automatically set by the EEPROM
control logic when the EEPROM is in programming mode. The user program should test it before
any EEPROM read or write operation; any attempt
to access the EEPROM while the busy bit is set
will be aborted and the writing procedure in
progress will be completed.
Bit 0 = E2ENA:
EEPROM Enable Bit. WRITE ONLY. This bit enables programming of the EEPROM
cells. It must be set before any write to the EEPROM register. Any attempt to write to the EEP-
E2PAR1E2PAR2E2BUSYE2E
NA
11/84
ST6255C ST6265C ST6265B
ROM when E2ENA is low is meaningless and will
not trigger a write cycle.
LVD. LVD RESET enable.When this bit is set, safe
RESET is performed by MCU when the supply
voltage is too low. When this bit is cleared, only
1.4 PROGRAMMING MODES
1.4.1 Option Bytes
The two Option Bytes allow configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when
the chip reset is activated.
It can only be accessed during the programming
mode. This access is made either automatically
(copy from a master device) or by selecting the
OPTION BYTE PROGRAMMING mode of the programmer.
The option bytes are located in a non-user map.
No address has to be specified.
power-on reset or external RESET are active.
PROTECT. Readout Protection. This bit allows the
protection of the software contents against piracy.
When the bit PROTECT is set high, readout of the
OTP contents is prevented by hardware. When
this bit is low, the user program can be read.
EXTCNTL. External STOP MODE control. When
EXTCNTL is high, STOP mode is available with
watchdog active by setting NMI pin to one. When
EXTCNTL is low, STOP mode is not available with
the watchdog active.
PB2-3 PULL. When set this bit removes pull-up at
reset on PB2-PB3 pins. When cleared PB2-PB3
pins have an internal pull-up resistor at reset.
PB0-1 PULL. When set this bit removes pull-up at
EPROM Code Option Byte (LSB)
70
PRO-
EXTC-
PB2-3
TECT
NTL
PULL
PB0-1
PULL
WDACT
DELAY
OSCIL OSGEN
reset on PB0-PB1 pins. When cleared PB0-PB1
pins have an internal pull-up resistor at reset.
WDACT. This bit controls the watchdog activation.
When it is high, hardware activation is selected.
The software activation is selected when WDACT
is low.
DELAY. This bit enables the selection of the delay
EPROM Code Option Byte (MSB)
internally generated after the internal reset (external pin, LVD, or watchdog activated) is released.
15 8
--SYNCHRO
ADC
--
NMI
PULL
LVD
When DELAY is low, the delay is 2048 cycles of
the oscillator, it is of 32768 cycles when DELAY is
high.
OSCIL. Oscillator selection. When this bit is low,
D15-D13. Reserved. Must be cleared.
ADC SYNCHRO. When set, an A/D conversion is
started upon WAIT instruction execution, in order
to reduce supply noise. When this bit is low, an A/
D conversion is started as soon as the STA bit of
the A/D Converter Control Register is set.
D11-D10. Reserved, must be cleared.
NMI PULL. NMI Pull-Up. This bit must be set high
to configure the NMI pin with a pull-up resistor.
When it is low, no pull-up is provided.
the oscillator must be controlled by a quartz crystal, a ceramic resonator or an external frequency.
When it is high, the oscillator must be controlled by
an RC network, with only the resistor having to be
externally provided.
OSGEN. Oscillator Safe Guard. This bit must be
set high to enable the Oscillator Safe Guard.
When this bit is low, the OSG is disabled.
The Option byte is written during programming either by using the PC menu (PC driven Mode) or
automatically (stand-alone mode).
12/84
PROGRAMMING MODES (Cont’d)
1.4.2 EPROM Erasing
The EPROM of the windowed package of the
MCUs may be erased by exposure to Ultra Violet
light. The erasure characteristic of the MCUs is
such that erasure begins when the memory is exposed to light with a wave lengths shorter than approximately 4000Å. It should be noted that sunlight
and some types of fluorescent lamps have wavelengths in the range 3000-4000Å.
It is thus recommended that the window of the
MCUs packages be covered by an opaque label to
ST6255C ST6265C ST6265B
prevent unintentional erasure problems when testing the application in such an environment.
The recommended erasure procedure of the
MCUs EPROM is the exposure to short wave ultraviolet light which have a wave-length 2537A.
The integrated dose (i.e. U.V. intensity x exposure
time) for erasure should be a minimum of 15Wsec/cm
proximately 15 to 20 minutes using an ultraviolet
lamp with 12000µW/cm
ST62E65C should be placed within 2.5cm (1Inch)
of the lamp tubes during erasure.
2
. The erasure time with this dosage is ap-
2
power rating. The
13/84
ST6255C ST6265C ST6265B
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communicating with on-chip I/O, Memory and Peripherals via internal address, data, and control
buses. In-core communication is arranged as
2.2 CPU REGISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragraphs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator can be addressed in Data
space as a RAM location at address FFh. Thus the
ST6 can manipulate the accumulator just like any
other register in Data space.
Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in
Data space. They are used in the register-indirect
addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction
shown in Figure 6; the controller being externally
linked to both the Reset and Oscillator circuits,
while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for
interrupt purposes, through the control registers.
set can use the indirect registers as any other register of the data space.
Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data
space as RAM locations at addresses 82h (V) and
83h (W). They can also be accessed using the direct and bit direct addressing modes. Thus, the
ST6 instruction set can use the short direct registers as any other register of the data space.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next ROM location to be processed by the core.
This ROM location may be an opcode, an operand, or the address of an operand. The 12-bit
length allows the direct addressing of 4096 bytes
in Program space.
14/84
Figure 6. ST6 Core Block Diagram
PROGRAM
RESET
OPCODE
FLAG
VALUES
2
CONTROLLER
FLAGS
ALU
A-DATA
B-DATA
ADDRESS/READ LINE
DATA SPACE
INTERRUPTS
DATA
RAM/EEPROM
DATA
ROM/EPROM
RESULTS TO DATA SPACE (WRITE LINE)
ROM/EPROM
DEDICATIONS
ACCUMULATOR
CONTROL
SIGNALS
OSCin
OSCout
ADDRESS
DECODER
256
12
Program Counter
and
6 LAYER STACK
0,01 TO 8MHz
VR01811
ST6255C ST6265C ST6265B
15/84
SHORT
DIRECT
ADDRESSING
MODE
V REGISTER
WREGISTER
PROGRAM COUNTER
SIX LEVELS
STACK REGISTER
CZNORMAL FLAGS
INTERRUPT FLAGS
NMI FLAGS
INDEX
REGISTER
VA000423
b7
b7
b7
b7
b7
b0
b0
b0
b0
b0
b0b11
ACCUMULATOR
YREG.POINTER
XREG.POINTER
CZ
CZ
ST6255C ST6265C ST6265B
CPU REGISTERS (Cont’d)
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
Bank Switch register.
The PC value is incremented after reading the address of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where they are added; the result is then
shifted back into the PC. The program counter can
be changed in the following ways:
- JP (Jump) instruction PC=Jump address
- CALL instruction PC= Call address
- Relative Branch Instruction.PC= PC +/- offset
- Interrupt PC=Interrupt vector
- Reset PC= Reset vector
- RET & RETI instructions PC= Pop (stack)
- Normal instruction PC= PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), each pair being associated
with one of the three normal modes of operation:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used during Interrupt mode (CI, ZI), and a third pair is used
in the Non Maskable Interrupt mode (CNMI, ZNMI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt flags (resp. the NMI flags)
instead of the Normal flags. When the RETI instruction is executed, the previously used set of
flags is restored. It should be noted that each flag
set can only be addressed in its own context (Non
Maskable Interrupt, Normal Interrupt or Main routine). The flags are not cleared during context
switching and thus retain their status.
The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is
cleared. The Carry flag is also set to the value of
the bit tested in a bit test instruction; it also participates in the rotate left instruction.
The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.
Switching between the three sets of flags is performed automatically when an NMI, an interrupt or
a RETI instructions occurs. As the NMI mode is
automatically selected after the reset of the MCU,
the ST6 core uses at first the NMI flags.
Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack
pointer. The stack consists of six separate 12-bit
RAM locations that do not belong to the data
space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level are
shifted into the next higher level, while the content
of the PC is shifted into the first level (the original
contents of the sixth stack level are lost). When a
subroutine or interrupt return occurs (RET or RETI
instructions), the first level register is shifted back
into the PC and the value of each level is popped
back into the previous level. Since the accumulator, in common with all other data space registers,
is not stored in this stack, management of these
registers should be performed within the subroutine. The stack will remain in its “deepest” position
if more than 6 nested calls or interrupts are executed, and consequently the last return address will
be lost. It will also remain in its highest position if
the stack is empty and a RET or RETI is executed.
In this case the next instruction will be executed.
Figure 7. ST6 CPU Programming Mode
l
16/84
ST6255C ST6265C ST6265B
INTEGRATED CLOCK
CRYSTAL/RESONATOR option
OSG ENABLED option
OSC
in
OSC
out
C
L1n
C
L2
ST6xxx
CRYSTAL/RESONATOR CLOCK
CRYSTAL/RESONATOR option
OSC
in
OSC
out
ST6xxx
EXTERNAL CLOCK
CRYSTAL/RESONATOR option
NC
OSC
in
OSC
out
ST6xxx
NC
OSC
in
OSC
out
R
NET
ST6xxx
RC NETWORK
RC NETWORK option
NC
3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES
3.1 CLOCK SYSTEM
The MCU features a Main Oscillator which can be
driven by an external clock, or used in conjunction
with an AT-cut parallel resonant crystal or a suitable ceramic resonator, or with an external resistor
). In addition, a Low Frequency Auxiliary Os-
(R
NET
cillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the
benefits of a back-up clock system.
The Oscillator Safeguard (OSG) option filters
spikes from the oscillator lines, provides access to
the LFAO to provide a backup oscillator in the
event of main oscillator failure and also automatically limits the internal clock frequency (f
function of V
ation. These functions are illustrated in Figure 9,
, in order to guarantee correct oper-
DD
Figure 10, Figure 11 and Figure 12.
A programmable divider on F
is also provided in
INT
order to adjust the internal clock of the MCU to the
best power consumption and performance tradeoff.
Figure 8 illustrates various possible oscillator con-
figurations using an external crystal or ceramic resonator, an external clock input, an external resistor
NET
LFAO. C
an CL2 should have a capacitance in the
L1
), or the lowest cost solution using only the
(R
range 12 to 22 pF for an oscillator frequency in the
4-8 MHz range.
The internal MCU clock frequency (f
) is divided
INT
by 12 to drive the Timer, the A/D converter and the
Watchdog timer, and by 13 to drive the CPU core,
as may be seen in Figure 11.
With an 8MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.
A machine cycle is the smallest unit of time needed
to execute any operation (for instance, to increment
the Program Counter). An instruction may require
two, four, or five machine cycles for execution.
3.1.1 Main Oscillator
The oscillator configuration may be specified by selecting the appropriate option. When the CRYSTAL/
RESONATOR option is selected, it must be used with
a quartz crystal, a ceramic resonator or an external
signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor.
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register. The
Low Frequency Auxiliary Oscillator is automatically started.
INT
) as a
Figure 8. Oscillator Configurations
17/84
ST6255C ST6265C ST6265B
CLOCK SYSTEM (Cont’d)
Turning on the main oscillator is achieved by resetting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting
the main oscillator implies a delay comprising the
oscillator start up delay period plus the duration of
the software instruction at f
clock frequency.
LFAO
3.1.2 Low Frequency Auxiliary Oscillator (LFAO)
The Low Frequency Auxiliary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consumption in non timing critical routines.
Secondly, it offers a fully integrated system clock,
without any external components. Lastly, it acts as
a safety oscillator in case of main oscillator failure.
This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing
edge from the main oscillator, whatever the reason
(main oscillator defective, no clock circuitry provided, main oscillator switched off...).
User code, normal interrupts, WAIT and STOP instructions, are processed as normal, at the reduced f
frequency. The A/D converter accura-
LFAO
cy is decreased, since the internal frequency is below 1MHz.
At power on, the Low Frequency Auxiliary Oscillator starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR
delay until the Main Oscillator runs.
The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.
ADCR
Address: 0D1h — Read/Write
70
ADCR7ADCR6ADCR5ADCR4ADCR3OSC
OFF
ADCR1ADCR
0
Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0:
ADC Control Register. These bits are reserved for
ADC Control.
Bit 2 = OSCOFF. When low, this bit enables main
oscillator to run. The main oscillator is switched off
when OSCOFF is high.
3.1.3 Oscillator Safe Guard
The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-
tions: it filters spikes from the oscillator lines which
would result in over frequency to the ST62 CPU; it
gives access to the Low Frequency Auxiliary Oscillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically
limits the internal clock frequency as a function of
supply voltage, in order to ensure correct operation even if the power supply should drop.
The OSG is enabled or disabled by choosing the
relevant OSG option. It may be viewed as a filter
whose cross-over frequency is device dependent.
Spikes on the oscillator lines result in an effectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over frequency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
9). In all cases, when the OSG is active, the maxi-
mum internal clock frequency, f
, which is supply voltage dependent. This re-
f
OSG
lationship is illustrated in Figure 12.
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator may be accessed. This oscillator starts operating after the first missing edge of
the main oscillator (see Figure 10).
Over-frequency, at a given power supply level, is
seen by the OSG as spikes; it therefore filters out
some cycles in order that the internal clock frequency of the device is kept within the range the
particular device can stand (depending on V
and below f
: the maximum authorised frequen-
OSG
cy with OSG enabled.
Note. The OSG should be used wherever possible
as it provides maximum safety. Care must be taken, however, as it can increase power consumption and reduce the maximum operating frequency
OSG
.
to f
Warning: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and is not accurate.
For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.
It should also be noted that power consumption in
Stop mode is higher when the OSG is enabled
(around 50µA at nominal conditions and room
temperature).
, is limited to
INT
DD
),
18/84
CLOCK SYSTEM (Cont’d)
(1)
VR001932
(3)
(2)
(4)
(1)
(2)
(3)
(4)
Maximum Frequency for the device to work correctly
Actual Quartz Crystal Frequency at OSCin pin
Noise from OSCin
Resulting Internal Frequency
Main
VR001933
Internal
Emergency
Oscillator
Frequency
Oscillator
Figure 9. OSG Filtering Principle
ST6255C ST6265C ST6265B
Figure 10. OSG Emergency Oscillator Principle
19/84
ST6255C ST6265C ST6265B
CLOCK SYSTEM (Cont’d)
Oscillator Control Registers
Address: DCh — Write only
Reset State: 00h
70
----
OSCR
3
-RS1RS0
Bit 7-4. These bits are not used.
Bit 3. Reserved. Cleared at Reset. Must be kept
cleared.
Bit 2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of
the Oscillator Divider in order to generate the internal frequency. The following selctions are available:
RS1 RS0 Division Ratio
0
0
1
1
0
1
0
1
Note: Care is required when handling the OSCR
register as some bits are write only. For this reason, it is not allowed to change the OSCR contents
while executing interrupt service routine, as the
service routine cannot save and then restore its
previous content. If it is impossible to avoid the
writing of this register in interrupt service routine,
an image of this register must be saved in a RAM
location, and each time the program writes to
OSCR it must write also to the image register. The
image register must be written first, so if an interrupt occurs between the two instructions the
OSCR is not affected.
1
2
4
4
20/84
CLOCK SYSTEM (Cont’d)
MAIN
OSCILLATOR
OSG
LFAO
M
U
X
Core
: 13
: 12
: 1
TIMER 1
Watchdog
POR
f
INT
Main Oscillator off
OSCILLATOR
DIVIDER
RS0,RS1
1
2.5
3.644.555.56
8
7
6
5
4
3
2
Maximum FREQUENCY (MHz)
SUPPLY VOLTAGE (V
DD
)
FUNCTIONALITY IS NOT
3
4
3
2
1
f
OSG
f
OSG
Min (at 85°C)
GUARANTEED
IN THIS AREA
VR01807J
f
OSG
Min (at 125°C)
Figure 11. Clock Circuit Block Diagram
ST6255C ST6265C ST6265B
Figure 12. Maximum Operating Frequency (f
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guaranteed at a frequency of at least f
3. When the OSG is disabled, operation in this
OSG Min.
) versus Supply Voltage (VDD)
MAX
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a f
OSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at f
OSG.
21/84
ST6255C ST6265C ST6265B
INT LATCH CLEARED
NMI MASK SET
RESET
( IF PRESENT )
SELECT
NMI MODE FLAGS
IS RESET STILL
PRESENT?
YES
PUT FFEH
ON ADDRESS BUS
FROM RESET LOCATIONS
FFE/FFF
NO
FETCH INSTRUCTION
LOAD PC
VA000427
3.1.4 RESETS
The MCU can be reset in four ways:
– by the external Reset input being pulled low;
– by Power-on Reset;
– by the digital Watchdog peripheral timing out.
– by Low Voltage Detection (LVD)
3.1.5 RESET Input
The RESET
pin may be connected to a device of
the application board in order to reset the MCU if
required. The RESET
pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the MCU internal state and ensure a
correct start-up procedure. The pin is active low
and features a Schmitt trigger input. The internal
Reset signal is generated by adding a delay to the
external signal. Therefore even short pulses on
the RESET
pin are acceptable, provided VDD has
completed its rising phase and that the oscillator is
running correctly (normal RUN or WAIT modes).
The MCU is kept in the Reset state as long as the
RESET
If RESET
pin is held low.
activation occurs in the RUN or WAIT
modes, processing of the user program is stopped
(RUN mode only), the Inputs and Outputs are configured as inputs with pull-up resistors and the
main Oscillator is restarted. When the level on the
RESET pin then goes high, the initialization sequence is executed following expiry of the internal
delay period.
If RESET
pin activation occurs in the STOP mode,
the oscillator starts up and all Inputs and Outputs
are configured as inputs with pull-up resistors.
When the level of the RESET
pin then goes high,
the initialization sequence is executed following
expiry of the internal delay period.
3.1.6 Power-on Reset
The function of the POR circuit consists in waking
up the MCU by detecting around 2V a dynamic
(rising edge) variation of the VDD Supply. At the
beginning of this sequence, the MCU is configured
in the Reset state: all I/O ports are configured as
inputs with pull-up resistors and no instruction is
executed. When the power supply voltage rises to
a sufficient level, the oscillator starts to operate,
whereupon an internal delay is initiated, in order to
allow the oscillator to fully stabilize before executing the first instruction. The initialization sequence
is executed immediately following the internal delay.
To ensure correct start-up, the user should take
care that the VDD Supply is stabilized at a sufficient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from
0V.
As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy
(presenting oscillation) VDD supplies.
An external RC network connected to the RESET
pin, or the LVD reset can be used instead to get
the best performances.
Figure 13. Reset and Interrupt Processing
22/84
RESETS (Cont’d)
RESET
RESET
VR02106A
time
V
Up
V
dn
V
DD
3.1.7 Watchdog Reset
The MCU provides a Watchdog timer function in
order to ensure graceful recovery from software
upsets. If the Watchdog register is not refreshed
before an end-of-count condition is reached, the
internal reset will be activated. This, amongst other things, resets the watchdog counter.
ues, allowing hysteresis effect. Reference value in
case of voltage drop has been set lower than the
reference value for power-on in order to avoid any
parasitic Reset when MCU start's running and
sinking current on the supply.
As long as the supply voltage is below the reference value, there is a internal and static RESET
command. The MCU can start only when the sup-
The MCU restarts just as though the Reset had
been generated by the RESET
pin, including the
built-in stabilisation delay period.
3.1.8 LVD Reset
The on-chip Low Voltage Detector, selectable as
user option, features static Reset when supply
voltage is below a reference value. Thanks to this
feature, external reset circuit can be removed
while keeping the application safety. This SAFE
RESET is effective as well in Power-on phase as
ply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU:
RESET active below the voltage reference, and
running mode over the voltage reference as
shown on the Figure 14, that represents a powerup, power-down sequence.
Note: When the RESET state is controlled by one
of the internal RESET sources (Low Voltage Detector, Watchdog, Power on Reset), the RESET
pin is tied to low logic level.
in power supply drop with different reference val-
Figure 14. LVD Reset on Power-on and Power-down (Brown-out)
ST6255C ST6265C ST6265B
3.1.9 Application Notes
No external resistor is required between V
the Reset pin, thanks to the built-in pull-up device.
DD
and
Direct external connection of the pin RESET
must be avoided in order to ensure safe be-
V
DD
haviour of the internal reset sources (AND.Wired
structure).
to
23/84
ST6255C ST6265C ST6265B
RESET
RESET
VECTOR
JP
JP:2 BYTES/4 CYCLES
RETI
RETI: 1 BYTE/2 CYCLES
INITIALIZATION
ROUTINE
VA00181
V
DD
RESET
R
PU
R
ESD
1)
POWER
WATCHDOG RESET
CK
COUNTER
RESET
ST6
INTERNAL
RESET
f
OSC
RESET
ON RESET
LVD RESET
VR02107A
AND. Wired
1) Resistive ESD protection. Value not guaranteed.
RESETS (Cont’d)
3.1.10 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (located in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the Interrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The initialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, however, a pending interrupt is present, it will be serviced.
Figure 16. Reset Block Diagram
Figure 15. Reset and Interrupt Processing
24/84
RESETS (Cont’d)
Table 5. Register Reset Status
Register Address(es) Status Comment
Oscillator Control Register
EEPROM Control Register
Port Data Registers
Port Direction Register
Port Option Register
Interrupt Option Register
TIMER Status/Control
0DCh
0EAh
0C0h to 0C2h
0C4h to 0C6h
0CCh to 0CEh
0C8h
0D4h
00h
00h
00h
00h
00h
00h
00h
ST6255C ST6265C ST6265B
EEPROM disabled (if available)
I/O are Input with pull-up
I/O are Input with pull-up
I/O are Input with pull-up
Interrupt disabled
TIMER disabled
AR TIMER Mode Control Register
AR TIMER Status/Control 0 Register
AR TIMER Status/Control 1 Register
AR TIMER Compare Register
AR TIMER Load Register
Miscellaneous Register
SPI Registers
SPI DIV Register
SPI MOD Register
SPI DSR Register
X, Y, V, W, Register
Accumulator
Data RAM
Data RAM EEPROM Page Register
Data ROM Window Register
EEPROM
A/D Result Register
AR TIMER Load Register
AR TIMER Reload/Capture Register
TIMER Counter Register
TIMER Prescaler Register
Watchdog Counter Register
A/D Control Register
0D5h
0D6h
0D7h
0DAh
0DBh
0DDh
0E0h to 0E2h
0E1h
0E2h
0E0h
080H TO 083H
0FFh
084h to 0BFh
0E8h
0C9h
00h to 03Fh
0D0h
0DBh
0D9h
0D3h
0D2h
0D8h
0D1h
00h
02h
00h
00h
00h
00h
00h
00h
00h
Undefined
Undefined
FFh
7Fh
FEh
40h
AR TIMER stopped
SPI Output not connected to PC3
SPI disabled
SPI disabled
SPI disabled
SPI disabled
As written if programmed
Max count loaded
A/D in Standby
25/84
ST6255C ST6265C ST6265B
3.2 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Reset when the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. In the event of a software mishap (usually caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be reloaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In order to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by two options,
known as “WATCHDOG ACTIVATION” (i.e.
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 6).
In the SOFTWARE option, the Watchdog is disabled until bit C of the DWDR register has been set.
Table 6. Recommended Option Choices
Functions Required Recommended Options
Stop Mode & Watchdog “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
Stop Mode “SOFTWARE WATCHDOG”
Watchdog “HARDWARE WATCHDOG”
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is permanently enabled. Since the oscillator will run continuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruction, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then governed by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP instruction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU enters STOP mode.
When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its
activity.
26/84
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