ST ST6252C, ST6262B, ST6262C User Manual

safe reset, auto-reload timer and EEPROM

(See end of Datasheet for Ordering Information)

PDIP16

PSO16

CDIP16W

SSOP16

Features

■ 3.0 to 6.0 V supply operating range

■ 8 MHz maximum clock frequency

■ -40 to +125°C operating temperature range

■ Run, Wait and Stop Modes

■ 5 Interrupt vectors

■ Look-up table capability in Program Memory

■ Data storage in Program Memory:

User selectable size

■ Data RAM: 128 bytes

■ Data EEPROM: 64 bytes (not in ST6252C devices)

■ User programmable options

■ 9 I/O pins, fully programmable as:

– Input with pull-up resistor – Input without pull-up resistor – Input with interrupt generation – Open-drain or push-pull output – Analog Input

■ 5 I/O lines can sink up to 30 mA to drive LEDs or

TRIACs directly

■ 8-bit Timer / Counter with 7-bit programmable

prescaler

■ 8-bit Auto-reload Timer with 7-bit programmable

prescaler (AR Timer)

■ Digital watchdog

■ Oscillator Safe Guard (not in ST6262B devices)

■ Low Voltage Detector for safe Reset (not in

ST6262B devices)

■ 8-bit A/D converter with 4 analog inputs

■ On-chip Clock oscillator can be driven by quartz

crystal ceramic resonator or RC network

■ User configurable Power-on Reset

■ One external Non-Maskable Interrupt

■ ST626x-EMU2 emulation and development

system (connects to an MS-DOS PC via a parallel port)

ST6252C ST6262B

ST6262C

8-bit MCUs with A/D converter,

Table 1. Device summary

DEVICE

ST6252C 1836 -

ST6262C 1836 64

ST6262B 1836 64

Program memory

(Bytes)

EEPROM

(Bytes)

March 2009 Rev. 4 1/75

Table of Contents

Document

Page

ST6252C ST6262B

ST6262C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 16

3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.3 RESETS (CONT’D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.4 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.3 AUTO-RELOAD TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.4 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.5 A/D CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.6 TIMER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.7 SPI CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.8 ARTIMER ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.1 OTP/EPROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.2 FASTROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8.3 ROM VERSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

9 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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1 GENERAL DESCRIPTION

TEST

NMI

INTERRUPT

PROGRAM

STACK LEVEL 1

STACK LEVEL 2 STACK LEVEL 3

STACK LEVEL 4 STACK LEVEL 5

STACK LEVEL 6

POWER SUPPLY

OSCILLATOR

RESET

DATA ROM

USER

SELECTABLE

DATA RAM

PORT A

PORT B

TIMER

DIGITAL

8 BIT CORE

TEST/V

8-BIT

A/D CONVERTER

PA4..PA5 / Ain

PB0, PB2..PB3 / 30 mA Sink

VDDV

OSCin OSCout RESET

WATCHDOG

MEMORY

PB6 / ARTimin / 20 mA Sink

PORT C

PC2..PC3 / Ain

AUTORELOAD

TIMER

PB7 / ARTimout / 20 mA Sink

128 Bytes

1836 bytes OTP

(ST62T52C, T62C)

1836 bytes EPROM

(ST62E62C)

DATA EEPROM

64 Bytes

(ST62T62C/E62C)

1.1 INTRODUCTION

The ST6252C and ST6262C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip periph erals.

The ST62E62C is the erasable EPROM version of the ST62T62C device, which may be used to em ulate the ST62T52C and ST62T62C devices as well as the ST6252C and ST6262B ROM devices.

OTP and EPROM devices are functionally identical. The ROM based versions offer the same functionality selecting as ROM options the options de-

Figure 1. Block Diagram

ST6252C ST6262B ST6262C

fined in the programmable option byte of the OTP/EPROM versions.

OTP devices offer all the advantages of user programmability at low cost, which make them the

ideal choice in a wide range of applications where frequent code changes, multiple code versions or last minute programmability are required.

These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit program mable prescaler, an 8-bit Auto-Reload Timer, EEPROM data capability (except ST6252C), an 8bit A/D Converter with 4 analog inputs and a Digit al Watchdog timer, making them well suited for a wide range of automotive, appliance and industrial applications.

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ST6252C ST6262B ST6262C

PB0

/TEST

PB2

PB3

ARTIMin/PB6

PC2/Ain

PC3/Ain

PA5/Ain

PA4/Ain

ARTIMout/PB7

NMI

RESET

OSCout

OSCin

1.2 PIN DESCRIPTIONS

VDD and VSS. Power is supplied to the MCU via

these two pins. VDD is the power connection and V

is the ground connection.

OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins. The OSCin pin is the input pin, the OSCout pin is the output pin.

RESET. The active-low RESET pin is used to restart the microcontroller.

TEST/VPP. The TEST must be held at VSS for nor- mal operation. If TEST pin is connected to a +12.5V level during the reset phase, the EPROM/OTP programming Mode is entered.

NMI. The NMI pin provides the capability for asynchronous interruption, by applying an external non maskable interrupt to the MCU. The NMI input is falling edge sensitive. It is provided with an on-chip pullup resistor (if option has been enabled), and Schmitt trigger characteristics.

PA4-PA5. These 2 lines are organized as one I/O port (A). Each line may be configured under soft ware control as inputs with or without internal pullup resistors, interrupt generating inputs with pullup resistors, open-drain or push-pull outputs, ana log inputs for the A/D converter.

PB0, PB2-PB3, PB6-PB7. These 5 lines are organized as one I/O port (B). Each line may be configured under software control as inputs with or without internal pull-up resistors, interrupt generating inputs with pull-up resistors, open-drain or push-pull outputs. PB6/ARTIMin and PB7/ARTI-

Mout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3 pins can be defined by option either with pull-up or high impedance.

PB0, PB2-PB3, PB6-PB7 scan also sink 30mA for direct LED driving.

PC2-PC3. These 2 lines are organized as one I/O port (C). Each line may be configured under soft ware control as input with or without internal pullup resistor, interrupt generating input with pull-up resistor, analog input for the A/D converter, opendrain or push-pull output.

Figure 2. ST62T52C, E62C and T62C Pin Configuration

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1.3 MEMORY MAP

PROGRAM SPACE

PROGRAM

INTERRUPT &

RESET VECTORS

ACCUMULATOR

DATA RAM

BANK SELECT

WINDOW SELECT

RAM

X REGISTER Y REGISTER V REGISTER

W REGISTER

DATA READ-ONLY

WINDOW

RAM / EEPROM BANKING AREA

000h

03Fh 040h

07Fh 080h 081h 082h 083h 084h

0C0h

0FFh

0-63

DATA SPACE

0000h

0FF0h

0FFFh

MEMORY

DATA READ-ONLY

MEMORY

1.3.1 Introduction

The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs.

Figure 3. Memory Addressing Diagram

ST6252C ST6262B ST6262C

Briefly, Program space contains user program code in OTP and user vectors; Data space contains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub routine and interrupt service routine nesting.

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ST6252C ST6262B ST6262C

0000h

RESERVED

USER

PROGRAM MEMORY

(OTP/EPROM)

1836 BYTES

0F9Fh 0FA0h 0FEFh 0FF0h 0FF7h 0FF8h

0FFBh 0FFCh 0FFDh

0FFEh

0FFFh

RESERVED

INTERRUPT VECTORS

NMI VECTOR

USER RESET VECTOR

(*) Reserved areas should be filled with 0FFh

0880h

087Fh

MEMORY MAP (Cont’d)

1.3.2 Program Space

Program Space comprises the instructions to be executed, the data required for immediate addressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register).

1.3.2.1 Program Memory Protection

The Program Memory in OTP or EPROM devices can be protected against external readout of memory by selecting the READOUT PROTECTION option in the option byte.

In the EPROM parts, READOUT PROTECTION option can be disactivated only by U.V. erasure that also results into the whole EPROM context erasure.

Note: Once the Readout Protection is activated, it is no longer possible, even for STMicroelectronics, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac cepted.

Figure 4. ST62T52C/T62C Program

Memory Map

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MEMORY MAP (Cont’d)

1.3.3 Data Space

Data Space accommodates all the data necessary for processing the user program. This space comprises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in OTP/EPROM.

1.3.3.1 Data ROM

All read-only data is physically stored in program memory, which also accommodates the Program Space. The program memory consequently con tains the program code to be executed, as well as the constants and look-up tables required by the

application.

The Data Space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in OTP/EPROM.

1.3.3.2 Data RAM/EEPROM

In ST62T52C, T62C and ST62E62C devices, the data space includes 60 bytes of RAM, the accu mulator (A), the indirect registers (X), (Y), the short direct registers (V), (W), the I/O port registers, the peripheral data and control registers, the interrupt option register and the Data ROM Window register

(DRW register). Additional RAM and EEPROM pages can also be

addressed using banks of 64 bytes located between addresses 00h and 3Fh.

1.3.4 Stack Space

Stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents.

Table 1. Additional RAM / EEPROM Banks

Device RAM EEPROM

ST62T52C 1 x 64 bytes ST62T62C 1 x 64 bytes 1 x 64 bytes

ST6252C ST6262B ST6262C

Table 2. ST62T52C, T62C and ST62E62C Data

* WRITE ONLY REGISTER

Memory Space

RAM / EEPROM banks

DATA ROM WINDOW AREA

X REGISTER 080h Y REGISTER 081h V REGISTER 082h

W REGISTER 083h

DATA RAM 60 BYTES

PORT A DATA REGISTER 0C0h PORT B DATA REGISTER 0C1h PORT C DATA REGISTER 0C2h

RESERVED 0C3h PORT A DIRECTION REGISTER 0C4h PORT B DIRECTION REGISTER 0C5h PORT C DIRECTION REGISTER 0C6h

RESERVED 0C7h

INTERRUPT OPTION REGISTER 0C8h* DATA ROM WINDOW REGISTER 0C9h*

RESERVED

PORT A OPTION REGISTER 0CCh PORT B OPTION REGISTER 0CDh PORT C OPTION REGISTER 0CEh

RESERVED 0CFh

A/D DATA REGISTER 0D0h

A/D CONTROL REGISTER 0D1h

TIMER PRESCALER REGISTER 0D2h

TIMER COUNTER REGISTER 0D3h

TIMER STATUS CONTROL REGISTER 0D4h

AR TIMER MODE CONTROL REGISTER 0D5h AR TIMER STATUS/CONTROL REGISTER1 0D6h AR TIMER STATUS/CONTROL REGISTER2 0D7h

WATCHDOG REGISTER 0D8h

AR TIMER RELOAD/CAPTURE REGISTER 0D9h

AR TIMER COMPARE REGISTER 0DAh

AR TIMER LOAD REGISTER 0DBh

RESERVED

DATA RAM/EEPROM REGISTER 0E8h*

RESERVED 0E9h

EEPROM CONTROL REGISTER 0EAh

RESERVED

ACCUMULATOR 0FFh

000h

03Fh 040h

07Fh

084h 0BFh

0CAh 0CBh

0DCh 0DDh 0DEh 0E7h

0EBh 0FEh

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ST6252C ST6262B ST6262C

DATA ROM

WINDOW REGISTER

CONTENTS

DATA SPACE ADDRESS

40h-7Fh

IN INSTRUCTION

PROGRAM SPACE ADDRESS

765432 0

543210

READ

67891011

VR01573C

DATA SPACE ADDRESS

59h

000

Example:

(DWR)

DWR=28h

0000000

ROM

ADDRESS:A19h

MEMORY MAP (Cont’d)

1.3.5 Data Window Register (DWR)

The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat ed anywhere in program memory, between address 0000h and 0FFFh (top memory address depends on the specific device). All the program memory can therefore be used to store either instructions or read-only data. Indeed, the window can be moved in steps of 64 bytes along the pro gram memory by writing the appropriate code in the Data Window Register (DWR).

The DWR can be addressed like any RAM location in the Data Space, it is however a write-only register and therefore cannot be accessed using singlebit operations. This register is used to position the 64-byte read-only data window (from address 40h to address 7Fh of the Data space) in program memory in 64-byte steps. The effective address of the byte to be read as data in program memory is obtained by concatenating the 6 least significant bits of the register address given in the instruction (as least significant bits) and the content of the DWR register (as most significant bits), as illustrat ed in Figure 5 below. For instance, when addressing location 0040h of the Data Space, with 0 loaded in the DWR register, the physical location addressed in program memory is 00h. The DWR register is not cleared on reset, therefore it must be written to prior to the first access to the Data readonly memory window area.

Figure 5. Data read-only memory Window Memory Addressing

Data Window Register (DWR)

Address: 0C9h — Write Only

7 0

- - DWR5 DWR4 DWR3 DWR2 DWR1 DWR0

Bits 6, 7 = Not used.

Bit 5-0 = DWR5-DWR0: Data read-only memory Window Register Bits. These are the Data read- only memory Window bits that correspond to the upper bits of the data read-only memory space.

Caution: This register is undefined on reset. Neither read nor single bit instructions may be used to address this register.

Note: Care is required when handling the DWR register as it is write only. For this reason, the DWR contents should not be changed while exe cuting an interrupt service routine, as the service routine cannot save and then restore the register’s previous contents. If it is impossible to avoid writ

ing to the DWR during the interrupt service routine,

an image of the register must be saved in a RAM location, and each time the program writes to the DWR, it must also write to the image register. The image register must be written first so that, if an in terrupt occurs between the two instructions, the DWR is not affected.

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MEMORY MAP (Cont’d)

1.3.6 Data RAM/EEPROM Bank Register (DRBR)

Address: E8h — Write only

7 0

- - -

DRBR

- - -

DRBR

Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM

Page 2. Bit 3-1. Not used Bit 0. DRBR0. This bit, when set, selects EEP-

ROM page 0. The selection of the bank is made by programming

the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should be set at a time.

The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to select the desired 64-byte RAM bank of the Data Space. The bank number has to be loaded in the DRBR register and the instruction has to point to the se lected location as if it was in bank 0 (from 00h address to 3Fh address).

This register is not cleared during the MCU initialization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa-

ST6252C ST6262B ST6262C

tion. The DRBR register is not modified when an interrupt or a subroutine occurs.

Notes : Care is required when handling the DRBR register

as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in terrupt service routine, as the service routine cannot save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected.

In DRBR Register, only 1 bit must be set. Otherwise two or more pages are enabled in parallel, producing errors.

Care must also be taken not to change the E²PROM page (when available) when the parallel writing mode is set for the E²PROM, as defined in EECTL register.

Table 3. Data RAM Bank Register Set-up

DRBR ST62T52C ST62T62C

00 None None 01 Not available EEPROM page 0 02 Not Available Not Available 08 Not available Not available

10h RAM Page 2 RAM Page 2

other Reserved Reserved

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ST6252C ST6262B ST6262C

MEMORY MAP (Cont’d)

1.3.7 EEPROM Description

EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage.

Data space from 00h to 3Fh is paged as described

Table 4 . EEPROM locations are accessed di-

in rectly by addressing these paged sections of data space.

The EEPROM does not require dedicated instructions for read or write access. Once selected via the Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Regis ter (EECTL), which is described below.

Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any ac cess is meaningless.

Programming must be enabled by setting the E2ENA bit of the EECTL register.

The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless.

Provided E2OFF and E2BUSY are reset, an EEPROM location is read just like any other data location, also in terms of access time.

Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode

Table 4. Row Arrangement for Parallel Writing of EEPROM Locations

Byte 0 1 2 3 4 5 6 7 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h

(PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with conse quent speed and power consumption advantages, the latter being particularly important in battery powered circuits).

General Notes: Data should be written directly to the intended ad-

dress in EEPROM space. There is no buffer memory between data RAM and the EEPROM space.

When the EEPROM is busy (E2BUSY = “1”)

EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved

and must never be set.

Care is required when dealing with the EECTL register, as some bits are write only. For this reason, the EECTL contents must not be altered while ex ecuting an interrupt service routine.

If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt oc curs between the two instructions, the EECTL will not be affected.

Dataspace

addresses.

Banks 0 and 1.

Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode.

The number of available 64-byte banks (1 or 2) is device dependent.

Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest power-consumption.

10/75

MEMORY MAP (Cont’d) Additional Notes on Parallel Mode:

If the user wishes to perform parallel programming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad dressed in write mode, the ROW address and the data will be latched and it will be possible to change them only at the end of the programming cycle or by resetting E2PAR2 without program ming the EEPROM. After the ROW address is latched, the MCU can only “see” the selected EEPROM row and any attempt to write or read other rows will produce errors.

The EEPROM should not be read while E2PAR2 is set.

As soon as the E2PAR2 bit is set, the 8 volatile ROW latches are cleared. From this moment on, the user can load data in all or in part of the ROW. Setting E2PAR1 will modify the EEPROM regis ters corresponding to the ROW latches accessed after E2PAR2. For example, if the software sets E2PAR2 and accesses the EEPROM by writing to addresses 18h, 1Ah and 1Bh, and then sets E2PAR1, these three registers will be modified si multaneously; the remaining bytes in the row will be unaffected.

Note that E2PAR2 is internally reset at the end of the programming cycle. This implies that the user must set the E2PAR2 bit between two parallel pro gramming cycles. Note that if the user tries to set E2PAR1 while E2PAR2 is not set, there will be no programming cycle and the E2PAR1 bit will be un affected. Consequently, the E2PAR1 bit cannot be set if E2ENA is low. The E2PAR1 bit can be set by the user, only if the E2ENA and E2PAR2 bits are also set.

Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set.

ST6252C ST6262B ST6262C

EEPROM Control Register (EECTL)

Address: EAh — Read/Write Reset status: 00h

7 0

E2O

D5 D4

Bit 7 = D7: Unused. Bit 6 = E2OFF: Stand-by Enable Bit. WRITE ONLY.

If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to its lowest value.

Bit 5-4 = D5-D4: Reserved. MUST be kept reset. Bit 3 = E2PAR1: Parallel Start Bit. WRITE ONLY.

Once in Parallel Mode, as soon as the user software

sets the E2PAR1 bit, parallel writing of the 8 adja cent registers will start. This bit is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written if required, the un defined bytes being unaffected by the parallel pro-

gramming cycle; this is explained in greater detail in the Additional Notes on Parallel Mode overleaf.

Bit 2 = E2PAR2: Parallel Mode En. Bit. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming. If E2PAR2

is set and the parallel start bit (E2PAR1) is reset, up to 8 adjacent bytes can be written simultane ously. These 8 adjacent bytes are considered as a

row, whose address lines A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bits, as illustrated in

Table 4. E2PAR2 is automatically re-

set at the end of any parallel programming procedure. It can be reset by the user software before starting the programming procedure, thus leaving the EEPROM registers unchanged.

Bit 1 = E2BUSY: EEPROM Busy Bit. READ ON- LY. This bit is automatically set by the EEPROM control logic when the EEPROM is in program ming mode. The user program should test it before any EEPROM read or write operation; any attempt to access the EEPROM while the busy bit is set will be aborted and the writing procedure in progress will be completed.

Bit 0 = E2ENA: EEPROM Enable Bit. WRITE ON- LY. This bit enables programming of the EEPROM cells. It must be set before any write to the EEP ROM register. Any attempt to write to the EEPROM when E2ENA is low is meaningless and will not trigger a write cycle.

E2PAR1E2PAR2E2BUSYE2E

11/75

ST6252C ST6262B ST6262C

1.4 PROGRAMMING MODES

1.4.1 Option Bytes

The two Option Bytes allow configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated.

It can only be accessed during the programming mode. This access is made either automatically (copy from a master device) or by selecting the OPTION BYTE PROGRAMMING mode of the pro grammer.

The option bytes are located in a non-user map. No address has to be specified.

EPROM Code Option Byte (LSB)

7 0

PRO-

EXTC-

PB2-3

- WDACT

NTL

PULL

TECT

EPROM Code Option Byte (MSB)

15 8

- - -

ADC

SYNCHRO

D15-D13. Reserved. Must be cleared. ADC SYNCHRO. When set, an A/D conversion is

started upon WAIT instruction execution, in order to reduce supply noise. When this bit is low, an A/D conversion is started as soon as the STA bit of the A/D Converter Control Register is set.

D11. Reserved, must be cleared. D10. Reserved, must be set to one. NMI PULL. NMI Pull-Up. This bit must be set high

to configure the NMI pin with a pull-up resistor. When it is low, no pull-up is provided.

LVD. LVD RESET enable.When this bit is set, safe RESET is performed by MCU when the supply voltage is too low. When this bit is cleared, only power-on reset or external RESET are active.

PROTECT. Readout Protection. This bit allows the protection of the software contents against piracy. When the bit PROTECT is set high, readout of the OTP contents is prevented by hardware.. When this bit is low, the user program can be read.

EXTCNTL. External STOP MODE control.. When EXTCNTL is high, STOP mode is available with watchdog active by setting NMI pin to one. When

- -

DELAY

OSCIL OSGEN

NMI

LVD

PULL

EXTCNTL is low, STOP mode is not available with the watchdog active.

PB2-3 PULL. When set this bit removes pull-up at reset on PB2-PB3 pins. When cleared PB2-PB3 pins have an internal pull-up resistor at reset.

D4. Reserved. Must be cleared to 0. WDACT. This bit controls the watchdog activation.

When it is high, hardware activation is selected.

The software activation is selected when WDACT

is low. DELAY. This bit enables the selection of the delay

internally generated after the internal reset (exter nal pin, LVD, or watchdog activated) is released. When DELAY is low, the delay is 2048 cycles of the oscillator, it is of 32768 cycles when DELAY is high.

OSCIL. Oscillator selection. When this bit is low, the oscillator must be controlled by a quartz crys tal, a ceramic resonator or an external frequency. When it is high, the oscillator must be controlled by an RC network, with only the resistor having to be externally provided.

OSGEN. Oscillator Safe Guard. This bit must be set high to enable the Oscillator Safe Guard. When this bit is low, the OSG is disabled.

The Option byte is written during programming either by using the PC menu (PC driven Mode) or automatically (stand-alone mode).

1.4.2 Program Memory

EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/VPP pin. The programming flow of the ST62T62C is described in the User Manual of the EPROM Programming Board.

The MCUs can be programmed with the ST62E6xB EPROM programming tools available from STMicroelectronics.

Table 5. ST62T52C/T62C Program Memory Map

Device Address Description

0000h-087Fh

0880h-0F9Fh

0FA0h-0FEFh

0FF0h-0FF7h

0FF8h-0FFBh 0FFCh-0FFDh 0FFEh-0FFFh

Note: OTP/EPROM devices can be programmed with the development tools available from STMi-

Reserved

User ROM

Reserved

Interrupt Vectors

Reserved

NMI Interrupt Vector

Reset Vector

croelectronics (ST62E6X-EPB or ST626X-KIT).

12/75

PROGRAMMING MODES (Cont’d)

1.4.3 . EEPROM Data Memory

EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEPROM data memory can be performed either through the application software or through an ex-

ST6252C ST6262B ST6262C

ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem ory.

13/75

ST6252C ST6262B ST6262C

PROGRAM

RESET

OPCODE

FLAG

VALUES

CONTROLLER

FLAGS

ALU

A-DATA

B-DATA

ADDRESS/READ LINE

DATA SPACE

INTERRUPTS

DATA

RAM/EEPROM

DATA

ROM/EPROM

RESULTS TO DATA SPACE (WRITE LINE)

ROM/EPROM

DEDICATIONS

ACCUMULATOR

CONTROL SIGNALS

OSCin

OSCout

ADDRESS

DECODER

256

Program Counter

and

6 LAYER STACK

0,01 TO 8MHz

VR01811

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought of as an independent central processor communicating with on-chip I/O, Memory and Pe ripherals via internal address, data, and control buses. In-core communication is arranged as shown in linked to both the Reset and Oscillator circuits, while the core is linked to the dedicated on-chip peripherals via the serial data bus and indirectly, for

Figure 6; the controller being externally

interrupt purposes, through the control registers.

2.2 CPU REGISTERS

The ST6 Family CPU core features six registers and three pairs of flags available to the programmer. These are described in the following paragraphs.

Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic cal culations, logical operations, and data manipulations. The accumulator can be addressed in Data space as a RAM location at address FFh. Thus the ST6 can manipulate the accumulator just like any other register in Data space.

Figure 6ST6 Core Block Diagram

Indirect Registers (X, Y). These two indirect registers are used as pointers to memory locations in Data space. They are used in the register-indirect addressing mode. These registers can be addressed in the data space as RAM locations at addresses 80h (X) and 81h (Y). They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST6 instruction set can use the indirect registers as any other register of the data space.

Short Direct Registers (V, W). These two registers are used to save a byte in short direct addressing mode. They can be addressed in Data space as RAM locations at addresses 82h (V) and 83h (W). They can also be accessed using the di rect and bit direct addressing modes. Thus, the ST6 instruction set can use the short direct regis ters as any other register of the data space.

Program Counter (PC). The program counter is a 12-bit register which contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an oper and, or the address of an operand. The 12-bit length allows the direct addressing of 4096 bytes in Program space.

14/75

CPU REGISTERS (Cont’d)

SHORT

DIRECT

ADDRESSING

MODE

VREGISTER

WREGISTER

PROGRAM COUNTER

SIX LEVELS

STACK REGISTER

CZNORMAL FLAGS

INTERRUPT FLAGS

NMI FLAGS

INDEX

VA000423

b0b11

ACCUMULATOR

Y REG. POINTER

X REG. POINTER

However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register.

The PC value is incremented after reading the address of the current instruction. To execute relative jumps, the PC and the offset are shifted through the ALU, where they are added; the result is then shifted back into the PC. The program counter can be changed in the following ways:

- JP (Jump) instructionPC=Jump address

- CALL instructionPC= Call address

- Relative Branch Instruction.PC= PC +/- offset

- Interrupt PC=Interrupt vector

- ResetPC= Reset vector

- RET & RETI instructionsPC= Pop (stack)

- Normal instructionPC= PC + 1

Flags (C, Z). The ST6 CPU includes three pairs of flags (Carry and Zero), each pair being associated with one of the three normal modes of operation: Normal mode, Interrupt mode and Non Maskable Interrupt mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during Normal operation, another pair is used dur ing Interrupt mode (CI, ZI), and a third pair is used in the Non Maskable Interrupt mode (CNMI, ZNMI).

The ST6 CPU uses the pair of flags associated with the current mode: as soon as an interrupt (or a Non Maskable Interrupt) is generated, the ST6 CPU uses the Interrupt flags (resp. the NMI flags) instead of the Normal flags. When the RETI in struction is executed, the previously used set of flags is restored. It should be noted that each flag set can only be addressed in its own context (Non Maskable Interrupt, Normal Interrupt or Main rou tine). The flags are not cleared during context switching and thus retain their status.

The Carry flag is set when a carry or a borrow occurs during arithmetic operations; otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction; it also partici pates in the rotate left instruction.

The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared.

Switching between the three sets of flags is performed automatically when an NMI, an interrupt or

ST6252C ST6262B ST6262C

a RETI instructions occurs. As the NMI mode is automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags.

Stack. The ST6 CPU includes a true LIFO hardware stack which eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or inter rupt request) occurs, the contents of each level are shifted into the next higher level, while the content of the PC is shifted into the first level (the original contents of the sixth stack level are lost). When a subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is popped back into the previous level. Since the accumula tor, in common with all other data space registers, is not stored in this stack, management of these registers should be performed within the subroutine. The stack will remain in its “deepest” position if more than 6 nested calls or interrupts are executed, and consequently the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed.

Figure 7ST6 CPU Programming Mode

15/75

ST6252C ST6262B ST6262C

INTEGRATED CLOCK

CRYSTAL/RESONATOR option

OSG ENABLED option

OSC

out

L1n

ST6xxx

CRYSTAL/RESONATOR CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

EXTERNAL CLOCK

CRYSTAL/RESONATOR option

OSC

out

ST6xxx

OSC

out

NET

ST6xxx

RC NETWORK

RC NETWORK option

3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES

3.1 CLOCK SYSTEM

The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita ble ceramic resonator, or with an external resistor

). In addition, a Low Frequency Auxiliary Os-

NET

cillator (LFAO) can be switched in for security reasons, to reduce power consumption, or to offer the benefits of a back-up clock system.

The Oscillator Safeguard (OSG) option filters spikes from the oscillator lines, provides access to the LFAO to provide a backup oscillator in the event of main oscillator failure and also automati cally limits the internal clock frequency (f function of V ation. These functions are illustrated in Figure 9.,

Figure 10., Figure 11. and Figure 12..

, in order to guarantee correct oper-

INT

) as a

Figure 8. illustrates various possible oscillator con-

figurations using an external crystal or ceramic resonator, an external clock input, an external resistor

), or the lowest cost solution using only the

NET

LFAO. C range 12 tclkadcosgo 22 pF for an oscillator fre quency in the 4-8 MHz range.

The internal MCU clock frequency (f

an CL2 should have a capacitance in the

by 12 to drive the Timer, the A/D converter and the Watchdog timer, and by 13 to drive the CPU core, as may be seen in

With an 8 MHz oscillator frequency, the fastest machine cycle is therefore 1.625µs.

A machine cycle is the smallest unit of time needed to execute any operation (for instance, to increment

Figure 11..

) is divided

INT

the Program Counter). An instruction may require two, four, or five machine cycles for execution.

3.1.1 Main Oscillator

The oscillator configuration may be specified by selecting the appropriate option. When the CRYSTAL/RESONATOR option is selected, it must be used with a quartz crystal, a ceramic resonator or an external signal provided on the OSCin pin. When the RC NETWORK option is selected, the system clock is generated by an external resistor.

The main oscillator can be turned off (when the OSG ENABLED option is selected) by setting the OSCOFF bit of the ADC Control Register. The Low Frequency Auxiliary Oscillator is automatical ly started.

Figure 8. Oscillator Configurations

16/75

CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re-

setting the OSCOFF bit of the A/D Converter Control Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up delay period plus the duration of the software instruction at f

clock frequency.

LFAO

3.1.2 Low Frequency Auxiliary Oscillator (LFAO)

The Low Frequency Auxiliary Oscillator has three main purposes. Firstly, it can be used to reduce power consumption in non timing critical routines. Secondly, it offers a fully integrated system clock, without any external components. Lastly, it acts as a safety oscillator in case of main oscillator failure.

This oscillator is available when the OSG ENABLED option is selected. In this case, it automatically starts one of its periods after the first missing edge from the main oscillator, whatever the reason (main oscillator defective, no clock circuitry provid

ed, main oscillator switched off...). User code, normal interrupts, WAIT and STOP in-

structions, are processed as normal, at the reduced f cy is decreased, since the internal frequency is be-

frequency. The A/D converter accura-

LFAO

low 1MHz. At power on, the Low Frequency Auxiliary Oscilla-

tor starts faster than the Main Oscillator. It therefore feeds the on-chip counter generating the POR delay until the Main Oscillator runs.

The Low Frequency Auxiliary Oscillator is automatically switched off as soon as the main oscillator starts.

ADCR

Address: 0D1h — Read/Write

7 0

ADCR7ADCR6ADCR5ADCR4ADCR3OSC

OFF

ADCR1ADCR

Bit 7-3, 1-0= ADCR7-ADCR3, ADCR1-ADCR0: ADC Control Register. These bits are not used.

Bit 2 = OSCOFF. When low, this bit enables main oscillator to run. The main oscillator is switched off when OSCOFF is high.

3.1.3 Oscillator Safe Guard

The Oscillator Safe Guard (OSG) affords drastically increased operational integrity in ST62xx devices. The OSG circuit provides three basic func-

ST6252C ST6262B ST6262C

tions: it filters spikes from the oscillator lines which would result in over frequency to the ST62 CPU; it gives access to the Low Frequency Auxiliary Os cillator (LFAO), used to ensure minimum processing in case of main oscillator failure, to offer reduced power consumption or to provide a fixed frequency low cost oscillator; finally, it automatically limits the internal clock frequency as a function of supply voltage, in order to ensure correct opera tion even if the power supply should drop.

The OSG is enabled or disabled by choosing the relevant OSG option. It may be viewed as a filter whose cross-over frequency is device dependent.

Spikes on the oscillator lines result in an effectively increased internal clock frequency. In the absence of an OSG circuit, this may lead to an over fre quency for a given power supply voltage. The OSG filters out such spikes (as illustrated in

9.). In all cases, when the OSG is active, the max-

imum internal clock frequency, f

, which is supply voltage dependent. This re-

OSG

lationship is illustrated in Figure 12..

INT

When the OSG is enabled, the Low Frequency Auxiliary Oscillator may be accessed. This oscilla tor starts operating after the first missing edge of the main oscillator (see

Figure 10.).

Over-frequency, at a given power supply level, is seen by the OSG as spikes; it therefore filters out some cycles in order that the internal clock fre quency of the device is kept within the range the particular device can stand (depending on V and below f cy with OSG enabled.

: the maximum authorised frequen-

OSG

Note. The OSG should be used wherever possible as it provides maximum safety. Care must be tak en, however, as it can increase power consumption and reduce the maximum operating frequency

to f

OSG

Warning: Care has to be taken when using the OSG, as the internal frequency is defined between a minimum and a maximum value and is not accu rate.

For precise timing measurements, it is not recommended to use the OSG and it should not be enabled in applications that use the SPI or the UART.

It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature).

Figure

, is limited to

17/75

ST6252C ST6262B ST6262C

(1)

VR001932

(3)

(2)

(4)

(1) (2)

(3) (4)

Maximum Frequency for the device to work correctly Actual Quartz Crystal Frequency at OSCin pin

Noise from OSCin Resulting Internal Frequency

Main

VR001933

Internal

Emergency

Oscillator

Frequency

Oscillator

CLOCK SYSTEM (Cont’d)

Figure 9. OSG Filtering Principle

Figure 10. OSG Emergency Oscillator Principle

18/75

CLOCK SYSTEM (Cont’d)

MAIN

OSCILLATOR

OSG

LFAO

M U X

Core

: 13

TIMER 1

Watchdog

POR

INT

Main Oscillator off

2.5

3.644.555.56

Maximum FREQUENCY (MHz)

SUPPLY VOLTAGE (V

)

FUNCTIONALITY IS NOT

OSG

Min (at 85°C)

GUARANTEED

IN THIS AREA

VR01807J

OSG

Min (at 125°C)

Figure 11. Clock Circuit Block Diagram

ST6252C ST6262B ST6262C

Figure 12. Maximum Operating Frequency (f

Notes:

1. In this area, operation is guaranteed at the

quartz crystal frequency.

2. When the OSG is disabled, operation in this

area is guaranteed at the crystal frequency. When the OSG is enabled, operation in this area is guaranteed at a frequency of at least f

3. When the OSG is disabled, operation in this

OSG Min.

MAX

) versus Supply Voltage (VDD)

area is guaranteed at the quartz crystal frequency. When the OSG is enabled, access to this area is prevented. The internal frequency is kept a f

4. When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is prevented. The internal frequency is kept at f

OSG.

19/75

ST6252C ST6262B ST6262C

INT LATCH CLEARED

NMI MASK SET

RESET

( IF PRESENT )

SELECT

NMI MODE FLAGS

IS RESET STILL

PRESENT?

YES

PUT FFEH

ON ADDRESS BUS

FROM RESET LOCATIONS

FFE/FFF

FETCH INSTRUCTION

LOAD PC

VA000427

3.2 RESETS

The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD)

3.2.1 RESET Input

The RESET pin may be connected to a device of the application board in order to reset the MCU if required. The RUN, WAIT or STOP mode. This input can be used to reset the MCU internal state and ensure a correct start-up procedure. The pin is active low and features a Schmitt trigger input. The internal Reset signal is generated by adding a delay to the external signal. Therefore even short pulses on

RESET pin are acceptable, provided VDD has

the completed its rising phase and that the oscillator is running correctly (normal RUN or WAIT modes). The MCU is kept in the Reset state as long as the RESET pin is held low.

If RESET activation occurs in the RUN or WAIT modes, processing of the user program is stopped (RUN mode only), the Inputs and Outputs are con figured as inputs with pull-up resistors and the main Oscillator is restarted. When the level on the RESET pin then goes high, the initialization se quence is executed following expiry of the internal delay period.

If RESET pin activation occurs in the STOP mode, the oscillator starts up and all Inputs and Outputs are configured as inputs with pull-up resistors. When the level of the the initialization sequence is executed following expiry of the internal delay period.

3.2.2 Power-on Reset

The function of the POR circuit consists in waking up the MCU by detecting around 2V a dynamic (rising edge) variation of the VDD Supply. At the beginning of this sequence, the MCU is configured in the Reset state: all I/O ports are configured as inputs with pull-up resistors and no instruction is executed. When the power supply voltage rises to a sufficient level, the oscillator starts to operate, whereupon an internal delay is initiated, in order to allow the oscillator to fully stabilize before execut ing the first instruction. The initialization sequence

RESET pin may be pulled low in

RESET pin then goes high,

is executed immediately following the internal de lay.

To ensure correct start-up, the user should take care that the VDD Supply is stabilized at a suffi cient level for the chosen frequency (see recommended operation) before the reset signal is released. In addition, supply rising must start from 0V.

As a consequence, the POR does not allow to supervise static, slowly rising, or falling, or noisy (presenting oscillation) VDD supplies.

An external RC network connected to the RESET pin, or the LVD reset can be used instead to get the best performances.

Figure 13. Reset and Interrupt Processing

20/75

RESETS (Cont’d)

RESET

VR02106A

time

3.2.3 Watchdog Reset

The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. This, amongst oth er things, resets the watchdog counter.

The MCU restarts just as though the Reset had been generated by the

RESET pin, including the

built-in stabilisation delay period.

3.2.4 LVD Reset

The on-chip Low Voltage Detector, selectable as user option, features static Reset when supply voltage is below a reference value. Thanks to this feature, external reset circuit can be removed while keeping the application safety. This SAFE RESET is effective as well in Power-on phase as in power supply drop with different reference val

ues, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply.

As long as the supply voltage is below the reference value, there is a internal and static RESET command. The MCU can start only when the sup ply voltage rises over the reference value. Therefore, only two operating mode exist for the MCU: RESET active below the voltage reference, and running mode over the voltage reference as shown on the up, power-down sequence.

Note: When the RESET state is controlled by one of the internal RESET sources (Low Voltage De tector, Watchdog, Power on Reset), the RESET pin is tied to low logic level.

Figure 14. LVD Reset on Power-on and Power-down (Brown-out)

ST6252C ST6262B ST6262C

Figure 14., that represents a power-

3.2.5 Application Notes

No external resistor is required between VDD and the Reset pin, thanks to the built-in pull-up device.

Direct external connection of the pin RESET to

must be avoided in order to ensure safe be-

haviour of the internal reset sources (AND.Wired structure).

21/75

ST6252C ST6262B ST6262C

RESET

VECTOR

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION ROUTINE

VA00181

RESET

ESD

POWER

WATCHDOG RESET

COUNTER

RESET

ST6 INTERNAL RESET

OSC

RESET

ON RESET

LVD RESET

VR02107A

AND. Wired

1) Resistive ESD protection. Value not guaranteed.

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat ed in program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the In terrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode; this prevents the initialisation routine from being interrupted. The in itialisation routine should therefore be terminated by a RETI instruction, in order to revert to normal mode and enable interrupts. If no pending interrupt is present at the end of the initialisation routine, the MCU will continue by processing the instruction immediately following the RETI instruction. If, how ever, a pending interrupt is present, it will be serviced.

Figure 16. Reset Block Diagram

Figure 15. Reset and Interrupt Processing

22/75

3.3 RESETS (Cont’d)

Table 6. Register Reset Status

EEPROM Control Register

Port Data Registers

Port Direction Register

Port Option Register

Interrupt Option Register

TIMER Status/Control

0EAh

0C0h to 0C2h

0C4h to 0C6h

0CCh to 0CEh

0C8h

0D4h

00h

ST6252C ST6262B ST6262C

EEPROM enabled (if available)

I/O are Input with pull-up

Interrupt disabled

TIMER disabled

AR TIMER Mode Control Register

AR TIMER Status/Control 1 Register

AR TIMER Status/Control 2Register

AR TIMER Compare Register X, Y, V, W, Register

Accumulator

Data RAM

Data RAM Page REgister

Data ROM Window Register

EEPROM

A/D Result Register

AR TIMER Load Register

AR TIMER Reload/Capture Register TIMER Counter Register

TIMER Prescaler Register

Watchdog Counter Register

A/D Control Register

0D5h

0D6h

0D7h

0DAh 080H TO 083H

0FFh

084h to 0BFh

0E8h

0C9h

00h to F3h

0D0h

0DBh

0D9h 0D3h

0D2h

0D8h

0D1h

Undefined

FFh

7Fh

FEh

40h

AR TIMER stopped

As written if programmed

Max count loaded

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