ST ST2G3236 User Manual

2-bit dual supply bus transceiver level translator

Features

■ High speed:

–t

= 6.2 ns (max) at TA = 85 °C

PD

–V
–V

■ Low power dissipation:

–I

■ Symmetrical output impedance:

–|I

–|I

■ Balanced propagation delays:

–T

■

Power-down protection on inputs and outputs

■ 26 Ω series resistor on A side

■ Operating voltage range:

–V
–V

■ Max data rates:

– 380 Mbps (1.8 V to 3.3 V translation)
– 260 Mbps (<1.8 V to 3.3 V translation)
– 260 Mbps (translate to 2.5 V)
– 210 Mbps (translate to 1.5 V)

■ Latch-up performance exceeds 500 mA

(JESD17)

■ ESD performance:

– HBM > 2 kV (MIL STD 883 method 3015)
– MM > 200 V

= 1.8 V

CCB

= 3.3 V

CCA

= I

CCA

| = I

OHA

V

CCB

| = I

OHB

or 3.0 V; V

≈ T

PLH

CCA

CCB

= 5 µA (max) at TA = 85 °C

CCB

= 7 mA min at V

OLA

= 1.65 V or 2.3 V

= 2 mA min at V

OLB

= 1.65 V

CCB

PHL

(OPR) = 1.4 V to 3.6 V
(OPR) = 1.4 V to 3.6 V

= 2.75 V;

CCA

= 2.3 V

CCA

ST2G3236

with side series resistor

QFN10 (1.8 mm x 1.4 mm)

Description

The ST2G3236 is a dual supply, low-voltage
CMOS 2-bit bus transceiver produced with sub­micron silicon gate and five-layer metal wiring

2

C

MOS technology. Designed for use as an

interface between a 3.3 V bus and a 2.5 V or

1.8 V bus in mixed 3.3 V/1.8 V, 3.3 V/2.5 V and

2.5 V/1.8 V supply systems, it achieves high
speed operation while maintaining the CMOS low
power dissipation.

This IC is intended for two-way asynchronous
communication between data buses, and the
direction of data transmission is determined by
DIR inputs. The A-port interfaces with the 3 V bus,
and the B-port with the 2.5 V and 1.8 V bus.

All inputs are equipped with protection circuits to
protect against static discharge, giving them 2 kV
of ESD immunity and transient excess voltage.

Table 1. Device summary

Part number Package Packaging

ST2G3236 QFN10 (1.8 mm x 1.4 mm) Tape and reel

July 2010 Doc ID 12942 Rev 4 1/22

www.st.com

1

Contents ST2G3236

Contents

1 Logic diagram and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Application notes and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3 Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 Recommended power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin connections and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 DC electrical characteristics for V

4.2 DC electrical characteristics for V

4.3 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 Capacitance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CCA

. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CCB

5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/22 Doc ID 12942 Rev 4

ST2G3236 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 3. Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 6. DC specification for V
Table 7. DC specification for V

Table 8. AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 9. Capacitance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 10. Test values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 11. Waveform symbol value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12. QFN10L (1.8 mm x 1.4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 13. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CCA

CCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Doc ID 12942 Rev 4 3/22

List of figures ST2G3236

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Pin connections (top through view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Waveform - propagation delay (f = 1 MHz, 50% duty cycle). . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Waveform - output enable and disable time (f = 1 MHz, 50% duty cycle) . . . . . . . . . . . . . 15

Figure 7. QFN10L (1.8 mm x 1.4 mm) package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. QFN10L (1.8 mm x 1.4 mm) footprint recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 9. QFN10L (1.8 mm x 1.4 mm) carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10. QFN10L (1.8 mm x 1.4 mm) reel information - back view . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 11. QFN10L (1.8 mm x 1.4 mm) reel information - front view. . . . . . . . . . . . . . . . . . . . . . . . . . 20

4/22 Doc ID 12942 Rev 4

ST2G3236 Logic diagram and I/O equivalent circuit

1 Logic diagram and I/O equivalent circuit

Figure 1. Logic diagram

1B1A

DIR1

DIR2

A2

Figure 2. I/O equivalent circuit

OE

OE

B2

AM04932v1

CS15740

Doc ID 12942 Rev 4 5/22

Logic diagram and I/O equivalent circuit ST2G3236

1.1 Truth table

Table 2. Truth table

Inputs Function

Output

OE

L L Output Input B => A

L H Input Output B <= A

H X High-Z High-Z HIGH-Z

DIRn A BUS B BUS

1.2 Application notes and recommendations

1. Once the device is enabled (OE = low), even if the input is floating, output may be either
on high or low logic level only, not in a high-impedance state. Output is in a high­impedance state only when OE

2. Unused I/O channel should be connected to GND or to the corresponding supply.

3. The OE
to V
V

and DIRn block is powered by V
. The OE and DIRn input high level can be equal to or greater than V

CCB

max.

IHB

4. Any input high level can be higher than the corresponding input supply voltage, up to
V

IHA

max (V

IHB

max).

Example:

= high.

and these input logic levels are referenced

CCB

CCB

, up to

V

= 1.8 V, V

CCA

= 2.6 V, OE = Low, DIRn = Low (B → A direction)

CCB

==> if I/O Bn = 3 V, I/O An = 1.8 V

5. If V

CCA

= V

= 0 V and OE = 0 V, An and Bn are isolated even if there is a signal on

CCB

An or Bn.

6. If the ST2G3236QTR is used in a UART application, there is a possibility of floating
input condition if the cable is disconnected, therefore a pull-down resistor is
recommended on the input port.

1.3 Recommended power-up sequence

1. Apply power to either VCC.

2. Apply power to the OE

input and to the respective data inputs. This may occur at the

same time as step 1.

3. Apply power to the other V

4. Drive the OE

input LOW to enable the device.

CC

.

1.4 Recommended power-down sequence

1. Drive the OE input HIGH to disable the device.

2. Remove power from either V

3. Remove power from the other V

CC

.

CC

.

6/22 Doc ID 12942 Rev 4

ST2G3236 Pin connections and descriptions

2 Pin connections and descriptions

2.1 Pin connections

Figure 3. Pin connections (top through view)

A2

A1

10

9

1

8

V

CCA

2.2 Pin descriptions

Table 3. Pin descriptions

Pin Symbol Name and function

1, 3 DIR1, DIR2 Directional controls

10 A1 Data inputs/outputs

4 B1 Data outputs/inputs

9 A2 Data inputs/outputs

5 B2 Data outputs/inputs

7 GND Ground (0 V)

8V

2V

6OE

CCA

CCB

CCB

2

3

4

V

B1

Positive supply voltage

Positive supply voltage

Output enable (active low)

5

B2

7

GND

OE

6

OE

AM04933v1

Doc ID 12942 Rev 4 7/22