Datasheet ST24LW21, ST24LC21B, ST24FW21, ST24FC21 Datasheet (SGS Thomson Microelectronics)

1 Kbit (x8) Dual Mode Serial EEPROM

1 MILLION ERASE/WRITE CYCLES
40 YEARS DA TA RETE NTION

3.6V to 5.5V SINGLE SUPPLY VOLTA GE
HARDWARE WRITE CONT ROL (ST24LW21

and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I2C

BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I2C BUS

COMPATIBLE
I2C PAGE WRITE (up to 8 Bytes)
I2C BYTE, RANDOM and SEQUENTIAL RE AD

MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCE D ESD/LATCH UP

PERFORMANCES
ERROR RECOVERY MECHA NI SM

(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE

ST24LC21B, ST24LW21

ST24FC21, ST24FW21

for VESA PLUG & PLAY

8

1

PSDIP8 (B)

0.25mm Frame

Figure 1. Logic Diagram

8

1

SO8 (M)

150mil Width

V

DESCRIPTION

CC

The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are 1K bit electrically erasable pro­grammable memory (EEPROM), organized in
128x8 bits. In the text, products are referred as

SCL

SDA

ST24xy21, where "x" is either "L" for VESA 1 or "F"
for VESA 2 com patible memories and where "y"
indicates the Write Control pin connection: "C"

ST24xy21VCLK

means WC on pin 7 and "W" means WC on pin 3.

WC

T ab le 1. Signal Names

SDA Serial Data Address Input/Output

2

SCL Serial Clock (I
V

CC

V

SS

VCLK Clock Transmit only mode
WC Write Control

January 1999 1/21

Supply Voltage
Ground

C mode)

Note:

WC signal is only available for ST24LW21 and ST24FW21
products.

V

SS

AI01741

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 2A. DIP Pin Connections

ST24LC21B

8
7
6
5

AI01742

VCLKNC
SCL
SDAV

Warning:

1

NC V

2
3

NC

4

SS

NC = Not Connected.

Figure 2C. DIP Pin Connections

ST24FC21

1

NC V

2
3

DU

4

SS

8
7
6
5

AI01744

VCLKNC
SCL
SDAV

CC

CC

Figure 2B. SO Pin Connections

ST24LC21B

8
7
6
5

AI01743

Warning:

NC V

1
2

NC

SS

NC = Not Connected.

3
4

Figure 2D. SO Pin Connections

ST24FC21

NC V

1
2

DU

SS

3
4

8
7
6
5

AI01745

CC

VCLKNC
SCL
SDAV

CC

VCLKNC
SCL
SDAV

Warning:

be left open or connected to V

NC = Not Connected. DU = Don’t Use, must

or VSS.

CC

Figure 2E. DIP Pin Connections

ST24FW21
ST24LW21

8
7
6
5

AI01746

VCLKNC
SCL
SDAV

Warning:

2/21

1

NC V

2
3

WC

4

SS

NC = Not Connected.

CC

Warning:

be left open or connected to V

NC = Not Connected. DU = Don’t Use, must

or VSS.

CC

Figure 2F. SO Pin Connections

ST24FW21
ST24LW21

8
7
6
5

AI01747

Warning:

NC V

1
2

WC

SS

NC = Not Connected.

3
4

CC

VCLKNC
SCL
SDAV

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

T ab le 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

T

T

V

Notes:

T

STG

LEAD

V

V

ESD

Ambient Operating Temperature –40 to 85

A

Storage Temperature –65 to 150
Lead Temperature, Soldering (SO8 package)

Input or Output Voltages –0.3 to 6.5 V

IO

Supply Voltage –0.3 to 6.5 V

CC

Electrostatic Discharge Voltage (Human Body model)
Electrostatic Discharge Voltage (Machine model)

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress rating s only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

(1)

(PSDIP8 package)

40 sec
10 sec

(2)

(3)

215
260

4000 V

500 V

T ab le 3. Device Select Code

Device Code Chip Enable RW

Bit b7 b6 b5 b4 b3 b2 b1 b0
Device Select 1 0 1 0 X X X R

Note:

The MSB b7 is sent first.
X = 0 or 1.

W

C

°

C

°

C

°

DESCRIPTION (cont’d)
The ST24xy21 can operate in two modes: Trans-

mit-Only mode and I

2

C bidirectional mode. When
powered, the device is in Tr ansmit-Only mode with
EEPROM data clocked out from the rising edge of
the signal applied on VCLK.

2

The device will switch to the I
upon the falling edge of the signal applied on SCL
pin. When in I

2

C mode, the ST24LC21B (or the

C bidirectional mode

ST24LW21) cannot switch back to the Transmit
Only mode (except when the power supply is re­moved). For the ST24FC21 (or the ST24FW21) ,
after the falling edge of SCL, the memory enter in
a transition state which allowed to switch back to
the Transmit-Only mode if no valid I

2

C activity is
observed. The device operates with a power supply
value as low as +3.6V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.

Transmit Only Mode

After a Power-up, the ST24xy21 is in the Transmit
Only mode. A proper initialization sequence (see
Figure 3) must supply nine clock pulses on the
VCLK pin (in order to internally synchronize the
device). During this initialization sequence, the
SDA pin is in high im pedance. On the rising edge
of the tenth pulse applied on VCLK pin, the device
will output the first bit of byte located at address 00h
(most significant bit first).

A byte is clocked out (on SDA pin) with nine clock
pulses on VCLK: 8 clock pulses for the data byte
and one extra clock pulse for a Don’t Care bit.

As long as the SCL pin is held high, each byte of
the memory array is transm itted serially on the SDA
pin with an automatic address increment.

When the last byte is transmitted, the address
counter will roll-over to location 00h.

3/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 3. Transmit Only Mode Wavefor ms

V

CC

SCL

SDA

VCLK

V

CC

SCL

SDA

VCLK

tVPU
1 2 8 9 10 11

Bit 6 Bit 4 Bit 0

Bit 5

12 13 17 18 19 20

Bit 7

Bit 7

Bit 6

Bit 6

AI01501

T able 4. I2C Operating Modes

Mode

Current Address
Read

Random Address
Read

R

ST24LC21B

W

bit

ST24FC21

VCLK

’1’ X X 1 START, Device Select, R

’0’ X X

’1’ X X reSTART, Device Select, R
Sequential Read ’1’ X X 1 to 128 Similar to Current or Random Mode
Byte Write ’0’ V
Page Write ’0’ V

Note:

X = V

or V

IH

IL

IH

IH

4/21

ST24LW21
ST24FW21WCBytes Initial Sequence

W = ’1’

START, Device Select, RW = ’0’, Address,

1

W = ’1’

V

IH

V

IH

1 START, Device Select, RW = ’0’
8 START, Device Select, RW = ’0’

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 4. Transition from Transmit Only (DDC1) to Bi-directional (DDC2B) Mode Waveforms

Transmit Only Mode

SCL

SDA

VCLK

- Temporary Bi-Directional Mode
(ST24FC21 and ST24FW21)

- Locked Bi-Directional Mode
(ST24LC21B and ST24LW21)

START
CONDITION

I2C Bidirectional Mode

The ST24xy21 can be switched from T ransmit Only
mode to I

2

C Bidirectional mode by apply ing a valid

high to low transition on the SCL pin (see Figure 4).
– When the ST24LC21B (or the ST24FC21) is in

2

C Bidirectional mode, the VCLK input

the I
(pin 7) enables (or inhibits) the exec ution of
any write instruction: if VCLK = 1, write instruc­tions are executed; if VCLK = 0, write instruc­tions are not executed.

– When the ST24LW21 (or the ST24FW21) is in

2

C Bidirectional mode, the Write Control

the I
(WC on pin 3) input enables (or inhibits) the
execution of any write instruction: if WC = 1,
write instructions are executed;if WC = 0,
write instructions are not executed.

2

The ST24xy21 is compatible with the I

C standard,
two wire serial interface whic h uses a bidirectional
data bus and serial clock. The device carries a
built-in 4 bit, unique device identification code
(1010) named Device Select code corresponding

2

to the I
The ST24xy21 behaves as a slave device in t he

2

I

C bus definition.

C protocol with all memory operations synchro­nized by the serial clock SCL. Read and write
operations are initiated by a STAR T condition gen-

- Locked Bi-Directional
Mode (ST24FC21
and ST24FW21)

1

MSB

2

89

ACK

erated by the bus master. The START condition is
followed by a stream of 7 bits (Device Select code
1010XXX), plus one read/write bit and terminated
by an acknowledge bit.

When data is written into the memory, the
ST24xy21 responds to the 8 bits received by as­serting an acknowledge bit during the 9th bit time.
When data is read by the bus master, it must
acknowledges the receipt of the data bytes in the
same way. Data transfers are terminated with a
STOP condition (see READ and WRITE desc rip­tions in the following pages).

Power On Reset: V

lock out write protect

CC

In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the V
voltage has reached the POR threshold value
(around 3V), the internal reset is active, all opera­tions are disabled and the device will not respond
to any command. In the same way, when V
down from the operating voltage to below the P OR
threshold value, all operations are disabled and the
device will not respond to any command. A stable

must be applied before applying any logic

V

CC

signal.

AI01892

CC

CC

drops

5/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21 and ST24FW21 products

Memory Power On

Internal Address Pointer = 0

Transition

State

(VESA 2)

VCLK

NO

NO

VCLK Internal Counter = 0

Start Internal 2 sec Timer

(START + Device Select)

NO

SCL

SDA Hi-Z

SCL

NO

Valid

2

C access

I

VCLK

YES

YES

YES

?

Send Data bit (MSB first) pointed

by the Address Pointer and

auto-increment pointed bit/byte

Reset VCLK Internal Counter

and Reset Internal Timer

YES

I2C communication idle

waiting for a Device Select byte

Transmit-Only Mode
(DDC1)

6/21

Increment VCLK Counter

NO

Counter = 128

or Timer > 2 sec

Switch Back to

Transmit-Only Mode

YES

YES

Reset Counter and Timer

Send Acknowledge

Respond to the Incoming

2

C Command

I

I2C Mode
(DDC2B)

AI01748

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 6. Maximum RL Value versus Bus Capacitance (C

20

16

12

8

Maximum RP value (kΩ)

4

0

10 1000

C

BUS

fc = 400kHz

100

(pF)

Error Recovery Modes available in the
ST24FC21 and the ST24FW21

When the ST24FC21 (or the ST24FW21) first
switches to the I
enters a transition state which is functionally iden­tical to I

2

C operation. But, if the ST24FC21 (or the

2

C mode (VESA DDC2B mode), it

ST24FW21) does not received a valid I
quence, that is a START condition followed by a
valid Device Select code (1010XXX R

W), within
either 128 VCLK periods or a period of time of
t

RECOVERY

(approximately 2 seconds), the
ST24FC21 (or the ST24FW21) will revert to the
Transmit-Only mode (VESA DDC1 mode).

If the ST24FC21 (or the ST24FW21) decodes a

2

valid I

C Device Select code, it will lock into I2C
mode. Under this condition, signals applied on the
VCLK input will not disturb READ access from the
ST24FC21 (or the ST24FW21). For WRITE ac­cess, refer to the Signal Desc r iption paragraph.

When in the transition state, the count of VCLK
pulses and the internal 2 seconds timer are reset
by any activity on the SCL line. This me ans that,
after each high to low transition on SCL, the m em­ory will re-initialise its transition state and will switch
back to Transmit-Only mode only after 128 more
VCLK pulses or after a new t

RECOVERY

delay.

2

C se-

fc = 100kHz

SIGNAL DESCRIP TIONS
I

to synchronize all data in and out of the memory . A
resistor can be connected from the SCL line to V
to act as a pull up ( see Figure 6).

Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V

Tr ansmit Only Clock (VCLK). The VCLK input pin
is used to synchronize data out when the
ST24xy21 is in Transmit Only mode.

For the ST24LC21B and the ST24FC21 Only, the
VCLK offers also a Write Enable (active high) func­tion when the ST24LC21B and the ST24FC21 are
in I

Write Control (WC). An hardware Wri te Control
feature (WC) is offered only on ST24LW21 and
ST24FW21 on pin 3. This feature is usefull to
protect the contents of the memory from any erro­neous erase/write cycle. The Write Control signal
is used to enable (WC = V
the internal write protection. When unconnected,
the WC input is internally tied to V

2

C Serial Clock (SCL). The SCL input pin is used

2

C bidirectional mode.

pull-down resistor and the memory is write pro­tected.

) for an I2C Bus

BUS

V

MASTER

to act as pull up (see F igure 6).

CC

CC

R

SDA

SCL

) or disable (WC = VIH)

IL

R

L

SS

L

C

BUS

AI01665

by a 100k ohm

C

BUS

CC

7/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

T able 5. Input Parameters

(1)

(TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

C

IN

C

IN

t

LP

Note:

1. Sampled only, not 100% tested.

Input Capacitance (SDA) 8 pF
Input Capacitance (other pins) 6 pF
Low-pass filter input time constant

(SDA and SCL)

200 500 ns

T ab le 6. DC Characteristics
(T

= –40 to 85 °C; VCC = 3.6V to 5.5V)

A

Symbol Parameter Test Condition Min Max Unit

Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current

Supply Current
Supply Current V

Supply Current (Standby)

Supply Current (Standby)

0V ≤ V

V

= 5V, fC = 400kHz

CC

(Rise/Fall time < 10ns)

= 3.6V, fC = 400kHz 1 mA

CC

V

IN

V

CC

V

IN

= 5V, fC = 400kHz

V

CC

V

IN

V

CC

V

IN

V

= 3.6V, fC = 400kHz

CC

≤ VCC

OUT

SDA in Hi-Z

= VSS or VCC,

= 5V, fC = 0

= VSS or VCC,

= VSS or VCC,

= 3.6V, fC = 0

= VSS or VCC,

Input Low Voltage
(SCL, SDA, WC)

Input High Voltage
(SCL, SDA, WC)

= 5.5V 1.4 2.1 V

V

High Level Threshold Voltage
(Schmitt Trigger on VLCK)

Low Level Threshold Voltage
(Schmitt Trigger on VLCK)

Hysteresis Voltage
(Schmitt Trigger on VLCK)

Output Low Voltage

CC

= 4.5V 1.2 1.9 V

V

CC

= 3.6V 1 1.7 V

V

CC

= 5.5V 0.6 1.4 V

V

CC

= 4.5V 0.5 1.2 V

V

CC

= 3.6V 0.4 1 V

V

CC

= 5.5V 0.4 1.5 V

V

CC

= 4.5V 0.4 1.4 V

V

CC

= 3.6V 0.35 1.3 V

V

CC

= 3mA, VCC = 3.6V 0.4 V

I

OL

= 6mA, VCC = 5V 0.6 V

I

OL

CC

–0.3 0.3 V

0.7 V

CC

2

±

2

±

2mA

100

300

30

100

CC

VCC + 1 V

I

I

V

V

I

LI

I

LO

I

CC

CC1

CC2

V

V

V

V

OL

IL

IH

P

N

H

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

V

8/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

T ab le 7. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 400kHz

(T

= –40 to 85 °C; VCC = 3.6V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

t
t

Notes:

(1)

CH1CH2

(1)

CL1CL2

(1)

DH1DH2

(1)

t

DL1DL2

(2)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

t

CLQV

t

CLQX

f

C

t

tWRWrite Time 10 ms

W

1. Sampled only, not 100% tested.

2. For a reSTART condition, or following a write cycle.

t
t
t
t

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

R

F

R

F

Clock Rise Time 300 ns
Clock Fall Time 300 ns
SDA Rise Time 20 300 ns
SDA Fall Time 20 300 ns
Clock High to Input Transition 600 ns
Clock Pulse Width High 600 ns
Input Low to Clock Low (START) 600 ns
Clock Low to Input Transition 0
Clock Pulse Width Low 1.3
Input Transition to Clock Transition 100 ns
Clock High to Input High (STOP) 600 ns
Input High to Input Low (Bus Free) 1.3
Clock Low to Data Out Valid 200 900 ns
Clock Low to Data Out Transition 200 ns
Clock Frequency 400 kHz

s

µ

s

µ

s

µ

DEVICE O PERATION

2

C Bus Background

I

The ST24xy21 supports the I

2

C protocol. This pro­tocol defines any device that sends data ont o the
bus as a transmitter and any device that reads the
data as a receiver. The device that controls the data
transfer is known as the master and the other as
the slave. The master will always initiate a data
transfer and will provide the serial clock for syn­chronisation. The ST24xy21 are always slave de­vices in all communications.

Start Condition . START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A ST AR T condition must
precede any command for data transfer. Except
during a programming cycle, the ST24xy21 con­tinuously monitor the SDA and SCL signals for a
START condition and will not res pond unless one
is given.

Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high s tate. A STOP c ondition termi­nates communication between the ST24xy21 and
the bus master. A STOP condition at the end of a
Read command (after the No ACK) forces the
standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM
write cycle.

Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, eit her master or s lave, will releas e
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.

Data Input. During data input, the ST24xy21 sam­ple the SDA bus signal on the rising edge of the
clock SCL. Note that for correct device operation
the SDA signal must be stable during the clock low
to high transition and the data must change ONLY
when the SCL line is low.

9/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

T ab le 8. AC Characteristics, I2C Bidirectional Mode for Clock Frequency = 100kHz

(T

= –40 to 85 °C; VCC = 3.6V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

CH1CH2

t

CL1CL2

t

DH1DH2

t

DL1DL1

(1)

t

CHDX

t

CHCL

t

DLCL

t

CLDX

t

CLCH

t

DXCX

t

CHDH

t

DHDL

(2)

t

CLQV

t

CLQX

f

C

t

W

Notes:

1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.

t

t

t

t

t

SU:STA

t

HIGH

t

HD:STA

t

HD:DAT

t

LOW

t

SU:DAT

t

SU:STO

t

BUF

t

AA

t

DH

f

SCL

t

WR

R

F

R

F

Clock Rise Time 1
Clock Fall Time 300 ns
Input Rise Time 1
Input Fall Time 300 ns
Clock High to Input Transition 4.7
Clock Pulse Width High 4
Input Low to Clock Low (START) 4
Clock Low to Input Transition 0
Clock Pulse Width Low 4.7
Input Transition to Clock Transition 250 ns
Clock High to Input High (STOP) 4.7
Input High to Input Low (Bus Free) 4.7
Clock Low to Next Data Out Valid 0.2 3.5
Data Out Hold Time 200 ns
Clock Frequency 100 kHz
Write Time 10 ms

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

Table 9. AC Characteristics, Transmit-only Mode

(T

= –40 to 85 °C; VCC = 3.6V to 5.5V)

A

Symbol Alt Parameter Min Max Unit

t

VCHQX

t

VCHVCL

t

VCLVCH

t

CLQZ

(1,2)

t

VPU

(2)

t

VH1VH2

(2)

t

VL1VL2

t

RECOVERY

Notes:

(2)

1. Refer to Figure 3.

2. Sampled only, not 100% tested.

10/21

t

VAA

t

VHIGH

t

VLOW

t

VHZ

t
t

Output Valid from VCLK 500 ns
VCLK High Time 600 ns
VCLK Low Time 1.3
Mode Tansition Time 500 ns
Transmit-onl y Power-up Time 0 ns

R

F

VCLK Rise Time 1
VCLK Fall Time 1
Recovery Time 1.5 3.5 sec

s

µ

s

µ

s

µ

Figure 7. AC Waveforms

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

SCL

SDA IN

SCL

SDA OUT

SCL

tCHCL

tDLCL

tCHDX

START

CONDITION

tCLQV tCLQX

tDHDL

tCLDX

SDA

INPUT

DATA VALID

DATA OUTPUT

SDA

CHANGE

tW

tCLCH

tDXCX

tCHDH

tDHDL

STOP &

BUS FREE

SDA IN

VCLK

SDA

SCL

tCHDH

STOP

CONDITION

WRITE CYCLE

tVCHVCL tVCLVCH

tVCHQX

tCHDX

START

CONDITION

tCLQZ

AI01503

11/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

T able 10. AC Measurement Conditions

Input Rise and Fall Times
Input Pulse Voltages SDA, SCL 0.2V
Input Pulse Voltages V

CLK

Input and Output Timing Ref.
Voltages

50ns

≤

to 0.8V

CC

0.4V to 2.4V

0.3V

to 0.7V

CC

Figure 9. I2C Bus Protocol

SCL

SDA

START

CONDITION

CC

CC

SDA

INPUT

Figure 8. AC Testing Input Output Waveforms

0.8V

CC

0.2V

CC

SDA

CHANGE

STOP

CONDITION

0.7V

0.3V

AI00825

CC

CC

SCL

SDA

SCL

SDA

START

CONDITION

1 23 789

MSB

1 23 789

MSB ACK

ACK

STOP

CONDITION

AI00792

12/21

Figure 10. Write Cycle Polling using ACK

WRITE Cycle

in Progress

START Condition

DEVICE SELECT

with RW = 0

ACK

NO

Returned

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

First byte of instruction
with RW = 0 already
decoded by ST24xxx

ReSTART

STOP

YES

Next

Operation is

Addressing the

Memory

WRITE Operation

Memory Addressing. To start communication be­tween the bus master and the slave ST24xy21, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the Device Select
code (7 bits) and a READ or WRITE bit. The 4 most
significant bits of the Device Select code are the
device type identifier, corresponding to the I

2

C bus
definition. For these memories the 4 bits are fix ed
as 1010b. The following 3 bits are Don’t Care. The
8th bit sent is the read or write bit (R

W), this bit is
set to ’1’ for read and ’0’ for write operations. If a
match is found, the corresponding memory will
acknowledge the identification on the SDA bus
during the 9th bit time.

YESNO

Send

Byte Address

Proceed

Proceed

Random Address

READ Operation

AI01099B

Write Operations

Following a START condition the master sends a
Device Select code with the R

W bit set to ’0’. The
memory acknowledges this and waits for a byte
address. After receipt of the byte add ress the de­vice again responds with an acknowledge.

2

In I

C bidirectional mode, any write command with
VCLK=0 (for the ST24LC21B and ST24FC21) or
with WC=0 (for the ST24LW 21 and ST24FW21) will
not modify data and will be acknowledged on data
bytes, as shown in Figure 12.

Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.

13/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 11. Write Modes Sequence

VCLK/WC

ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

R/W

START

VCLK/WC

ACK ACK

DATA IN 1 DATA IN 2

PAGE WRITE

ACK

DEV SEL BYTE ADDR

R/W

START

ACK ACK

DATA IN N

ACK

STOP

Page Wri te . The Page Write mode allows up to 8
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the most significant memory ad­dress bits are t he same. The master sends from
one up to 8 bytes of data, which are each acknow­ledged by the memory.

After each byte is transfered, the internal byte
address counter (3 least significant bits only) is
incremented. The transfer is terminated by the
master generating a STOP condition. Care must be
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for
any write mode, the generation by the master of the
STOP condition starts the internal memory pro­gram cycle. All inputs are disabled until the comple-

14/21

STOP

AI01893

tion of this cycle and the memory will not respond
to any request.

Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon­nects itself from the bus in order to cop y the data
from the internal latches to the memory cells. The
maximum value of the write time (t

) is given in the

W

AC Characteristics table, since the t ypical time is
shorter, the time seen by t he system may be re­duced by an ACK polling sequence issued by the
master. The sequence is as follows:

– Initial condition: a Write is in progress (see Fig-

ure 10).

– Step 1: the Master issues a START condition

followed by a Device Select byte (1st byte of
the new instruction).

Figure 12. Inhibited Write when VCLK/WC = 0

VCLK/WC

CONTROL

BYTE

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

ACK ACK

BYTE WRITE

START

CONTROL

BYTE

PAGE WRITE WORD ADD n DATA n DATA n + 1

START

– Step 2: if the memory is busy with the internal

write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem­ory is ready to receive the second part of the
instruction (the first byte of this instruction was
already sent during Step 1).

Read Operations

On delivery, the memory content is set at all "1’s"
(or FFh).

Current Address Read. The memory has an inter­nal byte address counter . Each time a byte is read,
this counter is incremented. For the Current Ad­dress Read mode, following a START condition,
the master sends the Device Select code with the

W bit set to ’1’. The memory acknowledges t his

R
and outputs the data byte addressed by the internal
byte address counter. This counter is then incre­mented. The master must NOT acknowledge the
data byte output and terminates the transfer with a
STOP condition.

Random Address Read. A dummy write is per­formed to load the address into the address
counter, see Figur e 14. This is followed by a Re-

WORD ADDR DATA

ACK

ACK

ACK

START condition send by the master and the De­vice Select code is repeated with the RW bit set t o
’1’. The memory acknowledges this and outputs the
addressed data byte. The master must NOT ac­knowledge the data byte output and terminates the
transfer with a STOP condition.

Sequential Read. This mode can be initiated with
either a Current Address Read or a Random Ad­dress Read. However, in this case the master
DOES acknowledge the data byte output and the
memory continues to output the next byte in se­quence. To terminate the stream of bytes, the
master must NOT acknowledge the last data byte
output, and MUST generate a STOP condition.

The output data is from consecutive byte ad­dresses, with the internal byte address counter
automatically incremented after each byte output.
After a count of the last memory address, the
address counter will ’roll-over’ and the memory will
continue to output data.

Acknowledge in Read Mode. In all read modes
the ST24xy21 wait for an acknowledge during the
9th bit time. If the master does not pull the SDA line
low during this time, the ST24xy21 terminate the
data transfer and switches to a st andby state.

ACK

STOP

ACKACK

DATA n + 7

STOP

AI01894

15/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Figure 13. Recommended Schematic for VESA 2.0 Specification

+5V

SCL

SDA

VSync

9

15

12

14

NOTE CONCERNING THE POWER SUPPLY
VOLTAG E I N THE VESA 2.0 SPECIF I CATION

According to the VESA 2.0 specification, the
ST24xy21 can be supplied by either the MONITOR
or by the HOST (using +5V on the VGA cable pin

9) power supply. The easyest way to implement this
is to use 2 diodes as described in the following
schematic. The ST24xy21 supply voltage will be
decreased by 0.6V, which is the diode forward
voltage drop, and will be below 4.5V . Nevertheless,

+5V Monitor

V

SCL

SDA

VCLK

CC

100nF

V

SS

AI01749

47kΩ

MONITORHOST VGA Cable

the ST24xy21 remains operational and no input will
be damaged if the applied voltage on any input
complies with the Absolute Maximum Ratings val­ues.

Under this condition, the threshold voltage of the
Schmitt-Trigger (pin 7) will be decreased (as in
Table 6).

Refer to the AN627 Application Note for more de­tailed information regarding the use and the protec­tion of the ST24xy21 in a Monitor application.

16/21

Figure 14. Read Modes Sequence

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

CURRENT
ADDRESS
READ

RANDOM
ADDRESS
READ

SEQUENTIAL
CURRENT
READ

SEQUENTIAL
RANDOM
READ

ACK

DEV SEL DATA OUT

R/W

START

ACK

DEV SEL * BYTE ADDR

R/W

START

ACK ACK ACK NO ACK

DEV SEL DATA OUT 1

R/W

START

ACK ACK

DEV SEL * BYTE ADDR

NO ACK

STOP

ACK ACK

DEV SEL * DATA OUT

R/W

START

DEV SEL * DATA OUT 1

NO ACK

STOP

DATA OUT N

STOP

ACK ACK

R/W

START

ACK NO ACK

DATA OUT N

STOP

Note:

* The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

START

R/W

AI00794C

17/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

ORDERING INFORMATION SCHEME

Example: ST24LC21B M 1 TR

Family Range

ST24LC21B VESA 1

WC on pin 7

ST24LW21 VESA 1

WC on pin 3

ST24FC21 VESA 2

WC on pin 7

ST24FW21 VESA 2

WC on pin 3

Package

B PSDIP8

0.25mm Frame

M SO8

150mil Width

Temperature Range

1 0 to 70 °C
6 –40 to 85 °C

Option

TR Tape & Reel

Packing

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Package, etc...) or for further information on any aspect of this device, please
contact the STMicroelectronics Sales Office nearest to you.

18/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

Symb

Typ Min Max Typ Min Max

A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209

B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065

C 0.20 0.36 0.008 0.014

D 9.20 9.90 0.362 0.390

E 7 .62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264
e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –
eB 10.00 0.394

L 3.00 3.80 0.118 0.150

N8 8

PSDIP8

mm inches

Drawing is not to scale.

A2

A1AL

B

e1

B1

D

N

C

eA
eB

E1 E

1

PSDIP-a

19/21

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

SO8 - 8 lead Plastic Small Outline, 150 mils body width

Symb

Typ Min Max Typ Min Max

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e1.27– –0.050– –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035

α

N8 8

CP 0.10 0.004

SO8

mm inches

0

°

8

°

0

°

8

°

Drawing is not to scale.

20/21

B

SO-a

h x 45˚

A

C

e

CP

D

N

E

H

1

LA1 α

ST24LC21B, ST24LW21, ST24FC21, ST24FW21

Information furnished is believ ed to be accura te and reliable. Ho wever, STMicroelectronics as sum es no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelect roni cs

© 1999 STMicroelectronics - All Rights Reserved

All other names are the property of their respective owners

2

2

I

Purchase of I

C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to

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C Components by STMicroelectronics, conveys a license under the Philips

2

C Standard Specifications as defined by Philips.

the I

STMicroelectronics GROUP OF COMPANIES

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21/21