ST ST2129 User Manual

Features

■ 42 MHz: 84 Mbps (max) data rate at

V

= 1.8 V, VCC = 3.3 V

L

■ Bidirectional level translation without direction

control pin

■ Wide voltage range (V

–V

■ Power down mode feature - when V

ranges from 1.65 to 3.6 V

L

ranges from 1.65 to 5.5 V

CC

≥ VL):

supply

CC

is off, all I/Os are in high impedance

■ Totem-pole driving

■ 5.5 V tolerant enable pin

■ ESD performance on all pins : ±2 kv HBM

■ Small package and footprint:

QFN10 (1.8 x 1.4 mm)

Applications

■ Low voltage system level translation

■ Mobile phones and other mobile devices

ST2129

2-bit dual supply level translator

without direction control pin

QFN10

(1.8 x 1.4 mm)

Description

The ST2129 is a 2-bit dual supply level translator which provides the level shifting capability to allow data transfer in a multi-voltage system. Externally applied voltages, V on either side of the device. Its architecture allows bidirectional level translation without a control pin.

The ST2129 accepts V V

from 1.65 to 5.5 V, making it ideal for data

CC

transfer between low-voltage ASICs/PLD and higher voltage systems. This device has a tri-state output mode which can be used to disable all I/Os.

and VL, set the logic levels

CC

from 1.65 to 3.6 V and

L

The ST2129 supports power-down mode when V

is grounded/floating or when the device is

CC

disabled via the OE pin.

Table 1. Device summary

Order Code Package Packaging

ST2129QTR QFN10 (1.8 x 1.4 mm) Tape & reel (3000 parts per reel)

September 2009 Doc ID 15967 Rev 1 1/20

www.st.com

20

Pin settings ST2129

1 Pin settings

1.1 Pin connection

Figure 1. Pin connection (top through view)

V

I/O

VL1

V

10 9

1

CC

L

8

I/O

VCC1

I/O

VL2

OE

1.2 Pin description

Table 2. Pin description

Pin number Symbol Name and function

1I/O

2I/O

3 OE Output enable

4 NC No connection

5 NC No connection

6 GND Ground

7I/O

8I/O

9V

10 V

2

3

VL1

VL2

VCC2

VCC1

CC

L

4

5

NC NC

7

6

I/O

GND

Data input/output

Supply voltage

VCC2

CS00011

2/20 Doc ID 15967 Rev 1

ST2129 Logic diagram

2 Logic diagram

Figure 2. Logic block diagram

2.1 Device block diagrams

Figure 3. ST2129 block diagram

Doc ID 15967 Rev 1 3/20

Logic diagram ST2129

Figure 4. Application block diagram

V

L

0.1 μF

V

L

system

controller

VL

I/O

VL1

I/O

VL2

V

CC

V

CC

I/O

VCC1

I/O

VCC2

system

controller

F

0.1 μ

OE

1 μF

CC

AM00708V2

4/20 Doc ID 15967 Rev 1

ST2129 Supplementary notes

3 Supplementary notes

3.1 Driver requirement

For proper operation, the driver from each side of the device must have the capability to source and sink a minimum of 1mA current. The device architecture requires the driver to source/sink a maximum current of (V

3.2 Load driving capability

To support the architecture that allows level translation without direction pin, the one-shot transistor is turned on only during state transition at the output side. After the one-shot transistor is turned off, only the 4 kΩ resistor maintains the state. So, resistive load or pull-up resistor less than 50 kΩ is not recommended for a proper operation.

3.3 Power off feature

In some applications, where it might be required to turn off one of the power supplies powering up the level translator, the device is automatically disabled when V turned off, even if the OE pin is set to HIGH (enabled). In this mode, all I/Os are in high impedance state.

/4) mA to/from the weak 4 kΩ output buffer.

CC

supply is

CC

3.4 Truth table

Table 3. Truth table

Enable Bidirectional Input/Output

OE I/O

H

(1) High level VL power supply referred.

(2) High level V

(3) Z = High impedance.

CC

VCC

(1)

LZ

power supply referred.

(2)

H

LL

(3)

I/O

H

Z

VL

(1)

(3)

Doc ID 15967 Rev 1 5/20

Maximum ratings ST2129

4 Maximum ratings

Stressing the device above the rating listed in Tabl e 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

V

CC

V

OE

V

I/OVL

V

I/OVCC

I

IK

I

I/OVL

I

I/OVCC

I

SCTOUT

P

T

STG

T

Supply voltage -0.3 to 4.6 V

L

Supply voltage -0.3 to 6.5 V

DC control input voltage -0.3 to 6.5 V

DC I/OVL input voltage (OE = GND or VL) -0.3 to VL + 0.3 V

DC I/O

input voltage (OE = GND or VL) -0.3 to VCC + 0.3 V

VCC

DC input diode current -20 mA

DC output current ±25 mA

DC output current ±258 mA

Short circuit duration, continuous 40 mA

Power dissipation

D

(1)

Storage temperature -65 to 150

Lead temperature (10 seconds) 300

L

ESD Electrostatic discharge protection (HBM) ±2 kV

4.1 Recommended operating conditions

Table 5. Recommended operating conditions

500 mW

°

C

°

C

Symbol Parameter Min. Typ. Max. Unit

V

I/OVL

V

I/OVCC

T

Supply voltage 1.65 – 3.6 V

L

Supply voltage 1.65 – 5.5 V

CC

Input voltage (OE output enable pin, VL power

OE

supply referred)

I/OVL voltage 0 – V

I/O

voltage 0 – V

VCC

Operating temperature -40 – 85

OP

dt/dV Input rise and fall time 0 – 1 ns/V

6/20 Doc ID 15967 Rev 1

0–3.6V

L

CC

V

°

C