ST ST10F273Z4 User Manual

16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

Features

■ High performance 16-bit CPU with DSP

functions – 31.25 ns instruction cycle time at 64 MHz

max CPU clock

– Multiply/accumulate unit (MAC) 16 x 16-bit

multiplication, 40-bit accumulator – Enhanced boolean bit manipulations – Single-cycle context switching support

■ Memory organization

– 512 Kbyte on-chip Flash memory single

voltage with erase/program controller (full

performance, 32-bit fetch) – 100K erasing/programming cycles. – Up to 16 Mbyte linear address space for

code and data (5 Mbytes with CAN or I – 2 Kbyte on-chip internal RAM (IRAM) – 34 Kbyte on-chip extension RAM (XRAM) – Pro grammable external bus configuration &

characteristics for different address ranges – 5 programmable chip-select signals – Hold-acknowledge bus arbitration support

■ Interrupt

– 8-channel peripheral event controller for

single cycle interrupt driven data transfer – 16-priority-level interrupt system with 56

sources, sampling rate down to 15.6 ns

■ Timers

– 2 multifunctional general purpose timer

units with 5 timers

■ Two 16-channel capture / compare units

■ 4-channel PWM unit + 4-channel XPWM

ST10F273Z4

PQFP144 (28 x 28 x 3.4mm)

(Plastic Quad Flat Package)

■ A/D Converter

– 24-channel 10-bit –3 µs Minimum conversion time

■ Serial channels

– 2 synch. / asynch. serial channels – 2 high-speed synchronous channels

–I

C standard interface

■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN

busses (64 or 2x32 messages, C-CAN version)

■ Fail-safe protection

– Programmable watchdog timer – Oscillator watchdog

■ On-chip bootstrap loader

■ Clock generation

– On-chip PLL and 4 to 12 MHz oscillator – Direct or prescaled clock input

■ Real-time clock and 32 kHz on-chip oscillator

■ Up to 111 general purpose I/O lines

– Individually programmable as input, output

or special function

– Programmable threshold (hysteresis)

■ Idle, power down and stand-by modes

■ Single voltage supply: 5 V ±10%.

LQFP144 (20 x 20 x 1.4mm)

(Low Profile Quad Flat Package)

Table 1. Device summary

Part Number Package

ST10F273Z4Q3 PQFP144 64 MHz 512 KB No 36 KB -40/+125

ST10F273Z4T3 LQFP144 40 MHz 512 KB No 36 KB -40/+125

January 2008 Rev 2 1/188

Max CPU

frequency

Iflash Xflash RAM Temperature range (°C)

www.st.com

Contents ST10F273Z4

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Pin data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Internal Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.2 Modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2.3 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.4 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.1 Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4.2 Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.4.3 Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4.4 Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4.5 Flash data register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.6 Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4.7 Flash data register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.4.8 Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.4.9 Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.4.10 Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.4.11 Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.5 Protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.5.1 Protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.5.2 Flash non volatile write protection I register low . . . . . . . . . . . . . . . . . . 37

5.5.3 Flash non volatile write protection I register high . . . . . . . . . . . . . . . . . . 37

5.5.4 Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . 37

5.5.5 Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . 38

5.5.6 Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . 38

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5.5.7 Access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.5.8 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.5.9 Temporary unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.6 Write operation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.7 Write operation summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 Bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.1 Selection among user-code, standard or selective bootstrap . . . . . . . . . . 44

6.2 Standard bootstrap loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.3 Alternate and selective boot mode (ABM & SBM) . . . . . . . . . . . . . . . . . . 45

6.3.1 Activation of the ABM and SBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.3.2 User mode signature integrity check . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.3.3 Selective boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

7 Central processing unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.1 Multiplier-accumulator unit (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

7.2 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.3 MAC coprocessor specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8 External bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9.1 X-Peripheral interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

9.2 Exception and error traps list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

10 Capture / compare (CAPCOM) units . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11 General purpose timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

11.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

11.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

12 PWM modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

13 Parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

13.2 I/O’s special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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13.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

13.3 Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

14 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

15 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

15.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 69

15.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

15.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

15.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 71

16 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

17 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

17.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

17.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

18 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

19 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

20 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

20.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

20.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

20.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

20.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

20.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

20.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

20.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

21 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

21.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

21.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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21.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.3 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

21.3.3 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 110

23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

24.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

24.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

24.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

24.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

24.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

24.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

24.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

24.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

24.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

24.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

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24.8.8 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

24.8.9 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

24.8.10 PLL lock / unlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

24.8.11 Main oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

24.8.12 32 kHz oscillator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

24.8.13 External clock drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

24.8.14 Memory cycle variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

24.8.15 External memory bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

24.8.16 Multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

24.8.17 Demultiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

24.8.18 CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

24.8.19 External bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

24.8.20 High-speed synchronous serial interface (SSC) timing . . . . . . . . . . . . 172

25 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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ST10F273Z4 List of tables

List of tables

Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2. Summary of IFlash address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3. Address space of the Flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. Flash modules sectorization (read operations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 5. Flash modules sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 6. Control register interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 7. Flash control register 0 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 8. Flash control register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9. Flash control register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10. Flash control register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. Banks (BxS) and sectors (BxFy) status bits meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 12. Flash data register 0 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Flash data register 0 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Flash data register 1 low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. Flash data register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. Flash address register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Flash address register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. Flash error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 19. Flash non volatile write protection register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 20. Flash non volatile protection register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 21. Flash non volatile access protection register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 22. Flash non volatile access protection register 1 low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 23. Flash non volatile access protection register 1 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 24. Summary of access protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 25. Flash write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 26. ST10F273 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 27. Standard instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 28. MAC instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 29. Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 30. X-Interrupt detailed mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 31. Trap priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 32. Compare modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 33. CAPCOM timer input frequencies, resolutions and periods at 40 MHz . . . . . . . . . . . . . . . 58

Table 34. CAPCOM timer input frequencies, resolutions and periods at 64 MHz . . . . . . . . . . . . . . . 58

Table 35. GPT1 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 59

Table 36. GPT1 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 60

Table 37. GPT2 timer input frequencies, resolutions and periods at 40 MHz. . . . . . . . . . . . . . . . . . . 61

Table 38. GPT2 timer input frequencies, resolutions and periods at 64 MHz. . . . . . . . . . . . . . . . . . . 61

Table 39. PWM unit frequencies and resolutions at 40 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 63

Table 40. PWM unit frequencies and resolutions at 64 MHz CPU clock . . . . . . . . . . . . . . . . . . . . . . 63

Table 41. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . 69 Table 42. ASC asynchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . 70 Table 43. ASC synchronous baud rates by reload value and deviation errors (fCPU = 40 MHz) . . . 70 Table 44. ASC synchronous baud rates by reload value and deviation errors (fCPU = 64 MHz) . . . 71

Table 45. Synchronous baud rate and reload values (fCPU = 40 MHz). . . . . . . . . . . . . . . . . . . . . . . 72

Table 46. Synchronous baud rate and reload values (fCPU = 64 MHz). . . . . . . . . . . . . . . . . . . . . . . 72

Table 47. WDTREL reload value (fCPU = 40 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 48. WDTREL reload value (fCPU = 64 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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List of tables ST10F273Z4

Table 49. Reset event definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 50. Reset event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 51. PORT0 latched configuration for the different reset events . . . . . . . . . . . . . . . . . . . . . . . 103

Table 52. Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 53. List of special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 54. List of XBus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 55. List of flash registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 56. IDMANUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 57. IDCHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 58. IDMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 59. IDPROG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Table 60. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 61. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 62. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 63. Product classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 64. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 65. Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 66. Flash data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 67. A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 68. A/D converter programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 69. On-chip clock generator selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 70. Internal PLL divider mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Table 71. PLL characteristics [V

= 5V ± 10%, VSS = 0V, TA = –40°C to +125°C] . . . . . . . . . . . . 151

Table 72. Main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 73. Main oscillator negative resistance (module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Table 74. 32 kHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 75. Minimum values of negative resistance (module) for 32 kHz oscillator . . . . . . . . . . . . . . 153

Table 76. External clock drive XTAL1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Table 77. Multiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Table 78. Demultiplexed bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Table 79. CLKOUT and READY

timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Table 80. External bus arbitration timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 81. SSC master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Table 82. SSC slave mode timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Table 83. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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ST10F273Z4 List of figures

List of figures

Figure 1. ST10F273 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2. Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 6. MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7. X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 8. Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 9. Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 10. Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 11. Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 75

Figure 12. Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 75

Figure 13. Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 76

Figure 14. Connection to one CAN bus with internal Parallel mode enabled . . . . . . . . . . . . . . . . . . . 76

Figure 15. Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 16. Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17. Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 18. Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 19. Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20. Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 21. Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 22. Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 23. SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 24. SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25. SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 26. SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 27. SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . 97

Figure 28. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 29. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 30. Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 31. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 100

Figure 32. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 101

Figure 33. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 34. External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 35. Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 36. Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 132

Figure 37. A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 38. A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 39. Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 40. Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 41. Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 42. Float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 43. Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 44. ST10F273 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 45. Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 46. 32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 47. External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 48. External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 158

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List of figures ST10F273Z4

Figure 49. External memory cycle: Multiplexed bus, with/without read/write delay, extended ALE. . 159 Figure 50. External memory cycle: Multiplexed bus, with/without r/w delay, normal ALE, r/w CS . . . 160 Figure 51. External memory cycle: Multiplexed bus, with/without r/w delay, extended ALE, r/w CS. 161

Figure 52. External memory cycle: Demultiplexed bus, with/without r/w delay, normal ALE . . . . . . . 164

Figure 53. Exteral memory cycle: Demultiplexed bus, with/without r/w delay, extended ALE. . . . . . 165

Figure 54. External memory cycle: Demultipl. bus, with/without r/w delay, normal ALE, r/w CS . . . . 166

Figure 55. External memory cycle: Demultiplexed bus, without r/w delay, extended ALE, r/w CS . . 167

Figure 56. CLKOUT and READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Figure 57. External bus arbitration (releasing the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 58. External bus arbitration (regaining the bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 59. SSC master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 60. SSC slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 61. 144-pin plastic quad flat package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 62. 144-pin low profile quad flat package (10x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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ST10F273Z4 Introduction

1 Introduction

The ST10F273Z4 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers.

The ST10F273Z4 combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides onchip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

ST10F273Z4 is processed in 0.18mm CMOS technology. The MCU core and the logic is supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V.

The device is upward compatible with the ST10F269 device, with the following set of differences:

● Flash control interface is now based on STMicroelectronics third generation of stand-

alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash.

● Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package

is used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin to 5.0 V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic type, typical value 10nF, maximum value 100nF).

● The AC and DC parameters are modified due to a difference in the maximum CPU

frequency.

● A new V

● EA pin assumes a new alternate functionality: it is also used to provide a dedicated

power supply (see VSTBY) to maintain biased a portion of the XRAM (16 Kbytes) when the main Power Supply of the device (V V18) is turned off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5 to 5.5 volts and a dedicated embedded low power voltage regulator is in charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real-Time Clock module when not disabled. It is allowed to exceed the upper limit up to 6 V for a very short period of time during the global life of the device and exceed the lower limit down to 4 V when RTC and 32 kHz on-chip oscillator are not used.

● A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here

SSC0, while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic SSC and the new XSSC.

● A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0,

while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the classic ASC and the new XASC.

● A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here

PWM0, while the new one is referred as XPWM or simply as PWM1). Note that some

pin replaces DC2 of ST10F269.

and consequently the internally generated

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Introduction ST10F273Z4

restrictions and functional differences due to the XBUS peculiarities are present between the classic PWM and the new XPWM.

● An I2C interface on the XBUS is added (see X-I2C or simply I2C interface).

● CLKOUT function can output either the CPU clock (like in ST10F269) or a software

programmable prescaled value of the CPU clock.

● On-chip RAM memory and FLASH size have been increased.

● PLL multiplication factors have been adapted to new frequency range.

● A/D Converter is not fully compatible versus ST10F269 (timing and programming

model). Formula for the conversion time is still valid, while the sampling phase programming model is different. Besides, additional 8 channels are available on P1L pins as alternate function: The accuracy reachable with these extra channels is reduced with respect to the standard Port5 channels.

● External Memory bus is affected by limitations on maximum speed and maximum

capacitance load: ST10F273Z4 is not able to address an external memory at 64 MHz with 0 wait states.

● XPERCON register bit mapping modified according to new peripherals implementation

(not fully compatible with ST10F269).

● Bondout chip for emulation (ST10R201) cannot achieve more than 50MHz at room

temperature (so no real-time emulation possible at maximum speed).

● Input section characteristics are different. The threshold programmability is extended to

all port pins (additional XPICON register); it is possible to select standard TTL (with up to 400mV of hysteresis) and standard CMOS (with up to 750mV of hysteresis).

● Output transition is not programmable.

● CAN module is enhanced: ST10F273Z4 implements two C-CAN modules, so the

programming model is slightly different. Besides, the possibility to map in parallel the two CAN modules is added (on P4.5/P4.6).

● On-chip main oscillator input frequency range has been reshaped, reducing it from 1 to

25 MHz down to 4 to 12 MHz. This is a low power oscillator amplifier, that allows a power consumption reduction when Real-Time Clock is running in Power down mode, using as reference the on-chip main oscillator clock. When this on-chip amplifier is used as reference for Real-Time Clock module, the Power-down consumption is dominated by the consumption of the oscillator amplifier itself.

● A second on-chip oscillator amplifier circuit (32 kHz) is implemented for low power

modes: it can be used to provide the reference to the Real-Time Clock counter (either in Power down or Stand-by mode). Pin XTAL3 and XTAL4 replace a couple of V

DD/VSS

pins of ST10F269.

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ST10F273Z4 Introduction

Figure 1. ST10F273Z4 Logic symbol

V18

VDD VSS

XTAL1 XTAL2 XTAL3 XTAL4

RSTIN

RSTOUT

VARE F

VAG ND

/ VSTBY

READY

WR / WRL

Por t 5

16-bit

NMI

ALE

ST10F273Z4

Por t 0 16-bit

Por t 1 16-bit

Por t 2 16-bit

Por t 3 15-bit

Por t 4 8-bit

Por t 6 8-bit

Por t 7 8-bit

Por t 8 8-bit

RPD

13/188

Pin data ST10F273Z4

2 Pin data

Figure 2. Pin configuration (top view)

(*)

XTAL4

XTAL3

NMI

RSTOUT

RSTIN

VSS

XTAL1

XTAL2

VDD

P1H.7 / A15 / CC27I

P1H.6 / A14 / CC26I

P1H.5 / A13 / CC25I

P1H.4 / A12 / CC24I

P1H.3 / A11

P1H.2 / A10

P1H.1 / A9

P1H.0 / A8

VSS

VDD

P1L.7 / A7 / AN23

P1L.6 / A6 / AN22

P1L.5 / A5 / AN21

P1L.4 / A4 / AN20

P1L.3 / A3 / AN19

P1L.2 / A2 / AN18

P1L.1 / A1 / AN17

P1L.0 / A0 / AN16

P0H.7 / AD15

P0H.6 / AD14

P0H.5 / AD13

P0H.4 / AD12

P0H.3 / AD11

P0H.2 / AD10

P0H.1 / AD9

VSS

VDD

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109 108

P6.0 / CS0 P6.1 / CS1 P6.2 / CS2 P6.3 / CS3

P6.4 / CS4 P6.5 / HOLD / SCLK1 P6.6 / HLDA

/ MTSR1

P6.7 / BREQ / MRST1 P8.0 / XPOUT0 / CC16IO P8.1 / XPOUT1 / CC17IO P8.2 / XPOUT2 / CC18IO P8.3 / XPOUT3 / CC19IO

P8.4 / CC20IO P8.5 / CC21IO

P8.6 / RxD1 / CC22IO

P8.7 / TxD1 / CC23IO

VDD

VSS P7.0 / POUT0 P7.1 / POUT1 P7.2 / POUT2 P7.3 / POUT3

P7.4 / CC28IO P7.5 / CC29IO P7.6 / CC30IO P7.7 / CC31IO

P5.0 / AN0 P5.1 / AN1 P5.2 / AN2 P5.3 / AN3 P5.4 / AN4 P5.5 / AN5 P5.6 / AN6 P5.7 / AN7 P5.8 / AN8 P5.9 / AN9

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

3738394041424344454647484950515253545556575859606162636465666768697071

VAREF

VAGND

P5.12 / AN12 / T6IN

P5.13 / AN13 / T5IN

P5.10 / AN10 / T6EUD

P5.11 / AN11 / T5EUD

P5.14 / AN14 / T4EUD

P5.15 / AN15 / T2EUD

VSS

VDD

P2.0 / CC0IO

P2.1 / CC1IO

ST10F273Z4

V18

VSS

P2.2 / CC2IO

P2.3 / CC3IO

P2.4 / CC4IO

P2.5 / CC5IO

P2.6 / CC6IO

P2.7 / CC7IO

P2.8 / CC8IO / EX0IN

P2.9 / CC9IO / EX1IN

P2.10 / CC10IO / EX2IN

P2.11 / CC11IO / EX3IN

P2.12 / CC12IO / EX4IN

P2.13 / CC13IO / EX5IN

P2.14 / CC14IO / EX6IN

P2.15 / CC15IO / EX7IN / T7IN

P3.0 / T0IN

P3.1 / T6OUT

P3.2 / CAPIN

P3.3 / T3OUT

P3.4 / T3EUD

P0H.0 / AD8

107

P0L.7 / AD7

106

P0L.6 / AD6

105

P0L.5 / AD5

104

P0L.4 / AD4

103

P0L.3 / AD3

102

P0L.2 / AD2

101

P0L.1 / AD1

100

P0L.0 / AD0

/ VSTBY

ALE

READY

WR/WRL

VSS

VDD

P4.7 / A23 / CAN2_TxD / SDA

P4.6 / A22 / CAN1_TxD / CAN2_TxD

P4.5 / A21 / CAN1_RxD / CAN2_RxD

P4.4 / A20 / CAN2_RxD / SCL

P4.3 / A19

P4.2 / A18

P4.1 / A17

P4.0 / A16

RPD

VSS

VDD

P3.15 / CLKOUT

P3.13 / SCLK0

P3.12 / BHE

P3.11 / RxD0

P3.10 / TxD0

P3.9 / MTSR0

P3.8 / MRST0

P3.7 / T2IN

P3.6 / T3IN

VSS

VDD

P3.5 / T4IN

/ WRH

14/188

ST10F273Z4 Pin data

Table 2. Pin description

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

1 - 8 I/O

high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 6 is selectable (TTL or CMOS). The following Port 6 pins have alternate functions:

1OP6.0CS0

Chip select 0 output

... ... ... ... ...

P6.0 - P6.7

5OP6.4CS4 Chip select 4 output

IP6.5HOLD

External master hold request input

I/O SCLK1 SSC1: master clock output / slave clock input

O P6.6 HLDA

Hold acknowledge output

I/O MTSR1 SSC1: master-transmitter / slave-receiver O/I

OP6.7 BREQ Bus request output

I/O MRST1 SSC1: master-receiver / slave-transmitter I/O

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

9-16 I/O

high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or CMOS). The following Port 8 pins have alternate functions:

I/O P8.0 CC16IO CAPCOM2: CC16 capture input / compare output

O XPWM0 PWM1: channel 0 output

... ... ... ... ...

P8.0 - P8.7

I/O P8.3 CC19IO CAPCOM2: CC19 capture input / compare output

O XPWM0 PWM1: channel 3 output

13 I/O P8.4 CC20IO CAPCOM2: CC20 capture input / compare output

14 I/O P8.5 CC21IO CAPCOM2: CC21 capture input / compare output

I/O P8.6 CC22IO CAPCOM2: CC22 capture input / compare output

I/O RxD1 ASC1: Data input (Asynchronous) or I/O (Synchronous)

I/O P8.7 CC23IO CAPCOM2: CC23 capture input / compare output

O TxD1 ASC1: Clock / Data output (Asynchronous/Synchronous)

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Pin data ST10F273Z4

Table 2. Pin description (continued)

Symbol Pin Type Function

8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to

P7.0 - P7.7

P5.0 - P5.9

P5.10 - P5.15

19-26 I/O

19 O P7.0 POUT0 PWM0: channel 0 output

... ... ... ... ...

22 O P7.3 POUT3 PWM0: channel 3 output

23 I/O P7.4 CC28IO CAPCOM2: CC28 capture input / compare output

... ... ... ... ...

26 I/O P7.7 CC31IO CAPCOM2: CC31 capture input / compare output

27-36 39-44

39 I P5.10 T6EUD GPT2: timer T6 external up/down control input

40 I P5.11 T5EUD GPT2: timer T5 external up/down control input

41 I P5.12 T6IN GPT2: timer T6 count input

42 I P5.13 T5IN GPT2: timer T5 count input

43 I P5.14 T4EUD GPT1: timer T4 external up/down control input

high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or CMOS). The following Port 7 pins have alternate functions:

16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals

ANx (Analog input channel x), or they are timer inputs. The input threshold of

Port 5 is selectable (TTL or CMOS). The following Port 5 pins have alternate functions:

P2.0 - P2.7

P2.8 - P2.15

44 I P5.15 T2EUD GPT1: timer T2 external up/down control input

16-bit bidirectional I/O port, bit-wise programmable for input or output via

47-54 57-64

47 I/O P2.0 CC0IO CAPCOM: CC0 capture input/compare output

... ... ... ... ...

54 I/O P2.7 CC7IO CAPCOM: CC7 capture input/compare output

57 I/O P2.8 CC8IO CAPCOM: CC8 capture input/compare output

... ... ... ... ...

64 I/O P2.15 CC15IO CAPCOM: CC15 capture input/compare output

direction bit. Programming an I/O pin as input forces the corresponding output

I/O

driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or CMOS). The following Port 2 pins have alternate functions:

I EX0IN Fast external interrupt 0 input

I EX7IN Fast external interrupt 7 input

I T7IN CAPCOM2: timer T7 count input

16/188

ST10F273Z4 Pin data

Table 2. Pin description (continued)

Symbol Pin Type Function

15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or 65-70, 73-80,

65 I P3.0 T0IN CAPCOM1: timer T0 count input

66 O P3.1 T6OUT GPT2: timer T6 toggle latch output

67 I P3.2 CAPIN GPT2: register CAPREL capture input

68 O P3.3 T3OUT GPT1: timer T3 toggle latch output

69 I P3.4 T3EUD GPT1: timer T3 external up/down control input

I/O

output via direction bit. Programming an I/O pin as input forces the

I/O

corresponding output driver to high impedance state. Port 3 outputs can be

I/O

configured as push-pull or open drain drivers. The input threshold of Port 3 is

selectable (TTL or CMOS). The following Port 3 pins have alternate functions:

P3.0 - P3.5

P3.6 - P3.13,

P3.15

70 I P3.5 T4IN GPT1; timer T4 input for count/gate/reload/capture

73 I P3.6 T3IN GPT1: timer T3 count/gate input

74 I P3.7 T2IN GPT1: timer T2 input for count/gate/reload / capture

75 I/O P3.8 MRST0 SSC0: master-receiver/slave-transmitter I/O

76 I/O P3.9 MTSR0 SSC0: master-transmitter/slave-receiver O/I

77 O P3.10 TxD0 ASC0: clock / data output (asynchronous/synchronous)

78 I/O P3.11 RxD0 ASC0: data input (asynchronous) or I/O (synchronous)

79 O P3.12 BHE

WRH

80 I/O P3.13 SCLK0 SSC0: master clock output / slave clock input

81 O P3.15 CLKOUT

External memory high byte enable signal

External memory high byte write strobe

System clock output (programmable divider on CPU clock)

17/188

Pin data ST10F273Z4

Table 2. Pin description (continued)

Symbol Pin Type Function

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or

output via direction bit. Programming an I/O pin as input forces the

corresponding output driver to high impedance state. The input threshold is

85-92 I/O

85 O P4.0 A16 Segment address line

86 O P4.1 A17 Segment address line

87 O P4.2 A18 Segment address line

88 O P4.3 A19 Segment address line

89 O P4.4 A20 Segment address line

P4.0 –P4.7

90 O P4.5 A21 Segment address line

91 O P4.6 A22 Segment address line

selectable (TTL or CMOS). Port 4.4, 4.5, 4.6 and 4.7 outputs can be configured

as push-pull or open drain drivers.

In case of an external bus configuration, Port 4 can be used to output the

segment address lines:

I CAN2_RxD CAN2: receive data input

I/O SCL

I2C Interface: serial clock

I CAN1_RxD CAN1: receive data input

I CAN2_RxD CAN2: receive data input

92 O P4.7 A23 Most significant segment address line

RD 95 O

/WRL 96 O

READY/

READY

97 I

ALE 98 O

O CAN1_TxD CAN1: transmit data output

O CAN2_TxD CAN2: transmit data output

I/O SDA

External memory read strobe. RD

I2C Interface: serial data

is activated for every external instruction or

data read access.

External memory write strobe. In WR

external data write access. In WRL

-mode this pin is activated for every

mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection.

Ready input. The active level is programmable. When the ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of waitstate cycles until the pin returns to the selected active level.

Address latch enable output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines.

18/188

ST10F273Z4 Pin data

Table 2. Pin description (continued)

Symbol Pin Type Function

External access enable pin. A low level applied to this pin during and after Reset forces the ST10F273Z4 to

start the program from the external memory space. A high level forces ST10F273Z4 to start in the internal memory space. This pin is also used (when

EA / V

STBY

P0L.0 -P0L.7,

P0H.0

P0H.1 - P0H.7

99 I

100-107,

108,

111-117

Stand-by mode is entered, that is ST10F273Z4 under reset and main V turned off) to bias the 32 kHz oscillator amplifier circuit and to provide a reference voltage for the low-power embedded voltage regulator which generates the internal 1.8V supply for the RTC module (when not disabled) and to retain data inside the Stand-by portion of the XRAM (16Kbyte). It can range from 4.5 to 5.5V (6V for a reduced amount of time during the device life, 4.0V when RTC and 32 kHz on-chip oscillator amplifier are turned off). In running mode, this pin can be tied low during reset without affecting 32 kHz oscillator, RTC and XRAM activities, since the presence of a stable V guarantees the proper biasing of all those modules.

Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold of Port 0 is selectable (TTL or CMOS). In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes

Data path width 8-bit 16-bi

I/O

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

P1L.0 - P1L.7

P1H.0 - P1H.7

Multiplexed bus modes

Data path width 8-bit 16-bi

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 – A15 AD8 - AD15

Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. PORT1 is used as the 16bit address bus (A) in demultiplexed bus modes: if at least BUSCONx is

118-125 128-135

configured such the demultiplexed mode is selected, the pis of PORT1 are not available for general purpose I/O function. The input threshold of Port 1 is

I/O

selectable (TTL or CMOS). The pins of P1L also serve as the additional (up to 8) analog input channels for

the A/D converter, where P1L.x equals ANy (Analog input channel y, where y = x + 16). This additional function have higher priority on demultiplexed bus function. The following PORT1 pins have alternate functions:

132 I P1H.4 CC24IO CAPCOM2: CC24 capture input

133 I P1H.5 CC25IO CAPCOM2: CC25 capture input

134 I P1H.6 CC26IO CAPCOM2: CC26 capture input

135 I P1H.7 CC27IO CAPCOM2: CC27 capture input

19/188

Pin data ST10F273Z4

Table 2. Pin description (continued)

Symbol Pin Type Function

XTAL1 138 I XTAL1 Main oscillator amplifier circuit and/or external clock input.

XTAL2 137 O XTAL2 Main oscillator amplifier circuit output.

To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed.

XTAL3 143 I XTAL3 32 kHz oscillator amplifier circuit input

XTAL4 144 O XTAL4 32 kHz oscillator amplifier circuit output

When 32 kHz oscillator amplifier is not used, to avoid spurious consumption, XTAL3 shall be tied to ground while XTAL4 shall be left open. Besides, bit OFF32 in RTCCON register shall be set. 32 kHz oscillator can only be driven by an external crystal, and not by a different clock source.

Reset Input with CMOS Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F273Z4. An

RSTIN

RSTOUT

NMI

140 I

141 O

142 I

internal pull-up resistor permits power-on reset using only a capacitor connected

. In bidirectional reset mode (enabled by setting bit BDRSTEN in

to V

SYSCON register), the RSTIN

line is pulled low for the duration of the internal

reset sequence.

Internal Reset Indication Output. This pin is driven to a low level during hardware, software or watchdog timer reset.

RSTOUT

remains low until the EINIT

(end of initialization) instruction is executed.

Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F273Z4 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI

should be pulled high externally.

AREF

AGND

RPD 84 -

37 - A/D converter reference voltage and analog supply

38 - A/D converter reference and analog ground

Timing pin for the return from interruptible power down mode and synchronous / asynchronous reset selection.

17, 46, 72,82,93, 109, 126,

136

Digital supply voltage = + 5V during normal operation, idle and power down

modes. It can be turned off when Stand-by RAM mode is selected.

18,45, 55,71,

83,94,

- Digital ground

110, 127,

139

56 -

1.8V decoupling pin: a decoupling capacitor (typical value of 10nF, max 100nF) must be connected between this pin and nearest V

20/188

pin.

ST10F273Z4 Functional description

3 Functional description

The architecture of the ST10F273Z4 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F273Z4.

Figure 3. Block diagram

IFlash

512K

CPU-core and MAC unit

IRAM

32K (16K

XCAN1

XRAM

(PEC)

XRAM

STBY)

XRTC

XI2C

Por t 0

Por t 1Por t 4

Por t 6

81615 8 8

16 16

XCAN2

External bus

XPWM

XASC

XSSC

controller

Por t 5

10-bit ADC

Interrupt controller

ASC0

GPT1 / GPT2

BRG BRG

Port 3 Port 7 Por t 8

PEC

SSC0

PWM

CAPCOM2

Watchdog

Oscillator

32 kHz

oscillator

PLL

5V-1.8V

voltage

regulator

CAPCOM1

Por t 2

21/188

Memory organization ST10F273Z4

4 Memory organization

The memory space of the ST10F273Z4 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16 Mbytes. The entire memory space can be accessed Byte wise or Word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable.

IFlash: 512 Kbytes of on-chip Flash memory. It is divided in 10 blocks (B0F0...B0F9) of the Bank 0 and two blocks of Bank 1 (B1F0, B1F1): read-while-write operations inside the same Bank are not allowed. When Bootstrap mode is selected, the Test-Flash Block B0TF (8 Kbyte) appears at address 00’0000h: refer to Chapter 5: Internal Flash memory on

page 25 for more details on memory mapping in boot mode. The summary of address range

for IFlash is the following:

Table 3. Summary of IFlash address range

Blocks User mode Size

B0TF Not visible 8 K

B0F0 00’0000h - 00’1FFFh 8 K

B0F1 00’2000h - 00’3FFFh 8 K

B0F2 00’4000h - 00’5FFFh 8 K

B0F3 00’6000h - 00’7FFFh 8 K

B0F4 01’8000h - 01’FFFFh 32K

B0F5 02’0000h - 02’FFFFh 64K

B0F6 03’0000h - 03’FFFFh 64K

B0F7 04’0000h - 04’FFFFh 64K

B0F8 05’0000h - 05’FFFFh 64K

B0F9 06’0000h - 06’FFFFh 64K

B1F0 07’0000h - 07’FFFFh 64K

B1F1 08’0000h - 08’FFFFh 64K

IRAM: 2 Kbytes of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 Wordwide (R0 to R15) and / or Bytewide (RL0, RH0, …, RL7, RH7) general purpose registers group.

XRAM: 32 K + 2 Kbytes of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code.

The XRAM is divided into two areas, the first 2 Kbytes named XRAM1 and the second 32 Kbytes named XRAM2, connected to the internal XBUS and are accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read/write delay (31.25ns access at 64 MHz CPU clock). Byte and Word accesses are allowed.

The XRAM1 address range is 00’E000h - 00’E7FFh if XPEN (bit 2 of SYSCON register), and XRAM1EN (bit 2 of XPERCON register) are set. If XRAM1EN or XPEN is cleared, then any access in the address range 00’E000h - 00’E7FFh will be directed to external memory

22/188

ST10F273Z4 Memory organization

interface, using the BUSCONx register corresponding to address matching ADDRSELx register.

The XRAM2 address range is F’0000h-F’7FFFFh if XPEN (bit 2 of SYSCON register), and XRAM2EN (bit 3 of XPERCON register) are set. If bit XPEN is cleared, then any access in the address range programmed for XRAM2 will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register.

The lower portion of the XRAM2 (address range F’0000h-F’3FFFFh) represents also the Stand-by RAM, which can be maintained biased through EA V

is turned off.

/ VSTBY pin when main supply

As the XRAM appears like external memory, it cannot be used as system stack or as register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable.

SFR/ESFR: 1024 bytes (2 x 512 bytes) of address space is reserved for the special function register areas. SFRs are Wordwide registers which are used to control and to monitor the function of the different on-chip units.

CAN1: Address range 00’EF00h - 00’EFFFh is reserved for the CAN1 Module access. The CAN1 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN1EN bit 0 of the XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64 MHz CPU clock. No tri-state wait states are used.

CAN2: Address range 00’EE00h - 00’EEFFh is reserved for the CAN2 Module access. The CAN2 is enabled by setting XPEN bit 2 of the SYSCON register and by setting CAN2EN bit 1 of the new XPERCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two wait states give an access time of 62.5ns at 64 MHz CPU clock. No tri-state wait states are used.

If one or the two CAN modules are used, Port 4 cannot be programmed to output all eight segment address lines. Thus, only four segment address lines can be used, reducing the external memory space to 5 Mbytes (1 Mbyte per CS line).

RTC: Address range 00’ED00h - 00’EDFFh is reserved for the RTC Module access. The RTC is enabled by setting XPEN bit 2 of the SYSCON register and bit 4 of the XPERCON register. Accesses to the RTC Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used.

PWM1: Address range 00’EC00h - 00’ECFFh is reserved for the PWM1 Module access. The PWM1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 6 of the XPERCON register. Accesses to the PWM1 Module use demultiplexed addresses and a 16bit data bus (only word accesses are possible). Two waitstates give an access time of

62.5ns at 64MHz CPU clock. No tristate waitstate is used. Only word access is allowed.

ASC1: Address range 00’E900h - 00’E9FFh is reserved for the ASC1 Module access. The ASC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 7 of the XPERCON register. Accesses to the ASC1 Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is used.

SSC1: Address range 00’E800h - 00’E8FFh is reserved for the SSC1 Module access. The SSC1 is enabled by setting XPEN bit 2 of the SYSCON register and bit 8 of the XPERCON register. Accesses to the SSC1 Module use demultiplexed addresses and a 16-bit data bus

23/188

Memory organization ST10F273Z4

(only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used.

I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register. Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used.

X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON register and bit 10 of the XPERCON register. Accesses to this additional features use demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two waitstates give an access time of 62.5ns at 64 MHz CPU clock. No tristate waitstate is used. The following set of features are provided:

● CLKOUT programmable divider

● XBUS interrupt management registers

● ADC multiplexing on P1L register

● Port1L digital disable register for extra ADC channels

● CAN2 multiplexing on P4.5/P4.6

● CAN1-2 main clock prescaler

● Main voltage regulator disable for Power-down mode

● TTL / CMOS threshold selection for Port0, Port1 and Port5.

In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 Mbytes of external memory can be connected to the microcontroller.

Visibility of XBUS peripherals

In order to keep the ST10F273Z4 compatible with the ST10F168 / ST10F269, the XBUS peripherals can be selected to be visible on the external address / data bus. Different bits for X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the global enabling with XPEN bit in SYSCON register, the corresponding address space, port pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and not available. Refer to Chapter 23: Register set on page 111.

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5 Internal Flash memory

5.1 Overview

The on-chip Flash is composed by one matrix module divided in two banks that can be read and modified indipendently one of the other: one bank can be read while another bank is under modification. Bank 0 is 384 Kbytes wide, Bank 1 is 128 Kbytes wide.

This module is on ST10 Internal bus, so it is called IFlash.

Figure 4. Flash structure

IFlash (Module I)

Bank 1: 128 Kbyte

program memory

Bank 0: 384 Kbyte

program memory

8 Kbyte test-Flash

I-BUS interface

The programming operations of the flash are managed by an embedded Flash Program/Erase Controller (FPEC). The High Voltages needed for Program/Erase operations are internally generated.

The Data bus is 32-bit wide for fetch accesses to IFlash, while it is 16-bit wide for read accesses to IFlash. Read/write accesses to IFlash Control Registers area are 16-bit wide.

5.2 Functional description

Control Section

HV and Ref.

generator

Program/erase

controller

Flash control

registers

X-BUS interface

5.2.1 Structure

Following table shows the Address space reserved to the Flash module.

Table 4. Address space of the Flash module

IFlash sectors 0x00 0000 to 0x08 FFFF 512 Kbytes

Registers and Flash internal reserved area 0x0E 0000 to 0x0E FFFF 64 Kbytes

Description Addresses Size

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5.2.2 Modules structure

The IFlash module is composed by 2 banks: (Bank 0) contains 384 Kbytes of Program Memory divided in 10 sectors (B0F0...B0F7), Bank 0 contains also a reserved sector named Test-Flash. Bank 1 contains 128 Kbytes of Program Memory or Parameter divided in two sectors (B1F0, B1F1, 64 Kbytes each). Addresses from 0x0E 0000 to 0x0E FFFF are reserved for the Control Register Interface and other internal service memory space used by the Flash Program/Erase controller.

The following tables show the memory mapping of the Flash when it is accessed in read mode (Table 5: Flash modules sectorization (read operations)) and when accessed in write or erase mode (Table 6: Flash modules sectorization): Note that with this second mapping, the first four banks are remapped into code segment 1 (same as obtained setting bit ROMS1 in SYSCON register).

Table 5. Flash modules sectorization (read operations)

Bank Description Addresses Size ST10 Bus size

Bank 0 Flash 0 (B0F0) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0000 2000 - 0x0000 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0000 4000 - 0x0000 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0000 6000 - 0x0000 7FFF 8 KB

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

32-bit (I-BUS)

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

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Table 6. Flash modules sectorization

Bank Description Addresses Size ST10 bus size

Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB

Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB

Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB

Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB

Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB

1. Write operations or with ROMS1=’1’ or bootstrap mode

Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB

Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB

Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB

Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB

Bank 0 Flash 8 (B0F8) 0x0005 0000 - 0x0005 FFFF 64 KB

Bank 0 Flash 9 (B0F9) 0x0006 0000 - 0x0006 FFFF 64 KB

Bank 1 Flash 0 (B1F0) 0x0007 0000 - 0x0007 FFFF 64 KB

Bank 1 Flash 1 (B1F1) 0x0008 0000 - 0x0008 FFFF 64 KB

(1)

32-bit (I-BUS)

The table above refers to the configuration when bit ROMS1 of SYSCON register is set.

When Bootstrap mode is entered:

● Test-Flash is seen and available for code fetches (address 00’0000h)

● User I-Flash is only available for read and write accesses

● Write accesses must be made with addresses starting in segment 1 from 01'0000h,

whatever ROMS1 bit in SYSCON value

● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value.

In Bootstrap mode, by default ROMS1 = 0, so the first 32 KBytes of IFlash are mapped in segment 0.

Example:

In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed.

Next Ta bl e 7 shows the Control Register interface composition: This set of registers can be addressed by the CPU.

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Table 7. Control register interface

Name Description Addresses Size

FCR1-0 Flash control registers 1-0 0x000E 0000 - 0x000E 0007 8 byte

FDR1-0 Flash data registers 1-0 0x000E 0008 - 0x000E 000F 8 byte

FAR Flash address registers 0x000E 0010 - 0x000E 0013 4 byte

FER Flash error register 0x000E 0014 - 0x000E 0015 2 byte

FNVWPIR

FNVAPR0

FNVAPR1

Flash non volatile protection I register

Flash Non volatile access protection register 0

Flash non volatile access protection register 1

0x000E DFB4 - 0x000E DFB7 4 byte

0x000E DFB8 - 0x000E DFB9 2 byte

0x000E DFBC - 0x000E DFBF 4 byte

(XBUS)

5.2.3 Low power mode

The Flash module is automatically switched off executing PWRDN instruction. The consumption is drastically reduced, but exiting this state can require a long time (t

Recovery time from Power down mode for the Flash modules is anyway shorter than the main oscillator start-up time. To avoid any problem in restarting to fetch code from the Flash, it is important to size properly the external circuit on RPD pin.

Note: PWRDN instruction must not be executed while a Flash program/erase operation is in

progress.

Bus size

16-bit

5.3 Write operation

The Flash module have one single register interface mapped in the memory space 0x0E 0000 to 0x0E 0015. All the operations are enabled through four 16-bit control registers: Flash Control Register 1-0 High/Low (FCR1H/L-FCR0H/L). Eight other 16-bit registers are used to store Flash Address and Data for Program operations (FARH/L and FDR1H/LFDR0H/L) and Write Operation Error flags (FERH/L). All registers are accessible with 8 and 16-bit instructions (since operates in 16-bit mode when in read/ write).

Before accessing the Flash registers used for program/erasing operations, bit 5 (XFLASHEN) in XPERCON register shall be set.

The two banks have their own dedicated sense amplifiers, so that one bank can be read while the other is written.

During a Flash write operation, any attempt to read the bank under modification will output invalid data (software trap 009Bh). This means that the Flash bank is not fetchable when a programming operation is active: The write operation commands must be executed from another bank or from the other memory (internal RAM or external memory).

During a Write operation, when bit LOCK of FCR0 is set, it is forbidden to write into the Flash Control Registers.

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Power supply drop

If, during a write operation, the internal low voltage supply drops below a certain internal voltage threshold, any write operation running is suddenly interrupted and the module is reset to Read mode. At following Power-on, the interrupted Flash write operation must be repeated.

5.4 Register description

5.4.1 Flash control register 0 low

The Flash Control Register 0 Low (FCR0L), together with the Flash Control Register 0 High (FCR0H), is used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap mode only.

FCR0L (0x0E 0000) FCR Reset Value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved BSY1 BSY0 LOCK res. res. res. res.

RRR

Table 8. Flash control register 0 low

Bit Function

Bank 0:1 Busy (IFlash) These bits indicate that a write operation is running on Bank 0 or Bank 1(IFlash). They are

automatically set when bit WMS is set. Setting Protection operation sets bits BSYx (since

BSY(1:0)

LOCK

protection registers are in this Block). When this bits are set, every read access to the corresponding bank will output invalid data (software trap 009Bh), while every write access to the bank will be ignored. At the end of the write operation or during a Program or Erase Suspend these bits are automatically reset and the bank returns to read mode. After a Program or Erase Resume these bits is automatically set again.

Flash registers access locked When this bit is set, it means that the access to the Flash Control Registers FCR0H/-FCR1H/L,

FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read access to the registers will output invalid data (software trap 009Bh) and any write access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set. This is the only bit the user can always access to detect the status of the Flash: once it is found low, the rest of FCR0L and all the other Flash registers are accessible by the user as well. Note that FER content can be read when LOCK is low, but its content is updated only when also BSYx bits are reset.

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5.4.2 Flash control register 0 high

The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low (FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user has no access in write mode to the Test-Flash (B0TF). Besides, Test-Flash block is seen by the user in Bootstrap mode only.

FCR0H (0x0E 0002) FCR Reset Value: 0000h

15 14 13 12 11109 8 7 6543210

WMS SUSP WPG DWPG SER reserved SPR SMOD reserved

RW RW RW RW RW RW RW

Table 9. Flash control register 0 high

Bit Function

SMOD

SPR

SER

DWPG

This must be set before every Write Operation except for writing in the Flash Non Volatile Protection Registers, SMOD is automatically reset at the end of the Write Operation.

Set protection

This bit must be set to select the Set Protection operation. The Set Protection operation allows to program 0s in place of 1s in the Flash Non Volatile Protection Registers. The Flash Address in which to program must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L before starting the execution by setting bit WMS. A sequence error is flagged by bit SEQER of FER if the address written in FARH/L is not in the range 0x0EDFB00x0EDFBF. SPR bit is automatically reset at the end of the Set Protection operation.

Sector erase This bit must be set to select the Sector Erase operation in the Flash modules. The Sector Erase

operation allows to erase all the Flash locations to value 0xFF. From 1 to all the sectors of the same bank (excluded Test-Flash for Bank B0) can be selected to be erased through bits BxFy of FCR1H/L registers before starting the execution by setting bit WMS. It is not necessary to preprogram the sectors to 0x00, because this is done automatically. SER bit is automatically reset at the end of the Sector Erase operation.

Double word program

This bit must be set to select the Double Word (64 bits) Program operation in the Flash module. The Double Word Program operation allows to program 0s in place of 1s. The Flash Address in which to program (aligned with even words) must be written in the FARH/L registers, while the 2 Flash Data to be programmed must be written in the FDR0H/L registers (even word) and FDR1H/L registers (odd word) before starting the execution by setting bit WMS. DWPG bit is automatically reset at the end of the Double Word Program operation.

Word program This bit must be set to select the Word (32 bits) Program operation in the Flash module. The Word

WPG

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Program operation allows to program 0s in place of 1s. The Flash Address to be programmed must be written in the FARH/L registers, while the Flash Data to be programmed must be written in the FDR0H/L registers before starting the execution by setting bit WMS. WPG bit is automatically reset at the end of the Word Program operation.

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