The SRI2K is a contactless memory, powered by an externally transmitted radio wave. It
contains a 2048-bit user EEPROM. The memory is organized as 64 blocks of 32 bits. The
SRI2K is accessed via the 13.56 MHz carrier. Incoming data are demodulated and decoded
from the received amplitude shift keying (ASK) modulation signal and outgoing data are
generated by load variation using bit phase shift keying (BPSK) coding of a 847 kHz
subcarrier. The received ASK wave is 10% modulated. The data transfer rate between the
SRI2K and the reader is 106 kbit/s in both reception and emission modes.
The SRI2K follows the ISO 14443 part 2 type B recommendation for the radio-frequency
power and signal interface.
Figure 1.Logic diagram
SRI2K
AC1
AC0
AI15575
2 Kbit
User
EEPROM
Power
Supply
Regulator
ASK
Demodulator
BPSK
Load
Modulator
The SRI2K is specifically designed for short range applications that need re-usable
products. The SRI2K includes an anticollision mechanism that allows it to detect and select
tags present at the same time within range of the reader. The anticollision is based on a
probabilistic scanning method using slot markers. Using the STMicroelectronics single chip
coupler, CRX14, it is easy to design a reader and build a contactless system.
Table 1.Signal names
Signal namesDescription
AC1Antenna coil
AC0Antenna coil
Doc ID 15779 Rev 37/45
Signal descriptionSRI2K
AI09055
AC1AC0
The SRI2K contactless EEPROM can be randomly read and written in block mode (each
block containing 32 bits). The instruction set includes the following nine commands:
●Read_block
●Write_block
●Initiate
●Pcall16
●Slot_marker
●Select
●Completion
●Reset_to_inventory
●Get_UID
The SRI2K memory is organized in three areas, as described in Figure 3. The first area is a
resettable OTP (one time programmable) area in which bits can only be switched from 1 to
0. Using a special command, it is possible to erase all bits of this area to 1. The second area
provides two 32-bit binary counters which can only be decremented from FFFF FFFFh to
0000 0000h, and gives a capacity of 4,294,967,296 units per counter. The last area is the
EEPROM memory. It is accessible by block of 32 bits and includes an auto-erase cycle
during each Write_block command.
Figure 2.Die floor plan
2 Signal description
2.1 AC1, AC0
The pads for the Antenna Coil. AC1 and AC0 must be directly bonded to the antenna.
8/45Doc ID 15779 Rev 3
SRI2KData transfer
DATA BIT TO TRANSMIT
TO THE
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE READER
Transfer time for one data bit is 1/106 kHz
SRI2K
AI15576
ai07664
1 ETU
Start
"0"
Stop
"1"
MSbLSbInformation Byte
b0b1b2b3b4b5b6b7b8b9
3 Data transfer
3.1 Input data transfer from the reader to the SRI2K (request
frame)
The reader must generate a 13.56 MHz sinusoidal carrier frequency at its antenna, with
enough energy to “remote-power” the memory. The energy received at the SRI2K’s antenna
is transformed into a supply voltage by a regulator, and into data bits by the ASK
demodulator. For the SRI2K to decode correctly the information it receives, the reader must
10% amplitude-modulate the 13.56 MHz wave before sending it to the SRI2K. This is
represented in Figure 3. The data transfer rate is 106 Kbits/s.
Figure 3.10% ASK modulation of the received wave
3.1.1 Character transmission format for request frame
The SRI2K transmits and receives data bytes as 10-bit characters, with the least significant
bit (b
) transmitted first, as shown in Figure 4. Each bit duration, an ETU (elementary time
0
unit), is equal to 9.44 µs (1/106 kHz).
These characters, framed by a start of frame (SOF) and an end of frame (EOF), are put
together to form a command frame as shown in Figure 10. A frame includes an SOF,
commands, addresses, data, a CRC and an EOF as defined in the ISO 14443-3 Type B
Standard. If an error is detected during data transfer, the SRI2K does not execute the
command, but it does not generate an error frame.
Figure 4.SRI2K request frame character format
Doc ID 15779 Rev 39/45
Data transferSRI2K
ai07665
ETU
b0b1b2b3b4b5b6b7b8b9b10b11
000000000011
ai07666
ETU
b0b1b2b3b4b5b6b7b8b9
0000000000
Table 2.Bit description
BitDescriptionValue
b
0
b1 to b
b
9
Start bit used to synchronize the transmissionb0 = 0
Information byte (command, address or data)
8
Stop bit used to indicate the end of a characterb9 = 1
3.1.2 Request start of frame
The SOF described in Figure 5 is composed of:
●one falling edge,
●followed by 10 ETUs at logic-0,
●followed by a single rising edge,
●followed by at least 2 ETUs (and at most 3) at logic-1.
Figure 5.Request start of frame
The information byte is sent with the
least significant bit first
3.1.3 Request end of frame
The EOF shown in Figure 6 is composed of:
●one falling edge,
●followed by 10 ETUs at logic-0,
●followed by a single rising edge.
Figure 6.Request end of frame
10/45Doc ID 15779 Rev 3
SRI2KData transfer
Or
ai15580
Data Bit to be Transmitted
to the Reader
847kHz BPSK Modulation
Generated by the SRI2K
BPSK Modulation at 847kHz
During a One-bit Data Transfer Time (1/106kHz)
ai07665
ETU
b0b1b2b3b4b5b6b7b8b9b10b11
000000000011
3.2 Output data transfer from the SRI2K to the reader (answer
frame)
The data bits issued by the SRI2K use backscattering. Backscattering is obtained by
modifying the SRI2K current consumption at the antenna (load modulation). The load
modulation causes a variation at the reader antenna by inductive coupling. With appropriate
detector circuitry, the reader is able to pick up information from the SRI2K. To improve loadmodulation detection, data is transmitted using a BPSK encoded, 847 kHz subcarrier
frequency ƒ
Figure 7.Wave transmitted using BPSK subcarrier modulation
as shown in Figure 7, and as specified in the ISO 14443-2 Type B Standard.
s
3.2.1 Character transmission format for answer frame
3.2.2 Answer start of frame
The character format is the same as for input data transfer (Figure 4). The transmitted
frames are made up of an SOF, data, a CRC and an EOF (Figure 10). As with an input data
transfer, if an error occurs, the reader does not issue an error code to the SRI2K, but it
should be able to detect it and manage the situation. The data transfer rate is
106 Kbits/second.
The SOF described in Figure 8 is composed of:
●followed by 10 ETUs at logic-0
●followed by 2 ETUs at logic-1
Figure 8.Answer start of frame
Doc ID 15779 Rev 311/45
Data transferSRI2K
ai07665
ETU
b0b1b2b3b4b5b6b7b8b9b10b11
000000000011
3.2.3 Answer end of frame
The EOF shown in Figure 9 is composed of:
●followed by 10 ETUs at logic-0,
●followed by 2 ETUs at logic-1.
Figure 9.Answer end of frame
3.3 Transmission frame
Between the request data transfer and the answer data transfer, all ASK and BPSK
modulations are suspended for a minimum time of t
to switch from Transmission to Reception mode. It is repeated after each frame. After t
13.5 6MHz carrier frequency is modulated by the SRI2K at 847 kHz for a period of t
128/ƒ
to allow the reader to synchronize. After t1, the first phase transition generated by the
S
SRI2K forms the start bit (‘0’) of the answer SOF. After the falling edge of the answer EOF,
the reader waits a minimum time, t
, before sending a new request frame to the SRI2K.
2
= 128/ƒS. This delay allows the reader
0
, the
0
=
1
Figure 10. Example of a complete transmission frame
Sent by the
Reader
Sent by the
SRI2K
SOF
12 bits
at 106kb/s
Data CRC CRC
Cmd
10 bits
10 bits10 bits10 bits10 bits
t
DR
Input data transfer using ASKOutput data transfer using BPSK
EOF
t
128/fs
0
fs=847.5kHz
Sync
t
128/fs
SOF
SOF
Data CRC CRC
1
12 bits
10 bits 10 bits 10 bits
EOF
12 bits
t
2
AI15577
12/45Doc ID 15779 Rev 3
SRI2KData transfer
CRC 16 (8 bits)CRC 16 (8 bits)
LSbitMSbit LSbitMSbit
LSByteMSByte
ai07667
3.4 CRC
The 16-bit CRC used by the SRI2K is generated in compliance with the ISO14443 Type B
recommendation. For further information, please see Appendix A. The initial register
contents are all 1s: FFFFh.
The two-byte CRC is present in every request and in every answer frame, before the EOF.
The CRC is calculated on all the bytes between SOF (not included) and the CRC field.
Upon reception of a request from a reader, the SRI2K verifies that the CRC value is valid. If
it is invalid, the SRI2K discards the frame and does not answer the reader.
Upon reception of an answer from the SRI2K, the reader should verify the validity of the
CRC. In case of error, the actions to be taken are the reader designer’s responsibility.
The CRC is transmitted with the least significant byte first and each byte is transmitted with
the least significant bit first.
Figure 11. CRC transmission rules
Doc ID 15779 Rev 313/45
Memory mappingSRI2K
4 Memory mapping
The SRI2K is organized as 64 blocks of 32 bits as shown in Tab l e 3 . All blocks are
accessible by the Read_block command. Depending on the write access, they can be
updated by the Write_block command. A Write_block updates all the 32 bits of the block.
Table 3.SRI2K memory mapping
Block
Addr
MSB32-bit blockLSB
b
31
b
24 b23
b16 b
15
b8 b
7
b
032 bits Boolean area
132 bits Boolean area
232 bits Boolean area
332 bits Boolean area
432 bits Boolean area
532 bits binary counter
632 bits binary counter
7User area
8User area
9User area
10User area
11User area
12User area
13User area
14User area
15User area
16User area
Description
0
Resettable OTP
bits
Count down
counter
Lockable
EEPROM
63User area
255OTP_Lock_RegST Reserved
UID0
64 bits UID areaROM
UID1
14/45Doc ID 15779 Rev 3
Fixed Chip_ID
(Option)
EEPROM...User area
System OTP
bits
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