ST M29W641DH, M29W641DL, M29W641DU User Manual

查询M29W641DH供应商

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V
–V
–V

■ ACCESS TIME: 70, 90, 100 and 120ns

■ PROGRAMMING TIME

– 10 µs typical
– Double Word Program option

■ 128 UNIFORM, 32-KWord MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Program and Erase algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programm ing

■ WRITE PROTECT OPTIONS

– M29W641DH: WP

Highest Address Block

– M29W641DL: WP

Lowest Address Block

– M29W641DU: No Write Protection

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

■ EXTENDED MEMORY BLOCK

– Extra block used as security block or to store

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Device Code M29W641D: 22C7h

2.7V to 3.6V Core Power Supply

CC =

= 1.8V to 3.6V for Input/Output

CCQ

=12 V for Fast Program (optional)

PP

Erase Suspend

Pin for Write Protection of

Pin for Write Protection of

additional information

M29W641DH, M29W641DL

M29W641DU

64 Mbit (4Mb x16, Uniform Block)

3V Supply Fl ash Me m ory

PRODUCT PREVIEW

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA63 (ZA)

7 x 11mm

April 2003

This is preliminary information on a new product now in development. Details are subject to change without notice.

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M29W641DH, M29W641DL, M29W641DU

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFGBA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ15 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

V

(VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PP

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

CC

V

Supply Voltage (1.8V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CCQ

V

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SS

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Suspend Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M29W641DH, M29W641DL, M29W641DU

Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Exit Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Program, Erase Times and Program, Erase Enduranc e Cyc les . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Operating and AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25

Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25
Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view pac kage outline 26
Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mechanical Data . . 26

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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M29W641DH, M29W641DL, M29W641DU

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Query Structure Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 20. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 21. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 22. Primary Algorithm-Specific Extende d Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Customer Lockable Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 24. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6

Table 25. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Programmer Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 26. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

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SUMMARY DESCRIPTION

The M29W641D is a 64 M bit (4Mb x16 ) non-vola­tile memory that can be read, erased and repro­grammed. These operations can be performed

CCQ

sup-

CC

supply

PP

using a single, low voltage, 2.7V to 3.6V V
ply for the circuitry and a 1.8V to 3.6V V
for the Input/Output pins. An optional 12 V V
power supply is provided to speed up customer
programming.

On power-up the memory defaults to its Read
mode where it can be read in the same way as a
ROM or EPROM.

The highest address blo ck of the M 29W641DH or
the lowest address block of th e M29W641DL c an
be protected from accidental programming or era­sure using the WP
M29W641DU does not feature the WP

pin (if WP = VIL). The

pin.

Each block can be erased indep endently so it is
possible to preserve valid dat a while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and E rase com­mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of prog ramming or erasing
the memory by taking care of all of the special op­erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi­fied. The command set required to control the
memory is consistent with JEDEC standards.

The M29W641D has an extra block, the Extended
Block, (of 32 KWords) that can be accessed using
a dedicated command. The Extended Block can
be protected and so is useful for storing security
information. However the protec tion i s not re vers­ible, once protected the protection cannot be un­done.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple conne ction to most m icropro­cessors, often without additional logic.

The memory is offered in a 48-pin TSOP package
(M29W641DL and M29W641DH) or in a 63- ball TF­BGA package (M29W64 1DU). All de vices a re del iv­ered with all the bits erased (set to 1) .

M29W641DH, M29W641DL, M29W641DU

Figure 2. Logic Diagram

CCQ

V

PP

16

DQ0-DQ15

AI06697b

V

V

CC

22

A0-A21

W

E

G
RB
RP

WP

M29W641D

V

SS

Table 1. Signal Names

A0-A21 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-

DQ15
E
G
W

RP

RB

Data Inputs/Outputs

Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect

(M29W641DH and M29W641DL only)
Ready/Busy Output (M29W641DU

only)

WP

V

CC

V

CCQ

V

PP

V

SS

Write Protect
Supply Voltage
Supply Voltage for Input/Output
Supply Voltage for Fast Program

(optional)
Ground

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M29W641DH, M29W641DL, M29W641DU

Figure 3. TSOP Connections

A15
A14
A13
A12
A11

1

48

A16
V

CCQ

V

SS

DQ15
DQ7

A10 DQ14

37
36

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

A21
A20

RP

V

PP

WP
A19
A18
A17

A9
A8

W

A7
A6
A5
A4
A3
A2
A1

12

M29W641D

13

24 25

AI06698

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M29W641DH, M29W641DL, M29W641DU

Figure 4. TFGBA Connections (Top view through package)

654321

A

B

NC

NC

(1)

(1)

C

D

E

F

G

H

NC

A3

A4

A2

A1

A0

(1)

A7

A17

A6

RB

V

PP

A18

A5 A20

DQ0

E

DQ8

DQ2

DQ10

W

RP

A21

A19

DQ5

DQ12

A9

A8

A10

A11

DQ7

DQ14

NC

NC

V

(1)

(1)

A13

A12

A14

A15

A16

CCQ

NC

NC

87

(1)

(1)

J

K

L

NC

M

NC

G

DQ9

V

SS

(1)

NC

(1)

NC

DQ1

(1)

(1)

DQ11

DQ3

V

CC

DQ4

Note: 1. Bal l s ar e shorted to get her via the substrate but not connec ted to the die.

DQ13

DQ6

DQ15

V

SS

NC

NC

NC

NC

(1)

(1)

AI06879

(1)

(1)

7/42

M29W641DH, M29W641DL, M29W641DU

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and T able 1, Sign al
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A21). The Address Inputs
select the cells i n the memory array to a ccess dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the Program/Erase Con­troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.

Data Inputs/Outputs (DQ8-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.

Chip Enable (E

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

IH

Output Enable (G

trols the Bus Read operation of the memory.

Write Enable (W

the Bus Write operation of the memory’s Com­mand Interf a c e .

Write Protect (W

available in the M29W641DH and M29W641DL
only. I t provid es a hard ware metho d of pro t ecting
the highest address block for the M29W641DH
and the lowest address block for the
M29W64 1DL. The Write Protect pin must not be
left floating or unconnected.

When Write Protect is Low, V
tects either the highest or low est address block;
Program and Erase operations in this block are ig­nored while Write Protect is Low.

When Write Pr otect
verts to the previous protection status for this
block. Program and Erase operations can now
modify the data in t his block unless the block is
protected using Block Protection.

Ready/Busy Output (RB

is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-

). The Chip Enable, E, activates

, all other pins are ignored.

). The Output Enable, G, con-

). The Write Enable, W, controls

P). The Write Protect pin is

, the memory pro-

IL

is High, VIH, the memory re-

). The Ready/Busy pin

. Ready/Busy is high-im-

OL

comes high-impedance. See Tabl e 13 and Figure
12, Reset/Block Temporary Unprotect AC Charac­teristics.

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Reset/Block Temporary Unprotect (RP

). The

Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that hav e b een
protected.

Note that if Write Protect

(WP) is at VIL, then one
of the two outermost blocks will remain p rotected
even if RP is at V

.

ID

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

. After Reset/Block Temporary Unprotect

t

PLPX

goes High, V

, the memory will be ready for Bus

IH

Read and Bus Write operations after t
t

, whichever occurs las t. See Table 13 and

RHEL

, for at least

IL

PHEL

or

Figure 12, Reset/Block T emporary Unprotect AC
Characteristics, for more details.

Holding RP

at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t

V

.

PHPHH

(VPP). When the VPP pin is raised to V

PP

to VID must be slower than

IH

PPH

the memory automatically enters the Unlock By­pass mode. When the pin is returned to V

IH

or V
normal operation resumes. During Unlock Bypass
Program operations the memory draws I

PP

from
the pin to supply the programming circuits. See the
description of the Unlock Bypass comm and in the
Command Interface section. The transitions from
V

to VPP and from VPP to VIH must be slower

IH

than t
Never raise the pin to V

, see Figure 13.

VHVPP

from any mode except

PP

Read mode, otherwise the memory may be left in
an indeterminate state.

V

Supply Voltage (2.7V to 3.6V). VCC pro-

CC

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the L ockout Voltage,

. This prevents Bus Write operations from ac-

V

LKO

cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

V

Supply Voltage (1.8V to 3.6V). V

CCQ

CCQ

pro­vides the power supply to the I/O pins and enables
all Outputs to be powered indepen dently of V

CC

IL

.

8/42

M29W641DH, M29W641DL, M29W641DU

V

can be tied to VCC or can use a separate

CCQ

supply.

V

Ground. VSS is the reference for all voltage

SS

measurements. The device f eatu res two V

SS

pins
which must be both connected to the system
ground.

Note: Each device in a system should have
V

CC, VCCQ

and VPP decoupled from V

SS

with a

Table 2. Bus Operations

Operation E G W

Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer

Code

Read Device Code

Extended Memory
Block Verify Code

Note: X = VIL or VIH.

V
V

V

V

V

V

V

IL

V

IL

V

IH

V

IL

V

IL

V

IL

V

IL

IH

IH

Cell Address Data Output

IH

V

Command Address Data Input

IL

V

X Hi-Z

IH

X X X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

V

IL

IL

IL

IH

Others V
A0 = VIH, A1 = VIL, A9 = VID,

V

IH

Others V

A0 = VIH, A1 = VIH, A6 = VIL,

V

IH

A9 = V

0.1µF ceramic capacitor close to the pin for
current surge protection (high frequency, in­herently low inductance ca pacitors should b e
as close as possible to the device). See Figure
8, AC Measurement Load Circuit. The PCB
trace widths should be sufficient to carry the
required V

program and erase curr ents. S ee

PP

Table 9, DC Characteristics.

Address Inputs

A0-A21

or V

IL

IH

or V

IL

IH

, Others VIL or V

ID

IH

Data Inputs/Outputs

DQ15-DQ0

0020h

22C7h

98h (factory locked, WP protects

highest address block)

18h (not factory locked, WP

protects highest address
block)

88h (factory locked, WP

lowest block)

08h (not factory locked, WP

protects lowest block)

protects

9/42

M29W641DH, M29W641DL, M29W641DU

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Wri te, Out­put Disable, Standby and Automatic Standby. See
Table 2, Bus Operations, for a summary. Typically
glitches of less than 5ns on Chip Enabl e o r Write
Enable are ignored by t he mem ory and do not a f­fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low sig nal, V
and Output Enable and keeping Write Enable
High, V

. The Data Inputs/Outputs will output the

IH

value, see Figure 9, Read Mode AC W aveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desire d address on t he Ad­dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En­able must remain High, V

IH

Write operation. See Figure 10 and Figure 11,
Write AC Waveforms, and Table 11 and Table 12,
Write AC Characteristics, for details of the timing
requirements.

Output Disa bl e . The Data Inputs/Outputs are in
the high impedance s tate when Output Enable is
High, V

.

IH

Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped­ance state. To reduce the S upply Current to the
Standby Supply Current, I

CC2

, to Chip Enable

IL

, during the whole Bus

, the

IH

, Chip Enable should

be held within V

± 0.2V. For the Standby current

CC

level see Table 9, DC Characteristics.
During program or erase operations the memory

will continue to use the Program/Erase Supply
Current, I

, for Program or Erase operations un-

CC3

til the operation completes.
Automatic Standby. If CMOS levels (V

± 0.2V)

CC

are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced to the Standby Supply Current, I

CC2

. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protec tion. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require V

to be applied to some pins.

ID

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying t he signals
listed in Table 2, Bus Operations.

Block Protect and Chip Unprotect.

Groups of
blocks can be protected against accidental Pro­gram or Erase. The whole chip can be unprotected
to allow the data inside the blocks to be changed.

Write Protect
the outermost blocks. When Write Protect
at V

one of the two outer mos t blo cks is protect-

IL

(WP) can be used to protect one of

(WP) is

ed and r emai ns prote cte d r egar dle ss o f th e Bloc k
Protection Status or the Reset/Block Temporary
Unprotect pin statu s. For the M 29W641D H, it is
the highest addressed block that can be protect­ed. For th e M29W 641DL, it i s t he l owest.

Block Protect and Chip Unprote ct operations are
described in Appendix D.

10/42

COMMAND INTERFACE

All Bus Write operations t o the me mory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Read mode. The long command sequences
are imposed to maximize data security.

See Table 3 for a summary of the commands.

Read/Reset Command

The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.

The Read/Reset command can be issued, be­tween Bus Write cycles before the start of a pro­gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the timeout of a Block erase operation then

the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.

Auto Select Command

The Auto Select command is used to read the
Manufacturer Code, the Device Code , the Block
Protection Status and the Extended Memory Block
Verify Code. Three consecutive B us Write opera­tions are required to iss ue the Auto Select com­mand. Once the Auto Select command is issued
the memory remains in Auto Select mode until a
Read/Reset command is issued. Read CFI Query
and Read/Reset comma nds are ac cept ed i n Aut o
Select mode, all other commands are ignored.

In Auto Select mode the Manufac turer Code can
be read using a Bus Read operation with A0 = V
and A1 = VIL. The other address bits may be set to
either V

or VIH. The Manufacturer Code f or ST-

IL

Microelectronics is 0020h.
The Device Code can be read using a B us Read

operation with A0 = V
address bits may be set to e ither V

and A1 = VIL. The other

IH

or VIH. The

IL

Device Code for the M29W641D is 22C7h.
The Bl ock Prot ection S tatus of each block can be

read using a Bus Read operation with A0 = V
A1 = V

, and A 12 -A 21 spec ify i n g t he address of

IH

IL

the bl ock. The oth er addr ess bit s may b e set t o ei­ther V

or VIH. If t h e ad dr ess ed b loc k is pro tec te d

IL

then 01h is output on Data Inputs/Outputs DQ0­DQ7, otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-

M29W641DH, M29W641DL, M29W641DU

vice is in the Read Array mode, or when the device
is in Autose lec ted mode .

One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is­sued subsequent Bus Read ope rations read from
the Common Flash Interface Memory Area.

The Read/Reset command m ust be issued to re­turn the device to the previous mode (the Read Ar­ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect­ed mode.

See Appendix B, Table 18 to Table 23 for details
on the information contained in the Common Flash
Interface (CFI) memory area.

Program Command

The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper­ations, the final write operation latches the ad­dress and data, and starts the Program/Erase
Controller.

If the address falls in a pro tected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operat ion the memo ry will ig­nore all commands. I t is n ot poss ible t o iss ue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op­erations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on the S tatus Register for more
details.

After the program operation has completed the
memory will return to the Read mode, unle ss an

IL

error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

Note that the Program command cannot change a
bit set at ’0’ bac k to ’1’. One of the E rase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

Fast Program Commands

,

There is a Fast Program command available to im­prove the programming throughput, by writing sev­eral adjacent words or bytes in parallel: the Double
Word Program command.

Double Word Program Command. Th e D oub l e
Word Program command is used to write a p age
of two adjacent words in parallel. Th e two words
must differ only for the address A0.

Three bus write cycles are necessary to issue the
Double Word Program command.

11/42

M29W641DH, M29W641DL, M29W641DU

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts
the Program/Erase Controller.

Only one bank can be programmed at any one
time. The other b ank must be in Read mode or
Erase Suspend.

Programming should not be attempted when V
is not at V

PPH

.

PP

After programming has started, Bus Read opera­tions in the Bank being programmed output the
Status Register content, while Bus Read opera­tions to the other B ank outpu t the cont ents of t he
memory ar ray.

After the program operation has completed the
memory will return to the Read mode, unle ss an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg­ister. A Read/Reset command must be issued to
reset the error condition and return t o Read mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Typical Program times are given in Tab le 4, Pro­gram, Erase Times and Program, Erase Endur­ance Cycles.

Unlock Bypass Command

The Unlock Bypass command is used in conjunc­tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When th e cycle time to the
device is long (as with some EPROM program­mers) considerable time saving can be m ade by
using these commands. Three Bus Write opera­tions are required to issue the Unlock Bypass
command.

Once the Unlock Bypas s command has bee n is­sued the memory enters Unlock Bypass mode.
When in this mode the memory can be read as if
in Read mode.

When V

is applied to the VPP pin the memory

PPH

automatically enters the Unlock Bypass mode and
the Unlock Bypass Program command can be is­sued immediately.

Unlock Bypass Program Command

The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two B us Write
operations, the final write operation latches the ad-

dress and data, and starts the Program/Erase
Controller.

A Program operation initiated by issuing the Un­lock Bypass Program command is identical to a
Program operation initiated by issuing the Pro­gram command. I t cannot be abo rted and a Bus
Read operation will output the Status Register.
See the Program Comma nd paragrap h f or further
details.

Unlock Bypass Reset Command

The Unlock Bypass Rese t command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.

Chip Erase Command

The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations a re re­quired to issue the Chip Erase Command and start
the Program/Erase Controller.

If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protect e d th e Chip Erase op erat i on ap­pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the erase operation the memory will ignore
all commands, including the Erase Suspen d com­mand. It is not possible to i ssue any c ommand t o
abort the operation. Typical chip erase tim es are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec­tion on the Status Register for more details.

After the Chip Erase operation has completed t he
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un­protected blocks of the memory to ’1’. All previous
data is lost.

Block Erase Command

The Block Erase com mand can be used to erase
a list of one or more blocks. Six Bus Write opera­tions are required to select the first block in the li st.
Each additional block in the list can be selected by
repeating the sixth Bus Write operation using the
address of the additional block. The B lock Erase
operation starts the Program/Erase Controller
about 50µs after the last Bus Write operation.
Once the Pr ogram /Erase Co ntroller st arts it is not
possible to select any more blocks. Each addition­al block must therefore be selected within 50µs of

12/42

M29W641DH, M29W641DL, M29W641DU

the lowest address block. The 50µs timer restarts
when an additional block is selected. The Status
Register can be read after the sixth Bus Write op­eration. See the Status Register section for details
on how to identify if th e Program /Erase Controller
has started the Block Erase operation.

If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are p rotected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un­changed. No error condition is given when protect­ed blocks are ignored.

During the Block Erase operation the me mory wi ll
ignore all commands except the Erase Susp end
command. Typical b lock era se tim es are g iven in
Table 4. All Bus Read operations during the Block
Erase ope ra tion will outp ut the S t atus R e gister on
the Data Inputs/Outputs. See the section on the
Status Register for more details.

After the Block Erase operation has completed the
memory will return to the Read Mode, unle ss an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.

Erase Suspend Command

The Erase Suspend Command may be used to
temporarily suspend a B lock Eras e operation and
return the memory to Read mode. T he comm and
requires one Bus Write operation.

The Program/Erase Controller will sus pend within
the Erase Suspend Latency time of the Erase Sus­pend Command being issued. Once the Program/
Erase Controller has stopped the mem ory will be
set to Read mode and the E ras e wi ll be s uspend­ed. If the Erase Suspend command is issued dur­ing the period when the memory is waiting for an
additional block (before the Program/Er ase Con­troller starts) then the Erase is suspended immedi­ately and will start immediately when the Erase
Resume Command is issued. It is not possibl e to
select any further blocks to erase after the Erase
Resume.

During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended

block then the Program comm and is ignored and
the data remains unchanged. The Status Register
is not read and no error condi tion is given. Read­ing from blocks that are being erased will output
the Status Register.

It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands du ring
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac­cepte d.

Erase Resume Command

The Erase Resume command must be used to re­start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspe nded and resumed mo re t han
once.

Enter Extended Block Command

The device has an extra 32 KWord block (Extend­ed Block) that can only be accessed using the En­ter Extended Block command. Three Bus write
cycles are required to issue the Exte nded Block
command. Once the command has been issued
the device enters Extended B lock mo de where all
Bus Read or Write operations to the Boot Block
addresses access the Extended Block. The Ex­tended Block (with the same address as the Boot
Blocks) cannot be erased, and can be t reated as
one-time programmable (OTP) memory. In Ex­tended Block mode the Boot Blocks are not acces­sible.

To exit from the Extended Block mode the Exit Ex­tended Block command must be issued.

The Extended Block can be protected, however
once protected the protection cannot be undone.

Exit Extended Block Com m a n d

The Exit Extended Block command is used to exit
from the Extended Block mod e and ret urn the de­vice to Read mode. Four Bus Write operations are
required to issue the command.

Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-

dental Program or E rase. The whole chip can be
unprotected to allow the data i nside the blocks to
be changed.

Block Protect and Chip Unprote ct operations are
described in Appendix D.

13/42