Datasheet M29W641DL, M29W641DH, M29W641D Datasheet (SGS Thomson Microelectronics)

1/42

PRODUCT PREVIEW

April 2003

This is preliminary information on a new product now in development. Details are subject to change without notice.

M29W641DH, M29W641DL

M29W641DU

64 Mbit (4Mb x16, Uniform Block)

3V Supply F l ash Me m ory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

CC =

2.7V to 3.6V Core Power Supply

–V

CCQ

= 1.8V to 3.6V for Input/Output

–V

PP

=12 V for Fast Program (optional)

■ ACCESS TIME: 70, 90, 100 and 120ns

■ PROGRAMMING TIME

– 10 µs typica l
– Double Word Program option

■ 128 UNIFORM, 32-KWord MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Program and Erase algorithms

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Progra mming

■ WRITE PROTECT OPTIONS

– M29W641DH: WP

Pin for Write Protection of

Highest Address Block

– M29W641DL: WP

Pin for Write Protection of

Lowest Address Block

– M29W64 1DU: No Write Protection

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

■ EXTENDED MEMORY BLOCK

– Extra block used as security block or to store

additional information

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Device Code M29W641D: 22C7h

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA63 (ZA)

7 x 11mm

M29W641DH, M29W641DL, M29W641DU

2/42

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFGBA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Inputs/Outputs (DQ8-DQ15 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

V

PP

(VPP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

CC

Supply Voltage (2.7V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

CCQ

Supply Voltage (1.8V to 3.6V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Erase Suspend Comma nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3/42

M29W641DH, M29W641DL, M29W641DU

Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Exit Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Program, Erase Times and Program, Erase E ndurance Cy cles . . . . . . . . . . . . . . . . . . . . 14

STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5

Table 5. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Table 7. Operating and AC Measurement Condition s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9

Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25

Table 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25
Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Bottom view packag e outline26
Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Package Mech anical Data . . 26

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

APPENDIX A. BLOCK ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

M29W641DH, M29W641DL, M29W641DU

4/42

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 18. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 19. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 20. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 21. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 22. Primary Algorithm-Spe cific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4

APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Customer Lockable Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 24. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 25. Programmer Technique Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Programmer Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. In-System Equipment Group Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 26. Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5/42

M29W641DH, M29W641DL, M29W641DU

SUMMARY DESCRIPTION

The M29W641D is a 64 M bit (4Mb x16 ) non-v ola­tile memory that can be read, erased and repro­grammed. These operations can be performed
using a single, low voltage, 2.7V to 3.6V V

CC

sup-

ply for the circuitry and a 1.8V to 3.6V V

CCQ

supply

for the Input/Output pins. An optional 12 V V

PP

power supply is provided to speed up customer
programming.

On power-up the memory defaults to its Read
mode where it can be read in the same way as a
ROM or EPROM.

The highest address blo ck of t he M 29W6 41DH or
the lowest address block of the M29W641 DL can
be protected from accidental programming or era­sure using the WP

pin (if WP = VIL). The

M29W641DU doe s not feature the WP

pin.

Each block can be erase d independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the me mory. Program an d Erase com­mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or e rasing
the memory by taking care of all of the special op­erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi­fied. The command set required to control the
memory is consistent with JEDEC standards.

The M29W641D has an extra block, the Extended
Block, (of 32 KWords) that can be accessed using
a dedicated command. The Extended Block can
be protected and s o is useful for storing security
information. However the prot ection i s not revers­ible, once protected the protection cannot be un­done.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple connection to most micropro­cessors, often without additional logic.

The memory is offered in a 48-pin TSOP package
(M29W641DL and M29W641DH) or i n a 63-ball TF­BGA pack age (M29W64 1DU). All de vices a re del iv­ered with all the bits e ras ed (set to 1).

Figure 2. L o gi c D iagram

Table 1. Signal Names

A0-A21 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-

DQ15

Data Inputs/Outputs

E

Chip Enable

G

Output Enable

W

Write Enable

RP

Reset/Block Temporary Unprotect
(M29W641DH and M29W641DL only)

RB

Ready/Busy Output (M29W641DU
only)

WP

Write Protect

V

CC

Supply Voltage

V

CCQ

Supply Voltage for Input/Output

V

PP

Supply Voltage for Fast Program
(optional)

V

SS

Ground

AI06697b

22

A0-A21

W

DQ0-DQ15

V

CC

M29W641D

E

V

SS

16

G

RP

V

PP

WP

V

CCQ

RB

M29W641DH, M29W641DL, M29W641DU

6/42

Figure 3. TSOP C on ne cti ons

DQ3

DQ9

DQ2

A6

DQ0

W

A3

A19

DQ6

A8

A9

DQ13

A17

A10 DQ14

A2

DQ12

DQ10

DQ15

V

CC

DQ4

DQ5

A7

DQ7

WP

V

PP

M29W641D

12

1

13

24 25

36

37

48

DQ8

A20

A21

A1

A18

A4

A5

DQ1

DQ11

G

A12

A13

A16

A11

V

CCQ

A15
A14

V

SS

E
A0

RP

V

SS

AI06698

7/42

M29W641DH, M29W641DL, M29W641DU

Figure 4. TFGBA Connections (Top view through package)

Note: 1. Bal l s are shorte d to gether via the substrat e but not connec te d to the die.

654321

V

SS

A15

A14

A12

A13

DQ3

DQ11

DQ10

A18

V

PP

RB

DQ1

DQ9

DQ8

DQ0

A6

A17

A7

G

E

A0

A4

A3

DQ2

DQ6

DQ13

DQ14

A10

A8

A9

DQ4

V

CC

DQ12

DQ5

A19

A21

RP

W

A11

DQ7

A1

A2

V

SS

A5 A20

A16

C

B

A

E

D

F

G

H

DQ15

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

NC

(1)

J

K

L

M

87

NC

(1)

NC

(1)

NC

(1)

NC

(1)

AI06879

V

CCQ

M29W641DH, M29W641DL, M29W641DU

8/42

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and T able 1, Signal
Names, for a brief overview of the signals connect­ed to this device.

Address Inputs (A0-A21). The Address Inputs
select the cell s in the memory arra y to access dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the Program/Erase Con­troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.

Data Inputs/Outputs (DQ8-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

IH

, all other pins are ignored.

Output Enable (G

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Com­mand Interface.

Write Protect (W

P). The Write Protect pin is

available in the M29W641DH and M29W641DL
only. I t provid es a hard war e metho d of pro tecting
the highest address block for the M29W641DH
and the lowest address block for the
M29W 641DL. The Write Protect pin must not be
left floating or unconnected.

When Write Protect is Low, V

IL

, the memory pro­tects either the highest or lowest address block;
Program and Erase operations in this block are ig­nored while Write Protect is Low.

When Write P rotect

is High, VIH, the memory re­verts to the previous protection status for this
block. Program and Erase operations can now
modify the data in this block unless the block is
protected using Block Protection.

Ready/Busy Output (RB

). The Ready/Busy pin

is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V

OL

. Ready/Busy is high-im­pedance during Read mode, Auto Select mode
and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-

comes high-impedanc e. See Tabl e 13 a nd Fi gure
12, Reset/Block Temporary Unprotect AC Charac­teristics.

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Reset/Block Temporary Unprotect (RP

). The

Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.

Note that if Write Protect

(WP) is at VIL, then one
of the two ou termost blocks will remain p rotected
even if RP is at V

ID

.

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V

IL

, for at least

t

PLPX

. After Reset/Block Temporary Unprotect

goes High, V

IH

, the memory will be ready for Bus

Read and Bus Write operations after t

PHEL

or

t

RHEL

, whichever occurs last. See Table 13 and
Figure 12, Reset/Block T emporary Unprotect AC
Characteristics, for more details.

Holding RP

at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V

IH

to VID must be slower than

t

PHPHH

.

V

PP

(VPP). When the VPP pin is raised to V

PPH

the memory automatically enters the Unlock By­pass mode. When the pin is returned to V

IH

or V

IL

normal operation resumes. During Unlock Bypass
Program operations the memory draws I

PP

from
the pin to supply the programming circuits. See the
description of the Unlock Bypas s c ommand in the
Command Interface section. The transitions from
V

IH

to VPP and from VPP to VIH must be slower

than t

VHVPP

, see Figure 13.

Never raise the pin to V

PP

from any mode except
Read mode, otherwise the memory may be left in
an indeterminate state.

V

CC

Supply Voltage (2.7V to 3.6V). VCC pro-

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V

CC

Supply Voltage is less than the L ockout Voltage,
V

LKO

. This prevents Bus Write operations from ac­cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

V

CCQ

Supply Voltage (1.8V to 3.6V). V

CCQ

pro­vides the power supply to the I/O pins and enables
all Outputs to be powered i ndependently of V

CC

.

9/42

M29W641DH, M29W641DL, M29W641DU

V

CCQ

can be tied to VCC or can use a separate

supply.

V

SS

Ground. VSS is the reference for all voltage

measurements. The device f eatures two V

SS

pins
which must be both connected to the system
ground.

Note: Each device in a system should have
V

CC, VCCQ

and VPP decoupled from V

SS

with a

0.1µF ceramic capacitor close to the pin for
current surge protection (high frequency, in­herently low inductan ce capacitors should b e
as close as possible to the device). See Figure
8, AC Measurement Load Circuit. The PCB
trace widths should be sufficient to carry the
required V

PP

program and erase currents. See

Table 9, DC Characteristics.

Table 2. Bus Operations

Note: X = VIL or VIH.

Operation E G W

Address Inputs

A0-A21

Data Inputs/Outputs

DQ15-DQ0

Bus Read

V

IL

V

IL

V

IH

Cell Address Data Output

Bus Write

V

IL

V

IH

V

IL

Command Address Data Input

Output Disable X

V

IH

V

IH

X Hi-Z

Standby

V

IH

X X X Hi-Z

Read Manufacturer
Code

V

IL

V

IL

V

IH

A0 = VIL, A1 = VIL, A9 = VID,
Others V

IL

or V

IH

0020h

Read Device Code

V

IL

V

IL

V

IH

A0 = VIH, A1 = VIL, A9 = VID,
Others V

IL

or V

IH

22C7h

Extended Memory
Block Verify Code

V

IL

V

IL

V

IH

A0 = VIH, A1 = VIH, A6 = VIL,
A9 = V

ID

, Others VIL or V

IH

98h (factory locked, WP protects

highest address block)

18h (not factory locked, WP

protects highest address
block)

88h (factory locked, WP

protects

lowest block)

08h (not factory locked, WP

protects lowest block)

M29W641DH, M29W641DL, M29W641DU

10/42

BUS OPERATIONS

There are five standard bus operations that control
the device. These are B us Read, Bus Wri te, Out­put Disable, Standby and Automatic Standby. See
Table 2, Bus Operations, for a summary. Typically
glitches of less t han 5ns on Chip E nable o r Write
Enable are ignored by the memory and do not a f­fect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low signal, V

IL

, to Chip Enable
and Output Enable and keeping Write Enable
High, V

IH

. The Data Inputs/Outputs will outp ut the
value, see Figure 9 , Read Mode AC Waveforms,
and Table 10, Read AC Characteristics, for details
of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting th e desired address o n the Ad­dress Inputs. The Address Input s are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs a re latc hed by the Com ­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En­able must remain High, V

IH

, during the whole Bus
Write operation. See Figure 10 and Figure 11,
Write AC Waveforms, and Table 11 and Table 12,
Write AC Characteristics, for details of the timing
requirements.

Output Disable. T he Data Inputs/Outputs are in
the high impedanc e state when Out put Enable is
High, V

IH

.

Standby. When Chip Enable is High, V

IH

, the
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped­ance state. To reduce t he Supply Current to the
Standby Supply Current, I

CC2

, Chip Enable should

be held within V

CC

± 0.2V. For the Standby current

level see Table 9, DC Characteristics.
During program or erase operations the memory

will continue to use the Program/Erase Supply
Current, I

CC3

, for Program or Erase operations un-

til the operation completes.
Automatic Standby. If CMOS levels (V

CC

± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced to the Standby Supply Current, I

CC2

. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require V

ID

to be applied to some pins.

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by app lying the signals
listed in Table 2, Bus Operations.

Block Protect and Chip Unprotect.

Groups of
blocks can be protected against accidental Pro­gram or Erase. The whole chip can be unprotected
to allow the data inside the blocks to be changed.

Write Protect

(WP) can be used to protect one of

the outermost blocks. When Write Protect

(WP) is

at V

IL

one of the two outer m os t blocks i s prot e ct­ed and r emai ns prot ect ed r eg ardle s s of the Bl ock
Protection Status or the Reset/Block Temporary
Unprotect pin stat us. For th e M29W641D H, it is
the highest addressed block that can be protect­ed. For the M29 W641DL, i t i s the lowest.

Block Protect and Chip Un protect operations are
described in Appendix D.

11/42

M29W641DH, M29W641DL, M29W641DU

COMMAND INTERFACE

All Bus Write operations to the memory are in ter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Read mode. The long command sequences
are imposed to maximize data security.

See Table 3 for a summary of the commands.

Read/Reset Command

The Read/Reset command returns the memory to
its Read mode where it behaves like a ROM or
EPROM. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.

The Read/Reset command can be issued, be­tween Bus Write cycles before the start of a pro­gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the timeout of a Block erase operation then

the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.

Auto Select Command

The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. Three consecut ive Bus W rite opera­tions are required to issue the Auto Select com­mand. Once the Auto Select command is issued
the memory remains in Auto S elect mode until a
Read/Reset command is issued. Read CFI Query
and Read/Reset com ma nds are accepted in Aut o
Select mode, all other commands are ignored.

In Auto Select mode the Manuf acturer Code can
be read using a Bus Read operation with A0 = V

IL

and A1 = VIL. The other address bits may be set to
either V

IL

or VIH. The Manufacturer Co de for ST-

Microelectronics is 0020h.
The Device Code can be read using a Bus Read

operation with A0 = V

IH

and A1 = VIL. The other

address bits may be set to e ither V

IL

or VIH. The

Device Code for the M29W641D is 22C7h.
The B l ock Protecti on Sta tus of each block can be

read using a Bus Read operation with A0 = V

IL

,

A1 = V

IH

, and A 12-A21 sp ecifyin g t h e addres s of
the b lock. T he oth er addr ess bi ts may b e set t o ei­ther V

IL

or VIH. If th e addr ess ed bloc k is p rot ecte d
then 01h is output on Data Inputs/Outputs DQ0­DQ7, otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-

vice is in the Read Array mode, or when the device
is in Autos ele c t e d mo de.

One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is­sued subsequent Bus Read ope rations read from
the Common Flash Interface Memory Area.

The Read/Reset comm and must be issued to re­turn the device to the previous mode (the Read Ar­ray mode or Autoselected mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Autoselect­ed mode.

See Appendix B, Ta ble 18 to Table 23 for details
on the information contained in the Common Flash
Interface (CFI) memory area.

Program Command

The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper­ations, the final write operation latches the ad­dress and data, and starts the Program/Erase
Controller.

If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operat ion the me mory will ig­nore all commands. I t is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 4. Bus Read op­erations during the program o peration will output
the Status Register on the Data Inputs/Outputs.
See the section on t he Status Register for more
details.

After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

Fast Program Commands

There is a Fast Program command available to im­prove the programming throughput, by writing sev­eral adjacent words or bytes in parallel: the Double
Word Program command.

Double Word Program Command. The Doub l e
Word Program comm and is used to write a page
of two adjacent words in paral lel. The two words
must differ only for the address A0.

Three bus write cycles are necessary to issue the
Double Word Program command.

M29W641DH, M29W641DL, M29W641DU

12/42

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts
the Program/Erase Controller.

Only one bank can be programmed at any one
time. The other b ank must be in Read mode or
Erase Suspend.

Programming should not be attempted when V

PP

is not at V

PPH

.

After programming has started, Bus Read opera­tions in the Bank being programmed output the
Status Register content, while Bus Read opera­tions to the oth er Bank o utput the c ontents of t he
memory a r ra y.

After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg­ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.

Note that the Fast Program commands cannot

change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Typical Program time s are given in Tab le 4, Pro­gram, Erase Times and Program, Erase Endur­ance Cycles.

Unlock Bypass Command

The Unlock Bypass command is used in conjunc­tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. Whe n the cycle time to the
device is long (as with some EPROM program­mers) considerable time saving can be made by
using these commands. Three Bus Write opera­tions are required to issue the Unlock Bypass
command.

Once the Unlock By pass command has been is­sued the memory enters Unlock Bypass mode.
When in this mode the memory can be read as if
in Read mode.

When V

PPH

is applied to the VPP pin the memory
automatically enters the Unlock Bypass mode and
the Unlock Bypass Program command can be is­sued immediately.

Unlock Bypass Program Command

The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires t wo Bus Write
operations, the final write operation latches the ad-

dress and data, and starts the Program/Erase
Controller.

A Program operation initiated by issuing the Un­lock Bypass Program command is identical to a
Program operation initiated by issuing the Pro­gram command. It cannot be aborted and a B us
Read operation will output the Status Register.
See the Program Comma nd paragraph for further
details.

Unlock Bypass Reset Command

The Unlock Bypass R eset com m and c an b e us ed
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.

Chip Erase Command

The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations a re re­quired to issue the Chip Erase Command and start
the Program/Erase Controller.

If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operat i on ap­pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the erase operation the memory will ignore
all commands, including the Erase Suspen d com­mand. It is not possible t o issue any comm and to
abort the operation. Typical chip erase t imes are
given in Table 4. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec­tion on the Status Register for more details.

After the Chip Erase operation has com pleted the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un­protected blocks of the memory to ’1’. All previous
data is lost.

Block Erase Command

The Block Erase c ommand can be used to erase
a list of one or more blocks. Six Bus Write opera­tions are required to select the first block i n the list.
Each additional block in the list can be selected by
repeating the sixth Bus Write operat ion using the
address of the additional block. The Block Erase
operation starts the Program/Erase Controller
about 50µs after the last Bus Write operation.
Once the P rogram /Erase Controller starts it is not
possible to select any more blocks. Each addition­al block must therefore be selected within 50µ s of

13/42

M29W641DH, M29W641DL, M29W641DU

the lowest address block. The 50µs time r restarts
when an additional block is selected. The Status
Register can be read after the sixth Bus Write op­eration. See the Status Register section for details
on how to identify if the P rogram /Erase Cont roller
has started the Block Erase operation.

If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are p rotected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un­changed. No error condition is given when protect­ed blocks are ignored.

During the Block Erase operation th e memory wi ll
ignore all commands except the Erase Suspend
command. Typical block era se t imes a re given in
Table 4. All Bus Read operations during the Block
Erase operation w ill ou t pu t the S t a tus R eg i st er on
the Data Inputs/Outputs. See the section on the
Status Register for more details.

After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.

Erase Suspend Command

The Erase Suspend Command may be used to
temporarily suspend a Block Erase o peration and
return the memory to Read mode. The com mand
requires one Bus Write operation.

The Program/Erase Controlle r will suspend within
the Erase Suspend Latency time of the Erase Sus­pend Command being issued. Once the Program/
Erase Controller has stopped the mem ory will be
set to Read mode and t he E rase wi ll be suspend­ed. If the Erase Suspend c ommand is issued dur­ing the period when the memory is waiting for an
additional block (before the Program/E rase Con­troller starts) then the Erase is suspended immedi­ately and will start immediately when the Erase
Resume Command is issued. It is not poss ible to
select any further blocks to erase after the Erase
Resume.

During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspen ded

block then the Program co mmand is ignored and
the data remains unchanged. The Status Register
is not read and no error condi tion is given. Read­ing from blocks that are being erased will output
the Status Register.

It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands du ring
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac­cepted.

Erase Resume Command

The Erase Resume command must be used to re­start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed mo re than
once.

Enter Extended Block Command

The device has an extra 32 KWord block (Extend­ed Block) that can only be accessed using the En­ter Extended Block command. Three Bus write
cycles are required to issue the Extended Block
command. Once the command has been issued
the device enters Extende d Block mo de where a ll
Bus Read or Write operations to the Boot Block
addresses access the Extended Block. The Ex­tended Block (with the same address as the Boot
Blocks) cannot be erased, and c an be treated as
one-time programmable (OTP) memory. In Ex­tended Block mode the Boot Blocks are not acces­sible.

To exit from the Extended Block mode the Exit Ex­tended Block command must be issued.

The Extended Block can be protected, however
once protected the protection cannot be undone.

Exit Exte nded Block Com m and

The Exit Extended Block command is used to exit
from the Extended Block mod e and return t he de­vice to Read mode. Four Bus Write operations are
required to issue the command.

Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-

dental Program or Erase. The whole chip can be
unprotected to allow the dat a inside the blocks to
be changed.

Block Protect and Chip Un protect operations are
described in Appendix D.

M29W641DH, M29W641DL, M29W641DU

14/42

Table 3. Commands

Note: X Don’t Care, PA Program A ddress, PD Program Data, BA An y address in the Block. All values in the table are in hexadecimal .

Table 4. Program, Erase Tim es and Progra m, Erase E nduran ce Cycle s

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value mea sured at worst cas e conditio ns for both temperature an d V

CC

after 100,00 program/erase cycles.

4. Maximum value mea sured at worst cas e conditio ns for both temperature an d V

CC

.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Dat a

Read/Reset

1X F0

3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Double Word Program 3 555 50 PA0 PD0 PA1 PD1
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass

Program

2X A0PAPD

Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 X B0
Erase Resume 1 X 30
Read CFI Query 1 55 98
Enter Extended Block 3 555 AA 2AA 55 555 88
Exit Extended Block 4 555 AA 2AA 55 555 90 X 00

Parameter Min

Typ

(1, 2)

Max

(2)

Unit

Chip Erase 80

400

(3)

s

Block Erase (32 KWords) 0.8

6

(4)

s

Erase Suspend Latency Time

50

(4)

µs

Program (Word) 10

200

(3)

µs

Double Word Program 10

200

(3)

µs

Chip Program (Word by Word) 40

200

(3)

s

Chip Program (Double Word) 20

100

(3)

s

Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years

15/42

M29W641DH, M29W641DL, M29W641DU

STATUS REGISTER

Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Sus­pend when an address within a block being erased
is accessed.

The bits in the Status Register are summari zed in
Table 5, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera­tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.

During Program operations the Data Polling Bit
outputs the complement of the bit being pro­grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad­dress just programmed o utput DQ7, not its com­plement.

During E rase ope ration s the Da ta Polling Bit ou t-

puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op­eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.

Figure 5, Data Polling Flowchart, gives an e xam­ple of how to use the Data Polling Bit. A Valid Ad­dress is the address being programmed or an
address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re­sponded to an Erase Suspen d. The Toggle Bit is
output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle
Bit changes from ’0 ’ to ’ 1’ to ’ 0’, etc ., with succes­sive Bus Read operations at any address. After
successful completion of the operation the memo­ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.

Figure 6, Data Toggl e Flowcha rt, gives an e xam­ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro­gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Re set com m and must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad­dress w ill s how the b it is s ti ll ‘ 0 ’. One of the Era s e
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com­mand. Once the Program/Erase Cont roller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional b locks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.

Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al­ternative Toggle Bit is output on DQ2 when the
Status Register is read.

During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operation s from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.

During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad­dresses within blocks not being erased wi ll output
the memory cell data as if in Read mode.

After an Erase operation that caus es t he Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er­ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera­tions from addresses within blocks that have not
erased correctly. The Alternative Togg le Bit does
not change if the addressed block has erased cor­rectly.

M29W641DH, M29W641DL, M29W641DU

16/42

Table 5. Status Register Bits

Note: 1. Only the M29W641DU devi ce is concer ned.

2. Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

RB

(1)

Program Any Address DQ7 Toggle 0 ––0
Program During Erase Suspend Any Address DQ7

Toggle 0 – – 0

Program Error Any Address DQ7

Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before timeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0

No

Toggle

0

Block Erase

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1

No

Toggle

0

Erase Suspend

Erasing Block 1

No

Toggle

0 – Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error

Good Block Address 0 Toggle 1 1

No

Toggle

0

Faulty Block Address 0 Toggle 1 1 Toggle 0

17/42

M29W641DH, M29W641DL, M29W641DU

Figure 5. Dat a Polling Flo wchart Figure 6. Da ta To ggl e Fl owchart

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI90194

DQ7

=

DATA

YES

NO

YES

NO

DQ5

= 1

DQ7

=

DATA

YES

NO

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI90195B

DQ6

=

TOGGLE

NO

NO

YES

YES

DQ5

= 1

NO

YES

DQ6

=

TOGGLE

READ

DQ5 & DQ6

M29W641DH, M29W641DL, M29W641DU

18/42

MAXIMUM RATI N G

Stressing the de vice above the rating l isted in t he
Absolute Maximum Ratings t able may cause per­manent damage to the device. Exposure to Abso­lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of t he device at

these or any other conditions above those indicat­ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu­ments.

Table 6. Absolute Maximum Ratings

Note: 1. M inimum voltage may undershoot to –2V during transition and for less than 20ns during transitions .

2. Maximum voltage may overshoot to V

CC

+2V during transitio n and for less t han 20ns during transitions.

3. V

PP

must not re m ai n at 12V for more t han a total of 80 hrs.

Symbol Parameter Min Max Unit

T

BIAS

Temperature Under Bias –50 125 °C

T

STG

Storage Temperature

–65 150 °C

V

CCQ

Input/Output Supply Voltage

(1,2)

–0.6 4 V

V

CC

Supply Voltage –0.6 4 V

V

ID

Identification Voltage –0.6 13.5 V

V

PP

(3)

Program Voltage –0.6 13.5 V

19/42

M29W641DH, M29W641DL, M29W641DU

DC AND AC PARAMETERS

This section summarizes t he operating and mea­surement conditions, and the DC and AC charac­teristics of the device. The parameters i n the DC
and AC Characteristic tables that follow are de­rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should c heck that the o perat ing
conditions in their circuit match the m easurement
conditions when relying on the quoted parame­ters.

Table 7. Operating and AC Measurement Conditions

Figure 7. AC Measurement I/O Waveform Figure 8. AC Measurement Load Circuit

Table 8. Device Capacitance

Note: Sampled only, not 100% tested.

Parameter

M29W641D

Unit70 90 100 120

Min Max Min Max Min Ma x Min Max

V

CC

Supply Voltage

3.0 3.6 2.7 3.6 3.0 3.6 2.7 3.6 V

V

CCQ

Supply Voltage

3.0 3.6 2.7 3.6 1.65 1.95 1.65 1.95 V

Ambient Operating Temperature –40 85 –40 85 –40 85 –40 85 °C

Load Capacitance (C

L

)

30 30 30 30 pF
Input Rise and Fall Times 10 10 10 10 ns
Input Pulse Voltages

0 to V

CCQ

0 to V

CCQ

0 to V

CCQ

0 to V

CCQ

V

Input and Output Timing Ref.
Voltages

V

CCQ

/2 V

CCQ

/2 V

CCQ

/2 V

CCQ

/2

V

AI05557b

V

CCQ

0V

V

CCQ

/2

AI05558b

C

L

CL includes JIG capacitance

DEVICE

UNDER

TEST

25kΩ

V

CCQ

25kΩ

V

CC

0.1µF

V

CCQ

0.1µF

V

PP

0.1µF

Symbol Parameter Test Condition Min Max Unit

C

IN

Input Capacitance

V

IN

= 0V

6pF

C

OUT

Output Capacitance

V

OUT

= 0V

12 pF

M29W641DH, M29W641DL, M29W641DU

20/42

Table 9. DC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

I

LI

Input Leakage Current

0V ≤ V

IN

≤ V

CCQ

±1

µA

I

LO

Output Leakage Current

0V ≤ V

OUT

≤ V

CCQ

±1

µA

I

CC1

Supply Current (Read)

E

= VIL, G = VIH,

f = 6 MHz

10 mA

I

CC2

Supply Current (Standby)

E

= VCC ±0.2V,

RP

= VCC ±0.2V

100

µA

I

CC3

Supply Current (Program/
Erase)

Program/Erase

Controller active

V

PP

pin =

V

IL

or V

IH

20 mA

V

PP

pin =

V

PPH

20 mA

V

IL

Input Low Voltage

V

CCQ

≤ V

CC

–0.5

0.8

V

V

IH

Input High Voltage

V

CCQ

≤ V

CC

0.7V

CCQ

V

CCQ

+ 0.3

V

V

PPH

Voltage for VPP Program
Acceleration

V

CC

= 3.0V ±10%

11.5 12.5 V

I

PP

Current for VPP Program
Acceleration

V

CC

= 3.0V ±10%

15 mA

V

OL

Output Low Voltage

I

OL

= 4.0mA, VCC = V

CCmin

0.45 V

V

OH

(1)

Output High Voltage

I

OH

= –2.0mA, VCC = V

CCmin

0.85V

CCQ

V

I

OH

= –100µA, VCC = V

CCmin

V

CCQ

– 0.4

V

V

ID

Identification Voltage 11.5 12.5 V

V

LKO

(1)

Program/Erase Lockout Supply
V oltage

1.8 2.3 V

21/42

M29W641DH, M29W641DL, M29W641DU

Figure 9. Read Mode AC Waveforms

Table 10. Read AC Characteristics

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition

M29W641D

Unit

70 90 100 120

t

AVAV

t

RC

Address Valid to Next Address Valid

E

= VIL,

G

= V

IL

Min 70 90 100 120 ns

t

AVQV

t

ACC

Address Valid to Output Valid

E

= VIL,

G

= V

IL

Max 70 90 100 120 ns

t

ELQX

(1)

t

LZ

Chip Enable Low to Output Transition

G

= V

IL

Min0000ns

t

ELQV

t

CE

Chip Enable Low to Output Valid

G

= V

IL

Max 70 90 100 120 ns

t

GLQX

(1)

t

OLZ

Output Enable Low to Output Transition

E

= V

IL

Min0000ns

t

GLQV

t

OE

Output Enable Low to Output Valid

E

= V

IL

Max 30 35 35 50 ns

t

EHQZ

(1)

t

HZ

Chip Enable High to Output Hi-Z

G

= V

IL

Max 25 30 30 30 ns

t

GHQZ

(1)

t

DF

Output Enable High to Output Hi-Z

E

= V

IL

Max 25 30 30 30 ns

t

EHQX

t

GHQX

t

AXQX

t

OH

Chip Enable, Output Enable or Address
Transition to Output Transition

Min0000ns

AI06699

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A21

G

DQ0-DQ7/
DQ8-DQ15

E

tELQV tEHQX

tGHQZ

VALID

M29W641DH, M29W641DL, M29W641DU

22/42

Figure 10. Write AC Waveforms, Write Enable Controlled

Note: 1. RB conc erns the M29W461DU only.

Table 11. Write AC Characteristics, Write Enable Controlled

Note: 1. This timing concerns the M29W461DU only.

Symbol Alt Parameter

M29W641D

Unit

70 90 100 120

t

AVAV

t

WC

Address Valid to Next Address Valid Min 70 90 100 120 ns

t

ELWL

t

CS

Chip Enable Low to Write Enable Low Min 0 0 0 0 ns

t

WLWH

t

WP

Write Enable Low to Write Enable High Min 35 35 35 50 ns

t

DVWH

t

DS

Input Valid to Write Enable High Min 45 45 45 50 ns

t

WHDX

t

DH

Write Enable High to Input Transition Min 0 0 0 0 ns

t

WHEH

t

CH

Write Enable High to Chip Enable High Min 0 0 0 0 ns

t

WHWL

t

WPH

Write Enable High to Write Enable Low Min 30 30 30 30 ns

t

AVWL

t

AS

Address Valid to Write Enable Low Min 0 0 0 0 ns

t

WLAX

t

AH

Write Enable Low to Address Transition Min 45 45 45 50 ns

t

GHWL

Output Enable High to Write Enable Low Min 0 0 0 0 ns

t

WHGL

t

OEH

Write Enable High to Output Enable Low Min 0 0 0 0 ns

t

WHRL

(1)

t

BUSY

Program/Erase Valid to RB Low Max 90 90 90 90 ns

t

VCHEL

t

VCSVCC

High to Chip Enable Low

Min 50 50 50 50 µs

AI06800b

E

G

W

A0-A21

DQ0-DQ7/
DQ8-DQ15

VALID

VALID

V

CC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

RB

tWHRL

23/42

M29W641DH, M29W641DL, M29W641DU

Figure 11. Write AC Waveforms, Chip Enable Controlled

Note: 1. RB conc erns the M29W461DU only.

Table 12. Write AC Characteristics, Chip Enable Controlled

Note: 1. This timing concerns the M29W461DU only.

Symbol Alt Parameter

M29W641D

Unit

70 90 100 120

t

AVAV

t

WC

Address Valid to Next Address Valid Min 70 90 100 120 ns

t

WLEL

t

WS

Write Enable Low to Chip Enable Low Min 0 0 0 0 ns

t

ELEH

t

CP

Chip Enable Low to Chip Enable High Min 45 45 45 50 ns

t

DVEH

t

DS

Input Valid to Chip Enable High Min 45 45 45 50 ns

t

EHDX

t

DH

Chip Enable High to Input Transition Min 0 0 0 0 ns

t

EHWH

t

WH

Chip Enable High to Write Enable High Min 0 0 0 0 ns

t

EHEL

t

CPH

Chip Enable High to Chip Enable Low Min 30 30 30 30 ns

t

AVEL

t

AS

Address Valid to Chip Enable Low Min 0 0 0 0 ns

t

ELAX

t

AH

Chip Enable Low to Address Transition Min 45 45 45 50 ns

t

GHEL

Output Enable High Chip Enable Low Min 0 0 0 0 ns

t

EHGL

t

OEH

Chip Enable High to Output Enable Low Min 0 0 0 0 ns

t

EHRL

(1)

t

BUSY

Program/Erase Valid to RB Low Max 90 90 90 90 ns

t

VCHWL

t

VCSVCC

High to Write Enable Low

Min 50 50 50 50 µs

AI06801b

E

G

W

A0-A21

DQ0-DQ7/
DQ8-DQ15

VALID

VALID

V

CC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

RB

tEHRL

M29W641DH, M29W641DL, M29W641DU

24/42

Figure 12. Reset/Block Tempor ary Unprotec t AC Waveforms

Note: 1. RB conc erns the M29W461DU only.

Table 13. Reset/Block Temporary Unprotect AC Characteristics

Note: 1. Sampled only, not 100% tested.

2. These timings conc ern the M29W461DU only.

Figure 13. Accelerated Program Timing Waveforms

Symbol Alt Parameter

M29W641D

Unit

70 90 100 120

t

PHWL

(1)

t

PHEL

t

PHGL

(1)

t

RH

RP High to Write Enable Low, Chip Enable Low,
Output Enable Low

Min 50 50 50 50 ns

t

RHWL

(1, 2)

t

RHEL

(1, 2)

t

RHGL

(1, 2)

t

RB

RB High to Write Enable Low, Chip Enable Low,
Output Enable Low

Min0000ns

t

PL YH

t

READY

RP Low to Read Mode Max 50 50 50 50 µs

t

PLPX

t

RP

RP Pulse Width Min 500 500 500 500 ns

t

PHPHH

(1)

t

VIDR

RP Rise Time to V

ID

Min 500 500 500 500 ns

t

VHVPP

(1)

VPP Rise and Fall Time

Min 250 250 250 250 ns

AI06802b

RB

W,

RP

tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

AI06806

VPP Pin

V

PP

V

IL

or V

IH

tVHVPP

tVHVPP

25/42

M29W641DH, M29W641DL, M29W641DU

PACKAGE MECHANICAL

Figure 14. TSO P4 8 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Pa ckage Outline

Note: Drawing is not to scale.

Table 14. TSOP48 – 48 lead Plastic Thin Sma ll Outline, 12 x 20mm, Packag e Me chan ical Data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7 283

e 0.500 – – 0.0197 – –

E 11.900 12.100 0.4685 0.4764

L 0.500 0.700 0.0197 0.0276

alfa 0 5 0 5

N48 48

TSOP-a

D1

E

1 N

CP

B

e

A2

A

N/2

D

DIE

C

LA1 α

M29W641DH, M29W641DL, M29W641DU

26/42

Figure 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8m m pitch, Bottom view package outline

Note: Drawing is not to scale.

Table 15. TFBGA63 - 7x11mm, 6x8 active ball array, 0.8mm pitch, Pack age Mechan ical Data

Symbol

millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472
A1 0.250 0.0098
A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 7.000 6.900 7.100 0.2756 0.2717 0.2795

D1 5.600 – – 0.2205 – –

ddd – – 0.100 – – 0.0039

E 11.000 10.900 11.100 0.4331 0.4291 0.4370
E1 8.800 – – 0.3465 – –

e 0.800 – – 0.0315 – –
FD 0.700 – – 0.0276 – –
FE 1.100 – – 0.0433 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –

E

D

eb

SD

SE

A2

A1

A

BGA-Z33

ddd

FD

D1

E1

e

FE

BALL "A1"

27/42

M29W641DH, M29W641DL, M29W641DU

PART NUMBERING

Table 16. Ordering Information Scheme

Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of available op­tions (Speed, Package, etc.) o r for further i nformation on a ny aspec t of this dev ice, please c ontact your
nearest ST Sales Office.

Example: M29W641DL 70 N 1 T

Device Type

M29

Operating Voltage

W = V

CC

= 2.7 to 3.6V

Device Function

641DH = 64 Mbit (x16), Uniform Block, Write Protection on highest
address Block

641DL = 64 Mbit (x16), Uniform Block, Write Protection on Lowest
Address Block

641DU = 64 Mbit (x16), Uniform Block, No Write Protection

Speed

70 = 70ns
90 = 90ns
10 = 100ns
12 = 120ns

Package

N = TSOP48: 12 x 20 mm (M29W641DH and M29W641DL only)
ZA = TFBGA63: 7 x 11mm, 0.80mm pitch (M29W641DU only)

Temperature Range

1 = 0 to 70 °C
6 = –40 to 85 °C

Option

T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing

M29W641DH, M29W641DL, M29W641DU

28/42

APPENDIX A. BLOCK ADDRESSES

Table 17. Block Addresses

Block KWords Protection Block Group Address Range

032

Protection Group

000000h–007FFFh

(1)

1 32 008000h–00FFFFh
2 32 010000h–017FFFh
3 32 018000h–01FFFFh
432

Protection Group

020000h–027FFFh
5 32 028000h–02FFFFh
6 32 030000h–037FFFh
7 32 038000h–03FFFFh
832

Protection Group

040000h–047FFFh
9 32 048000h–04FFFFh

10 32 050000h–057FFFh
11 32 058000h–05FFFFh
12 32

Protection Group

060000h–067FFFh

13 32 068000h–06FFFFh
14 32 070000h–077FFFh
15 32 078000h–07FFFFh
16 32

Protection Group

080000h–087FFFh

17 32 088000h–08FFFFh
18 32 090000h–097FFFh
19 32 098000h–09FFFFh
20 32

Protection Group

0A0000h–0A7FFFh
21 32 0A8000h–0AFFFFh
22 32 0B0000h–0B7FFFh
23 32 0B8000h–0BFFFFh
24 32

Protection Group

0C0000h–0C7FFFh
25 32 0C8000h–0CFFFFh
26 32 0D0000h–0D7FFFh
27 32 0D8000h–0DFFFFh
28 32

Protection Group

0E0000h–0E7FFFh
29 32 0E8000h–0EFFFFh
30 32 0F0000h–0F7FFFh
31 32 0F8000h–0FFFFFh

29/42

M29W641DH, M29W641DL, M29W641DU

32 32

Protection Group

100000h–107FFFh
33 32 108000h–10FFFFh
34 32 110000h–117FFFh
35 32 118000h–11FFFFh
36 32

Protection Group

120000h–127FFFh
37 32 128000h–12FFFFh
38 32 130000h–137FFFh
39 32 138000h–13FFFFh
40 32

Protection Group

140000h–147FFFh
41 32 148000h–14FFFFh
42 32 150000h–157FFFh
43 32 158000h–15FFFFh
44 32

Protection Group

160000h–167FFFh
45 32 168000h–16FFFFh
46 32 170000h–177FFFh

47

32 178000h–17FFFFh

48 32

Protection Group

180000h–187FFFh
49 32 188000h–18FFFFh
50 32 190000h–197FFFh
51 32 198000h–19FFFFh
52 32

Protection Group

1A0000h–1A7FFFh
53 32 1A8000h–1AFFFFh
54 32 1B0000h–1B7FFFh
55 32 1B8000h–1BFFFFh
56 32

Protection Group

1C0000h–1C7FFFh
57 32 1C8000h–1CFFFFh
58 32 1D0000h–1D7FFFh
59 32 1D8000h–1DFFFFh
60 32

Protection Group

1E0000h–1E7FFFh
61 32 1E8000h–1EFFFFh
62 32 1F0000h–1F7FFFh
63 32 1F8000h–1FFFFFh
64 32

Protection Group

200000h–207FFFh
65 32 208000h–20FFFFh
66 32 210000h–217FFFh
67 32 218000h–21FFFFh

Block KWords Protection Block Group Address Range

M29W641DH, M29W641DL, M29W641DU

30/42

68 32

Protection Group

220000h–227FFFh

69 32 228000h–22FFFFh
70 32 230000h–237FFFh
71 32 238000h–23FFFFh
72 32

Protection Group

240000h–247FFFh
73 32 248000h–24FFFFh
74 32 250000h–257FFFh
75 32 258000h–25FFFFh
76 32

Protection Group

260000h–267FFFh
77 32 268000h–26FFFFh
78 32 270000h–277FFFh
79 32 278000h–27FFFFh
80 32

Protection Group

280000h–287FFFh
81 32 288000h–28FFFFh
82 32 290000h–297FFFh
83 32 298000h–29FFFFh
84 32

Protection Group

2A0000h–2A7FFFh
85 32 2A8000h–2AFFFFh
86 32 2B0000h–2B7FFFh
87 32 2B8000h–2BFFFFh
88 32

Protection Group

2C0000h–2C7FFFh
89 32 2C8000h–2CFFFFh
90 32 2D0000h–2D7FFFh
91 32 2D8000h–2DFFFFh
92 32

Protection Group

2E0000h–2E7FFFh
93 32 2E8000h–2EFFFFh
94 32 2F0000h–2F7FFFh
95 32 2F8000h–2FFFFFh
96 32

Protection Group

300000h–307FFFh
97 32 308000h–30FFFFh
98 32 310000h–317FFFh
99 32 318000h–31FFFFh

100 32

Protection Group

320000h–327FFFh

101 32 328000h–32FFFFh
102 32 330000h–337FFFh
103 32 338000h–33FFFFh

Block KWords Protection Block Group Address Range

31/42

M29W641DH, M29W641DL, M29W641DU

Note: 1. U sed as the Extended Block Addresses i n E xt ended Block mode.

104 32

Protection Group

340000h–347FFFh

105 32 348000h–34FFFFh
106 32 350000h–357FFFh
107 32 358000h–35FFFFh
108 32

Protection Group

360000h–367FFFh

109 32 368000h–36FFFFh
110 32 370000h–377FFFh

111

32

378000h–37FFFFh

112 32

Protection Group

380000h–387FFFh

113 32 388000h–38FFFFh
114 32 390000h–397FFFh
115 32 398000h–39FFFFh
116 32

Protection Group

3A0000h–3A7FFFh
117 32 3A8000h–3AFFFFh
118 32 3B0000h–3B7FFFh
119 32 3B8000h–3BFFFFh
120 32

Protection Group

3C0000h–3C7FFFh
121 32 3C8000h–3CFFFFh
122 32 3D0000h–3D7FFFh
123 32 3D8000h–3DFFFFh
124 32

Protection Group

3E0000h–3E7FFFh
125 32 3E8000h–3EFFFFh
126 32 3F0000h–3F7FFFh

127 32

3F8000h–3FFFFFh

Block KWords Protection Block Group Address Range

M29W641DH, M29W641DL, M29W641DU

32/42

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the de vic e to determine
various electrical and timing parameters, density
information and function s supported by t he mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the CFI Query Command is issued the de­vice enters CFI Query mode and the data structure
is read from the memory. Table 18 to Table 23
show the addresses used to retrieve the data.

The CFI data structure also contains a security
area where a 64 bit unique security number is writ­ten (see Table 23, Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to c hange the se curity num­ber after it has been written by ST.

Table 18. Query Stru cture Overvi ew

Note: Query data are always presented on the lowest order data outputs.

Table 19. CFI Query Identification String

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Address Sub-section Name Description

10h CFI Query Identification String Command set ID and algorithm data offset

1Bh System Interface Information Device timing & voltage information

27h Device Geometry Definition Flash device layout

40h

Primary Algorithm-specific Extended
Query table

Additional information specific to the Primary
Algorithm (optional)

61h Security Code Area 64 bit unique device number

Address Data Description Value

10h 0051h “Q”
11h 0052h Query Unique ASCII String "QRY" "R"
12h 0059h "Y"
13h 0002h

Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm

AMD

Compatible

14h 0000h
15h 0040h

Address for Primary Algorithm extended Query table (see Table 22) P = 40h

16h 0000h
17h 0000h

Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported

NA

18h 0000h
19h 0000h

Address for Alternate Algorithm extended Query table

NA

1Ah 0000h

33/42

M29W641DH, M29W641DL, M29W641DU

Table 20. CFI Query System Interface I nform ation

Table 21. Device Geometry Definition

Address Data Description Value

1Bh 0027h

V

CC

Logic Supply Minimum Program/Erase voltage
bit 7 to 4 BCD value in volts
bit 3 to 0 BCD value in 100 mV

2.7V

1Ch 0036h

V

CC

Logic Supply Maximum Program/Erase voltage
bit 7 to 4 BCD value in volts

bit 3 to 0 BCD value in 100 mV

3.6V

1Dh 00B5h

V

PP

[Programming] Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

11.5V

1Eh 00C5h

V

PP

[Programming] Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

12.5V

1Fh 0004h

Typical timeout per single word program = 2

n

µs

16µs

20h 0000h

Typical timeout for minimum size write buffer program = 2

n

µs

NA

21h 000Ah

Typical timeout per individual block erase = 2

n

ms

1s

22h 0000h

Typical timeout for full chip erase = 2

n

ms

NA

23h 0004h

Maximum timeout for word program = 2

n

times typical

256 µs

24h 0000h

Maximum timeout for write buffer program = 2

n

times typical

NA

25h 0003h

Maximum timeout per individual block erase = 2

n

times typical

8s

26h 0000h

Maximum timeout for chip erase = 2

n

times typical

NA

Address Data Description Value

27h 0017h

Device Size = 2

n

in number of bytes

8 MByte

28h
29h

0001h
0000h

Flash Device Interface Code description

x16

Async.

2Ah
2Bh

0000h
0000h

Maximum number of bytes in multi-byte program or page = 2

n

NA

2Ch 0001h

Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size.

1

2Dh
2Eh

007Fh
0000h

Region 1 Information
Number of identical size erase block = 007Fh+1

128

2Fh
30h

0000h
0001h

Region 1 Information
Block size in Region 1 = 0100h * 256 byte

64 KByte

M29W641DH, M29W641DL, M29W641DU

34/42

Table 22. Primary Algorithm -Speci fic Extend ed Query Table

Table 23. Security Code Area

Address Data Description Value

40h 0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"
41h 0052h "R"
42h 0049h "I"
43h 0031h Major version number, ASCII "1"
44h 0030h Minor version number, ASCII "0"
45h 0000h Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

Yes

46h 0002h Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write

2

47h 0004h Block Protection

00 = not supported, x = number of blocks per protection group

4

48h 0001h Temporary Block Unprotect

00 = not supported, 01 = supported

Yes

49h 0004h Block Protect /Unprotect

04 = M29W400B

4

4Ah 0000h Simultaneous Operations, 00 = not supported No
4Bh 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No
4Dh 00B5h V

PP

Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

11.5V

4Eh 00C5h V

PP

Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts

bit 3 to 0 BCD value in 100 mV

12.5V

Address Data Description

61h XXXX

64 bit: unique device number

62h XXXX
63h XXXX
64h XXXX

35/42

M29W641DH, M29W641DL, M29W641DU

APPENDIX C. EXTENDED MEMORY BLOCK

The M29W641D has an extra block, the Extended
Block, that can be accessed using a dedicated
command.

This Extended Block is 32 KWords. It is used as a
security block (to provide a permanent security
identification number) or to store addit ional infor­mation .

The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit

DQ7. This bit is permane ntl y set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprotected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a facto­ry locked one.

Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific proced ure must
be followed to read it. See “Extended Memory
Block Ve rify Code

” in Table 2, Bus Operations, for

details of how to read bit DQ7.
The Extended Block can only be accessed when

the device is in Ext ended B lock m ode. Fo r details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Com­mand and Exit Extended Block Command para-

graphs, and to Table 3, “Commands”.

Factory Locked Extended Block

In devices where the Extended Block is factory
locked, the Security Identification Number i s writ­ten to the Extended Block address space (see Ta­ble 24, Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.

Customer Lockable Extended Block

A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protec­tion of the Extended Block is not reversible.

There are two ways of protecting the Extended
Block:

■ Issue the Enter Extended Block command t o

place the device in Extended Block mode, then
use the In-System Technique (refer to Appendix
D, In-System Technique and to the
corresponding flowcharts, Figures 18 and 19,
for a detailed explanation of the technique).

■ Issue the Enter Extended Block command to

place the device in Extended Block mode, then
use the Programmer Technique (refer to
Appendix D, Programmer Technique and to the
corresponding flowcharts, Figures 16 and 17,
for a detailed explanation of the technique).

Once the Extended Block is programmed and pro­tected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.

Table 24. Extended Block Address and Data

Note: 1. Se e T able 17, Block Addresses.

Device

Address

(1)

Data

x16 Factory Locked Custo mer Lockable

M29W641D

000000h-000007h Security Identification Number

Determined by Customer

000008h-007FFFh Unavailable

M29W641DH, M29W641DL, M29W641DU

36/42

APPENDIX D. BLOCK PROTECTION

Block protection can be used to prevent any oper­ation from modifying the data stored in the memo­ry. Once protected, Program and Erase
operations within the protected group fail to
change the data.

There are three techniques that can be used to
control Block Protection, these a re the Program­mer technique, the In-System technique and Tem­porary Unprotection. Temporary Unprotection is
controlled by the Re set/Block Temporary Unpro­tection pin, RP

; this is described in the Sign al De-

scriptions sect ion.

Prog ram m er Te chnique

The Programmer tec hnique uses high (V

ID

) volt­age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended on ly for
use in Programming Equipment.

To protect a group of blocks follow the flowchart in
Figure 16, Programmer Equipment G roup P rote ct
Flowchart. To unprotect the whole chip it is neces­sary to protect all of the groups first, then all
groups can be unprotect ed at the same time. To
unprotect the chip foll ow Figure 17, Prog rammer
Equipment Chip Unprotect Flowchart. Table 25,
Programmer Techniq ue Bus Operations, gives a
summary of each operation.

The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do
not abort the proce dure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.

In-System Technique

The In-System technique require s a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP

. This can be achieved without violating the
maximum ratings of the components on the micro­processor bus, therefore this technique is suitable
for use after the memory has been fitted to the sys­tem.

To protect a group of blocks follow the flowchart in
Figure 18, In-System Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces­sary to protect all of the groups first, then all the
groups can be unprotect ed at the same time. To
unprotect the chip follow Figure 19, In-System
Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care
should be taken t o ensure t hat, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor t o service interru pts
that will upset the timing and do not abort the pro­cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.

Table 25. Programm er Tech niqu e Bus Operati ons

Note: 1. Blo ck Protection Groups are sh own in Appendix A, Tables 17.

Operation E G W

Address Inputs

A0-A21

Data Inputs/Outputs

DQ15-DQ0

Block (Group)
Protect

(1)

V

IL

VIDVIL Pulse

A9 = V

ID

, A12-A21 Block Address

Others = X

X

Chip Unprotect

V

ID

VIDVIL Pulse

A9 = V

ID

, A12 = VIH, A15 = VIH

Others = X

X

Block (Group)
Protection Verify

V

IL

V

IL

V

IH

A0 = VIL, A1 = VIH, A6 = VIL, A9=VID,

A12-A21 Block Address

Others = X

Pass = XX01h

Retry = XX00h

Block (Group)
Unprotection Verify

V

IL

V

IL

V

IH

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

A12-A21 Block Address

Others = X

Retry = XX01h

Pass = XX00h

37/42

M29W641DH, M29W641DL, M29W641DU

Figure 16. Programmer Equipment Group Protect Flowchart

ADDRESS = GROUP ADDRESS

AI05574

G, A9 = VID,

E = V

IL

n = 0

Wait 4µs

Wait 100µs

W = V

IL

W = V

IH

E, G = VIH,

A0, A6 = VIL,

A1 = V

IH

A9 = V

IH

E, G = V

IH

++n

= 25

START

FAIL

PASS

YES

NO

DATA

=

01h

YES

NO

W = V

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

Verify Protect Set-upEnd

A9 = V

IH

E, G = V

IH

M29W641DH, M29W641DL, M29W641DU

38/42

Figu re 17. Progr ammer Equipm e nt Chip Unprotect Flowch a rt

PROTECT ALL GROUPS

AI05575

A6, A12, A15 = V

IH

(1)

E, G, A9 = V

ID

DATA

W = V

IH

E, G = V

IH

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1, A6 = V

IH

Wait 10ms

=

00h

INCREMENT

CURRENT GROUP

n = 0

CURRENT GROUP = 0

Wait 4µs

W = V

IL

++n

= 1000

START

YES

YESNO

NO

LAST

GROUP

YES

NO

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

FAIL PASS

Verify Unprotect Set-upEnd

A9 = V

IH

E, G = V

IH

A9 = V

IH

E, G = V

IH

39/42

M29W641DH, M29W641DL, M29W641DU

Figure 18. In-System Equipment Group Protect Flowchart

AI05576

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IL

n = 0

Wait 100µs

WRITE 40h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IL

RP = V

IH

++n

= 25

START

FAIL

PASS

YES

NO

DATA

=

01h

YES

NO

RP = V

IH

Wait 4µs

Verify Protect Set-upEnd

READ DATA

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IL

RP = V

ID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IL

M29W641DH, M29W641DL, M29W641DU

40/42

Figure 19. In-System Equipment Chip Unprotect Flowchart

AI05577

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

IH

n = 0

CURRENT GROUP = 0

Wait 10ms

WRITE 40h

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IH

RP = V

IH

++n

= 1000

START

FAIL

PASS

YES

NO

DATA

=

00h

YESNO

RP = V

IH

Wait 4µs

READ DATA

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IH

RP = V

ID

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PROTECT ALL GROUPS

INCREMENT

CURRENT GROUP

LAST

GROUP

YES

NO

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

IH

Verify Unprotect Set-upEnd

41/42

M29W641DH, M29W641DL, M29W641DU

REVISION HISTORY

Table 26. Document Revision History

Date Version Revision Details

30-Apr-2002 -01 Document released

05-Sep-2002 1.1

When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Double Word Program Time (typ) changed to 20s.
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 01 equals 1.0).

8-Apr-2003 2.0

New Part Numbers added. 100ns and 120ns Speed Classes added. TFBGA63 package
added. V

IO

removed from and V

CCQ

added to Table 6, Absolute Maximum Ratings. V

CCQ

added to Table 7, Operating and AC Measurement Conditions. Ready/Busy pin
(TFBGA63 package) added to the signals (concerns M29W641DU only).
Figure 7, AC Measurement I/O Waveform, and Figure 8, AC Measurement Load Circuit,
modified. Unlock Bypass Commands clarified and V

CCQ

description specified in SIGNAL

DESCRIPTIONS section. Test Conditions modified for I

LI

, ILO, VIL, VIH, VOL and VOH

parameters in Table 9, DC Characteristics, and V

IL

, VIH, VOL and VOH parameters

corrected. t

WLWH

, t

DVWH

, t

WLAX

, t

WHRL

parameters modified for 90ns speed class in Tab le

11, Write AC Characteristics, Write Enable Controlled. t

ELEH

, t

DVEH

, t

ELAX

and t

EHRL

parameters modified for 90ns speed class in Table 12, Write AC Characteristics, Chip
Enable Controlled. t

PLYH

parameter added to Tab le 13, Reset/Block Temporary Unprotect

AC Characteristics.
Data and Value modified for address 2Dh, and Data modified for address 30h in T ab le 21,
Device Geometry Definition. Description modified at address offset 4Eh in Table 22.
Data Retention and Erase Suspend Latency Time parameters added to T able 6, Program,
Erase Times and Program, Erase Endurance Cycles, and Typical after 100k W/E Cycles
column removed. I

ID

(Identification) current removed from Table 9, DC Characteristics.

Lead-free package options E and F added to Table 16, Ordering Information Scheme.
Appendix C, EXTENDED MEMORY BLOCK, added. V

SS

pin connection to ground
clarified. Auto Select Command is used to read the Extended Memory Block. Note added
to Table 16, Ordering Information Scheme.

M29W641DH, M29W641DL, M29W641DU

42/42

Informa tion furnished is believed to be ac curate and reliable. However, STMicroelectro ni cs assumes no resp onsibility for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwis e under any patent or patent ri ghts of STM i croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authoriz ed for use as cri tical comp onents in life support devi ces or systems without express writt en approval of STM i croelect ronics.

The ST logo is registered trade m ark of STMicroelectronics

All other names are th e property of their respec tive owners

© 2003 STMicroelectronics - All Rights Reserved

STMicroelectronics group of companies

Australia - Brazil - Canada - China - F i nl and - France - Germany - Hong Kong -

India - Isr ael - I taly - Japan - M al aysia - Malt a - M orocco - S in gapore - Spain - Sweden - S witzerland - United Kingdom - Unit ed States.

www.st.com