M28W640ECB10N1
M28W640ECT
M28W640ECB
64 Mbit (4Mb x16, Boot Block)
3V Supply Flash Memory
PRELIMINARY DATA
FEATURES SUMMARY
■SUPPLY VOLTAGE
–VDD = 2.7V to 3.6V Core Power Supply
–VDDQ= 1.65V to 3.6V for Input/Output
–VPP = 12V for fast Program (optional)
■ACCESS TIME: 70, 85, 90,100ns
■PROGRAMMING TIME:
–10µs typical
–Double Word Programming Option
–Quadruple Word Programming Option
■COMMON FLASH INTERFACE
■MEMORY BLOCKS
–Parameter Blocks (Top or Bottom location)
–Main Blocks
■BLOCK LOCKING
–All blocks locked at Power Up
–Any combination of blocks can be locked
–WP for Block Lock-Down
■SECURITY
–128 bit user Programmable OTP cells
–64 bit unique device identifier
■AUTOMATIC STAND-BY MODE
■PROGRAM and ERASE SUSPEND
■100,000 PROGRAM/ERASE CYCLES per BLOCK
■ELECTRONIC SIGNATURE
–Manufacturer Code: 20h
–Top Device Code, M28W640ECT: 8848h
–Bottom Device Code, M28W640ECB: 8849h
Figure 1. Packages
FBGA
TFBGA48 (ZB) 6.39 x 10.5mm
TSOP48 (N) 12 x 20mm
April 2003 |
1/55 |
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M28W640ECT, M28W640ECB
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Protection Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/55
M28W640ECT, M28W640ECB
Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 16
BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 9. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 16. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12. Power-Up and Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 19. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/55
M28W640ECT, M28W640ECB
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 30 Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 30 Figure 14. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline31 Table 21. TFBGA48 6.39x10.5mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 31 Figure 15. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 32 Figure 16. TFBGA48 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 24. Top Boot Block Addresses, M28W640ECT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 25. Bottom Boot Block Addresses, M28W640ECB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 27. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 28. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 19. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 20. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 47 Figure 21. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 23. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 52
Table 32. Write State Machine Current/Next, sheet 1 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 33. Write State Machine Current/Next, sheet 2 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4/55
M28W640ECT, M28W640ECB
SUMMARY DESCRIPTION
The M28W640EC is a 64 Mbit (4 Mbit x 16) nonvolatile Flash memory that can be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 2.7V to 3.6V VDD supply for the circuitry and a 1.65V to 3.6V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming.
The device features an asymmetrical blocked architecture. The M28W640EC has an array of 135 blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. M28W640ECT has the Parameter Blocks at the top of the memory address space while the M28W640ECB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 5, Block Addresses.
The M28W640EC features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase.
When VPP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles.
The device includes a 192 bit Protection Register to increase the protection of a system design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The 64 bit segment contains a unique device number written by ST, while the second one is one-time-programmable by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register Memory Map.
Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
The memory is offered in TSOP48 (12 X 20mm) and TFBGA48 (6.39 x 10.5mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
VDD VDDQ VPP
22 |
16 |
A0-A21
DQ0-DQ15
W
E M28W640ECT
M28W640ECB
G
RP
WP
VSS
AI04378b
Table 1. Signal Names
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A0-A21 |
Address Inputs |
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DQ0-DQ15 |
Data Input/Output |
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Chip Enable |
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E |
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Output Enable |
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G |
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Write Enable |
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W |
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Reset |
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RP |
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Write Protect |
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WP |
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VDD |
Core Power Supply |
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VDDQ |
Power Supply for |
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Input/Output |
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VPP |
Optional Supply Voltage for |
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VSS |
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NC |
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5/55
M28W640ECT, M28W640ECB
Figure 3. TSOP Connections
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A16 |
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A15 |
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A13 |
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A12 |
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A10 |
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DQ14 |
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A9 |
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DQ6 |
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A8 |
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DQ13 |
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A21 |
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DQ5 |
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A20 |
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DQ12 |
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DQ4 |
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12 M28W640ECT 37 |
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VDD |
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VPP |
13 M28W640ECB 36 |
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DQ11 |
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WP |
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DQ3 |
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A19 |
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DQ10 |
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A18 |
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DQ2 |
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A17 |
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DQ9 |
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A7 |
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DQ1 |
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A6 |
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DQ8 |
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A5 |
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DQ0 |
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A3 |
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A1 |
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A0 |
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AI04379b |
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6/55
M28W640ECT, M28W640ECB
Figure 4. TFBGA Connections (Top view through package)
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
A |
A13 |
A11 |
A8 |
VPP |
WP |
A19 |
A7 |
A4 |
B |
A14 |
A10 |
W |
RP |
A18 |
A17 |
A5 |
A2 |
C |
A15 |
A12 |
A9 |
A21 |
A20 |
A6 |
A3 |
A1 |
D |
A16 |
DQ14 |
DQ5 |
DQ11 |
DQ2 |
DQ8 |
E |
A0 |
E |
VDDQ |
DQ15 |
DQ6 |
DQ12 |
DQ3 |
DQ9 |
DQ0 |
VSS |
F |
VSS |
DQ7 |
DQ13 |
DQ4 |
VDD |
DQ10 |
DQ1 |
G |
AI04380
7/55
M28W640ECT, M28W640ECB
Figure 5. Block Addresses
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M28W640ECT |
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M28W640ECB |
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Top Boot Block Addresses |
Bottom Boot Block Addresses |
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3FFFFF |
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3FFFFF |
4 KWords |
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32 KWords |
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3FF000 |
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3F8000 |
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Total of 8 |
3F7FFF |
32 KWords |
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3F0000 |
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3F8FFF |
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4 KWord Blocks |
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Total of 127 |
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4 KWords |
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32 KWord Blocks |
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3F8000 |
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3F7FFF |
32 KWords |
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3F0000 |
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00FFFF |
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32 KWords |
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008000 |
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007FFF |
4 KWords |
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Total of 127 |
007000 |
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32 KWord Blocks |
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Total of 8 |
00FFFF |
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4 KWord Blocks |
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32 KWords |
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008000 |
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007FFF |
32 KWords |
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000FFF |
4 KWords |
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000000 |
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000000 |
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AI04386b |
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Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.
Figure 6. Protection Register Memory Map
PROTECTION REGISTER
8Ch
User Programmable OTP
85h
84h
Unique device number
81h
80h |
Protection Register Lock |
1 |
0 |
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AI05520b
8/55
M28W640ECT, M28W640ECB
SIGNAL DESCRIPTIONS
See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation.
Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level.
Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory.
Write Enable (W). The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable, E, or Write Enable, W, whichever occurs first.
Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the block cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the block can be locked or unlocked. (refer to Table 7, Read Protection Register and Protection Register Lock).
Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is minimized. After Reset all blocks are in the Locked
state. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode, but a negative transition of Chip Enable or a change of the address is required to ensure valid data outputs.
VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VDD and the Program Supply Voltage VPP can be applied in any order.
If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Table 15, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect on Program or Erase, however for Double or Quadruple Word Program the results are uncertain.
If VPP is in the range 11.4V to 12.6V it acts as a power supply pin. In this condition VPP must be
stable until the Program/Erase algorithm is completed (see Table 17 and 18).
VSS Ground. VSS is the reference for all voltage measurements.
Note: Each device in a system should have
VDD, VDDQ and VPP decoupled with a 0.1µF capacitor close to the pin. See Figure 8, AC Mea-
surement Load Circuit. The PCB trace widths should be sufficient to carry the required VPP program and erase currents.
9/55
M28W640ECT, M28W640ECB
BUS OPERATIONS
There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Reset. See Table 2, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figure 9, Read Mode AC Waveforms, and Table 16, Read AC Characteristics, for details of when the output becomes valid.
Read mode is the default state of the device when exiting Reset or after power-up.
Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first.
Table 2. Bus Operations
See Figures 10 and 11, Write AC Waveforms, and Tables 17 and 18, Write AC Characteristics, for details of the timing requirements.
Output Disable. The data outputs are high impedance when the Output Enable is at VIH.
Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished.
Automatic Standby. Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs will still output data if a bus Read operation is in progress.
Reset. During Reset mode when Output Enable is Low, VIL, the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid.
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VPP |
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Operation |
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E |
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G |
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W |
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RP |
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WP |
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DQ0-DQ15 |
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Bus Read |
VIL |
VIL |
VIH |
VIH |
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X |
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Don’t Care |
Data Output |
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Bus Write |
VIL |
VIH |
VIL |
VIH |
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X |
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VDD or VPPH |
Data Input |
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Output Disable |
VIL |
VIH |
VIH |
VIH |
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X |
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Don’t Care |
Hi-Z |
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Standby |
VIH |
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X |
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X |
VIH |
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Don’t Care |
Hi-Z |
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Reset |
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X |
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X |
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X |
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VIL |
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X |
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Don’t Care |
Hi-Z |
Note: X = VIL or VIH, VPPH = 12V ± 5%.
10/55
M28W640ECT, M28W640ECB
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time during, to monitor the progress of the operation, or the Program/Erase states. See Table 3, Command Codes, for a summary of the commands and see Appendix 22, Table 32, Write State Machine Current/Next, for a summary of the Command Interface.
The Command Interface is reset to Read mode when power is first applied, when exiting from Re-
set or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any
invalid combination of commands will reset the device to Read mode. Refer to Table 4, Commands, in conjunction with the text descriptions below.
Read Memory Array Command
The Read command returns the memory to its Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Subsequent read operations will read the addressed location and output the data. When a device Reset occurs, the memory defaults to Read mode.
Read Status Register Command
The Status Register indicates when a program or erase operation is complete and the success or failure of the operation itself. Issue a Read Status Register command to read the Status Register’s contents. Subsequent Bus Read operations read the Status Register at any address, until another command is issued. See Table 11, Status Register Bits, for details on the definitions of the bits.
The Read Status Register command may be issued at any time, even during a Program/Erase operation. Any Read attempt during a Program/ Erase operation will automatically output the content of the Status Register.
Read Electronic Signature Command
The Read Electronic Signature command reads the Manufacturer and Device Codes and the Block Locking Status, or the Protection Register.
The Read Electronic Signature command consists of one write cycle, a subsequent read will output the Manufacturer Code, the Device Code, the Block Lock and Lock-Down Status, or the Protection and Lock Register. See Tables 5, 6 and 7 for the valid address.
Table 3. Command Codes
Hex Code |
Command |
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01h |
Block Lock confirm |
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10h |
Program |
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20h |
Erase |
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2Fh |
Block Lock-Down confirm |
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30h |
Double Word Program |
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40h |
Program |
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50h |
Clear Status Register |
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56h |
Quadruple Word Program |
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60h |
Block Lock, Block Unlock, Block Lock- |
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Down |
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70h |
Read Status Register |
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90h |
Read Electronic Signature |
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98h |
Read CFI Query |
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B0h |
Program/Erase Suspend |
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C0h |
Protection Register Program |
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D0h |
Program/Erase Resume, Block Unlock |
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confirm |
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FFh |
Read Memory Array |
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Read CFI Query Command
The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Common Flash Interface, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface memory area.
Block Erase Command
The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error.
Two Bus Write cycles are required to issue the command.
■ The first bus cycle sets up the Erase command.
11/55
M28W640ECT, M28W640ECB
■The second latches the block address in the internal state machine and starts the Program/ Erase Controller.
If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts.
Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again.
During Erase operations the memory will accept the Read Status Register command and the Program/Erase Suspend command, all other commands will be ignored. Typical Erase times are given in Table 8, Program, Erase Times and Program/Erase Endurance Cycles.
See Appendix C, Figure 21, Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Erase command.
Program Command
The memory array can be programmed word-by- word. Two bus write cycles are required to issue the Program Command.
■The first bus cycle sets up the Program command.
■The second latches the Address and the Data to be written and starts the Program/Erase Controller.
During Program operations the memory will accept the Read Status Register command and the Program/Erase Suspend command. Typical Program times are given in Table 8, Program, Erase Times and Program/Erase Endurance Cycles.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.
See Appendix C, Figure 17, Program Flowchart and Pseudo Code, for the flowchart for using the Program command.
Double Word Program Command
This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH.
Three bus write cycles are necessary to issue the Double Word Program command.
■The first bus cycle sets up the Double Word Program Command.
■The second bus cycle latches the Address and the Data of the first word to be written.
■The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller.
12/55
Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.
See Appendix C, Figure 18, Double Word Program Flowchart and Pseudo Code, for the flowchart for using the Double Word Program command.
Quadruple Word Program Command
This feature is offered to improve the programming throughput, writing a page of four adjacent words in parallel.The four words must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at VPPH.
Five bus write cycles are necessary to issue the Quadruple Word Program command.
■The first bus cycle sets up the Quadruple Word Program Command.
■The second bus cycle latches the Address and the Data of the first word to be written.
■The third bus cycle latches the Address and the Data of the second word to be written.
■The fourth bus cycle latches the Address and the Data of the third word to be written.
■The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the block containing the memory location must be erased and reprogrammed.
See Appendix C, Figure 19, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command.
Clear Status Register Command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One bus write cycle is required to issue the Clear Status Register command.
The bits in the Status Register do not automatically return to ‘0’ when a new Program or Erase command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller.
M28W640ECT, M28W640ECB
During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array, Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Program, Double Word Program, Quadruple Word Program, Block Lock, Block Lock-Down or Protection Program commands will also be accepted. The block being erased may be protected by issuing the Block Protect, Block Lock or Protection Program commands. When the Program/ Erase Resume command is issued the operation will complete. Only the blocks not being erased may be read or programmed correctly.
During a Program/Erase Suspend, the device can be placed in a pseudo-standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL.
See Appendix C, Figure 20, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 22, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command.
Program/Erase Resume Command
The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the command. Once the command is issued subsequent Bus Read operations read the Status Register.
See Appendix C, Figure 20, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 22, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Resume command.
Protection Register Program Command
The Protection Register Program command is used to Program the 128 bit user One-Time-Pro- grammable (OTP) segment of the Protection Register. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’.
Two write cycles are required to issue the Protection Register Program command.
■The first bus cycle sets up the Protection Register Program command.
■The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller.
Read operations output the Status Register content after the programming has started.
The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 6, Protection Register Memory Map). Attempting to program a previously protected Protection Regis-
ter will result in a Status Register error. The protection of the Protection Register is not reversible.
The Protection Register Program cannot be suspended.
Block Lock Command
The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset.
Two Bus Write cycles are required to issue the Block Lock command.
■The first bus cycle sets up the Block Lock command.
■The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Table. 10 shows the protection status after issuing a Block Lock command.
The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Blocks Unlock command. Refer to the section, Block Locking, for a detailed explanation.
Block Unlock Command
The Blocks Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Blocks Unlock command.
■The first bus cycle sets up the Block Unlock command.
■The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Table. 10 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation.
Block Lock-Down Command
A locked block cannot be Programmed or Erased, or have its protection status changed when WP is
low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be
individually unlocked by the Block Unlock command.
Two Bus Write cycles are required to issue the Block Lock-Down command.
■The first bus cycle sets up the Block Lock command.
■The second Bus Write cycle latches the block address.
The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not
13/55
M28W640ECT, M28W640ECB
locked-down) state when the device is reset on power-down. Table. 10 shows the protection status after issuing a Block Lock-Down command.
Table 4. Commands
Refer to the section, Block Locking, for a detailed explanation.
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Cycles |
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Bus Write Operations |
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Commands |
1st Cycle |
2nd Cycle |
3rd Cycle |
4th Cycle |
5th Cycle |
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Op. |
Add |
Data |
Op. |
Add |
Data |
Op. |
Add |
Data |
Op. |
Add |
Data |
Op. |
Add |
Data |
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Read Memory |
1+ |
Write |
X |
FFh |
Read |
RA |
RD |
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Array |
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Read Status |
1+ |
Write |
X |
70h |
Read |
X |
SRD |
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Register |
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Read Electronic |
1+ |
Write |
X |
90h |
Read |
SA(2) |
IDh |
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Signature |
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Read CFI Query |
1+ |
Write |
X |
98h |
Read |
QA |
QD |
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Erase |
2 |
Write |
X |
20h |
Write |
BA |
D0h |
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Program |
2 |
Write |
X |
40h or |
Write |
PA |
PD |
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10h |
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Double Word |
3 |
Write |
X |
30h |
Write |
PA1 |
PD1 |
Write |
PA2 |
PD2 |
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Program(3) |
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Quadruple Word |
5 |
Write |
X |
56h(5) |
Write |
PA1 |
PD1 |
Write |
PA2 |
PD2 |
Write |
PA3 |
PD3 |
Write |
PA4 |
PD4 |
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Program(4) |
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Clear Status |
1 |
Write |
X |
50h |
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Register |
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Program/Erase |
1 |
Write |
X |
B0h |
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Suspend |
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Program/Erase |
1 |
Write |
X |
D0h |
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Resume |
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Block Lock |
2 |
Write |
X |
60h |
Write |
BA |
01h |
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Block Unlock |
2 |
Write |
X |
60h |
Write |
BA |
D0h |
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Block Lock-Down |
2 |
Write |
X |
60h |
Write |
BA |
2Fh |
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Protection |
2 |
Write |
X |
C0h |
Write |
PRA |
PRD |
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Register Program |
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Note: 1. X = Don’t Care, RA=Read Address, RD=Read Data, SRD=Status Register Data, ID=Identifier (Manufacture and Device Code), QA=Query Address, QD=Query Data, BA=Block Address, PA=Program Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data.
2.The signature addresses are listed in Tables 5, 6 and 7.
3.Program Addresses 1 and 2 must be consecutive Addresses differing only for A0.
4.Program Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1.
5.To be characterized.
Table 5. Read Electronic Signature
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Code |
Device |
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E |
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G |
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W |
A0 |
A1 |
A2-A7 |
A8-A21 |
DQ0-DQ7 |
DQ8-DQ15 |
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Manufacture |
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VIL |
VIL |
VIH |
VIL |
VIL |
0 |
Don’t Care |
20h |
00h |
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Code |
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Device Code |
M28W640ECT |
VIL |
VIL |
VIH |
VIH |
VIL |
0 |
Don’t Care |
48h |
88h |
|||||||||
M28W640ECB |
VIL |
VIL |
VIH |
VIH |
VIL |
0 |
Don’t Care |
49h |
88h |
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Note: RP = VIH.
14/55
M28W640ECT, M28W640ECB
Table 6. Read Block Lock Signature
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Block Status |
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E |
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G |
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W |
A0 |
A1 |
A2-A7 |
A8-A11 |
A12-A21 |
DQ0 |
DQ1 |
DQ2-DQ15 |
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Locked Block |
VIL |
VIL |
VIH |
VIL |
VIH |
0 |
Don’t Care |
Block Address |
1 |
0 |
00h |
|||||||
Unlocked Block |
VIL |
VIL |
VIH |
VIL |
VIH |
0 |
Don’t Care |
Block Address |
0 |
0 |
00h |
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Locked-Down |
VIL |
VIL |
VIH |
VIL |
VIH |
0 |
Don’t Care |
Block Address |
X (1) |
1 |
00h |
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Block |
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Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section. |
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Table 7. Read Protection Register and Lock Register
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Word |
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E |
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G |
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W |
A0-A7 |
A8-A21 |
DQ0 |
DQ1 |
DQ2 |
DQ3-DQ7 |
DQ8-DQ15 |
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Lock |
VIL |
VIL |
VIH |
80h |
Don’t Care |
0 |
OTP Prot. |
0 |
00h |
00h |
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data |
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Unique ID 0 |
VIL |
VIL |
VIH |
81h |
Don’t Care |
ID data |
ID data |
ID data |
ID data |
ID data |
|||||||
Unique ID 1 |
VIL |
VIL |
VIH |
82h |
Don’t Care |
ID data |
ID data |
ID data |
ID data |
ID data |
|||||||
Unique ID 2 |
VIL |
VIL |
VIH |
83h |
Don’t Care |
ID data |
ID data |
ID data |
ID data |
ID data |
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Unique ID 3 |
VIL |
VIL |
VIH |
84h |
Don’t Care |
ID data |
ID data |
ID data |
ID data |
ID data |
|||||||
OTP 0 |
VIL |
VIL |
VIH |
85h |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
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|||||||
OTP 1 |
VIL |
VIL |
VIH |
86h |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
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OTP 2 |
VIL |
VIL |
VIH |
87h |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
OTP 3 |
VIL |
VIL |
VIH |
88h |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
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OTP 4 |
VIL |
VIL |
VIH |
89h |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
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OTP 5 |
VIL |
VIL |
VIH |
8Ah |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
|||||||
OTP 6 |
VIL |
VIL |
VIH |
8Bh |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
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OTP 7 |
VIL |
VIL |
VIH |
8Ch |
Don’t Care |
OTP data |
OTP data |
OTP data |
OTP data |
OTP data |
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15/55
M28W640ECT, M28W640ECB
Table 8. Program, Erase Times and Program/Erase Endurance Cycles
Parameter |
Test Conditions |
|
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M28W640EC |
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Unit |
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Min |
Typ |
Max |
|||
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Word Program |
VPP = VDD |
|
10 |
200 |
µs |
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Double Word Program |
VPP = 12V ±5% |
|
10 |
200 |
µs |
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Quadruple Word Program |
VPP = 12V ±5% |
|
10 |
200 |
µs |
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|
Main Block Program |
VPP = 12V ±5% |
|
0.16/0.08 (1) |
5 |
s |
|
VPP = VDD |
|
0.32 |
5 |
s |
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Parameter Block Program |
VPP = 12V ±5% |
|
0.02/0.01 (1) |
4 |
s |
|
VPP = VDD |
|
0.04 |
4 |
s |
||
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|||||
Main Block Erase |
VPP = 12V ±5% |
|
1 |
10 |
s |
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VPP = VDD |
|
1 |
10 |
s |
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Parameter Block Erase |
VPP = 12V ±5% |
|
0.4 |
10 |
s |
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VPP = VDD |
|
0.4 |
10 |
s |
||
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|||||
Program/Erase Cycles (per Block) |
|
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100,000 |
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cycles |
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Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands respectively.
BLOCK LOCKING
The M28W640EC features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection.
■Lock/Unlock - this first level allows softwareonly control of block locking.
■Lock-Down - this second level requires hardware interaction before locking can be changed.
■VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks.
The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 10, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 23, shows a flowchart for the locking operations.
Reading a Block’s Lock Status
The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock
16/55
command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down.
The following sections explain the operation of the locking system.
Locked State
The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command.
Unlocked State
Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command.
M28W640ECT, M28W640ECB
Lock-Down State
Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down.
The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from pro- gram, erase and protection status changes. When WP=1 (VIH) the Lock-Down function is disabled (1,1,1) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be relocked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state.
Table 9. Block Lock Status
Locking Operations During Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress.
To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command.
If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete.
Locking operations cannot be performed during a program suspend. Refer to Appendix D, Command Interface and Program/Erase Controller State, for detailed information on which commands are valid during erase suspend.
Item |
Address |
Data |
|
|
|
|
|
Block Lock Configuration |
|
LOCK |
|
|
|
|
|
Block is Unlocked |
xx002 |
DQ0=0 |
|
|
|
||
Block is Locked |
DQ0=1 |
||
|
|||
|
|
|
|
Block is Locked-Down |
|
DQ1=1 |
|
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|
|
17/55