ST LSM330 User Manual

3D accelerometer and 3D gyroscope

LGA-24L (3x3.5x1 mm)

Features

■ Analog supply voltage: 2.4 V to 3.6 V

■ Digital supply voltage IOs: 1.8 V

■ Power-down and sleep modes

■ 2 Embedded programmable state machines

■ 3 independent acceleration channels and 3

angular rate channels

■ ±2 g/±4 g/±6 g/±8 g/±16 g selectable full scale

■ ±250/±500/±2000 dps selectable full scale

■ SPI/I

■ Embedded Temperature Sensor

■ Embedded FIFOs

■ ECOPACK

Application

■ GPS navigation systems

■ Impact recognition and logging

■ Gaming and virtual reality input devices

■ Motion activated functions

■ Intelligent power saving for handheld devices

■ Vibration monitoring and compensation

■ Free-fall detection

■ 6D orientation detection

Description

2

C serial interface

®

RoHS and “Green” compliant

LSM330

iNEMO inertial module:

Datasheet — target specification

The various sensing elements are manufactured
using specialized micromachining processes,
while the IC interfaces are developed using a
CMOS technology that allows the design of a
dedicated circuit which is trimmed to better match
the sensing element characteristics.

The LSM330 has an user-selectable full scale
acceleration range of ±2 g/±4 g/±6 g/±8 g/±16 g
and angular rate range of ±250/±500/±2000
d.The accelerometer and gyroscope sensors can
be either activated or separately put in Power­down/ sleep mode for applications optimized for
power saving.

The LSM330 is available in a plastic land grid
array (LGA) package.

Table 1. Device summary

Part number

LSM330 -40 to +85

LSM330TR -40 to +85

Temperature

range [°C]

Package Packing

LGA-24L

(3x3.5x1mm)

Tr a y

Tape

and reel

The LSM330 is a system-in-package featuring a
3D digital accelerometer with two embedded state
machines that can be programmed to implement
autonomous applications and a 3D digital
gyroscope.

ST’s family of MEMS sensor modules leverages
the robust and mature manufacturing processes
already used for the production of micromachined
accelerometers and gyroscopes.

July 2012 Doc ID 023426 Rev 1 1/76

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

www.st.com

76

Contents LSM330

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Linear acceleration sensor digital main blocks . . . . . . . . . . . . . . . . . . . . . 16

4.2.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.3 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.4 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.5 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.6 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.7 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.8 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3 Angular rate sensor digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.2 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.3 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3.4 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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4.3.5 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.6 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.7 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3.8 Level-sensitive / edge-sensitive data enable . . . . . . . . . . . . . . . . . . . . . 23

4.3.9 Level-sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.10 Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.2 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.1 WHO_AM_I_A (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.2 CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.3 CTRL_REG5_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8.4 CTRL_REG6_A (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.5 CTRL_REG7_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.6 STATUS_REG_A (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.7 OFF_X (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.8 OFF_Y (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.9 OFF_Z (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.10 CS_X (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.11 CS_Y (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.12 CS_Z (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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8.13 LC_L (16h) and LC_H (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.14 STAT (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.15 VFC_1 (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.16 VFC_2 (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.17 VFC_3 (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.18 VFC_4 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.19 THRS3 (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.20 OUT_X_L_A (28h) and OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . 45

8.21 OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . 45

8.22 OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . 45

8.23 FIFO_CTRL_REG_A (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

8.24 FIFO_SRC_REG_A (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.25 CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.26 STx_1 (40h-4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.27 TIM4_1 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.28 TIM3_1 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.29 TIM2_1 (52h - 53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.30 TIM1_1 (54h - 55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.31 THRS2_1 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.32 THRS1_1(57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.33 MASKB_1 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

8.34 MASKA_1(5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.35 SETT1 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

8.36 PR1 (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.37 TC1 (5Dh-5E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8.38 OUTS1 (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.39 PEAK1 (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.40 CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8.41 STx_2 (60h-6Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.42 TIM4_2 (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.43 TIM3_2 (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.44 TIM2_2 (72h - 73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8.45 TIM1_2 (74h - 75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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8.46 THRS2_2 (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.47 THRS1_2 (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.48 MASKB_2 (79h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

8.49 MASKA_2 (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.50 SETT2 (7Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8.51 PR2 (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.52 TC2 (7Dh-7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.53 OUTS2 (7Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

8.54 PEAK2 (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.55 DES2 (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.56 WHO_AM_I_G (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

8.57 CTRL_REG1_G (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

8.58 CTRL_REG2_G (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

8.59 CTRL_REG3_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.60 CTRL_REG4_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

8.61 CTRL_REG5_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8.62 REFERENCE_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.63 OUT_TEMP_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.64 STATUS_REG_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.65 OUT_X_L_G (28h), OUT_X_H_G (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.66 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.67 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.68 FIFO_CTRL_REG_G (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.69 FIFO_SRC_REG_G (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.70 INT1_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

8.71 INT1_SRC_G (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

8.72 INT1_THS_XH_G (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.73 INT1_THS_XL_G (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.74 INT1_THS_YH _G (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.75 INT1_THS_YL_G (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8.76 INT1_THS_ZH_G (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.77 INT1_THS_ZL_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8.78 INT1_DURATION_G (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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LSM330 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. LSM330 accelerometer state machines: sequence of state to execute an algorithm. . . . . 21

Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 14. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 33

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 33

Table 16. Linear Acceleration SAD+Read/Write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 17. Angular rate SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 18. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19. WHO_AM_I_A register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 20. CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 21. CTRL_REG4_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 22. CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 23. CTRL_REG5_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 24. CTRL_REG5_A Output Data Rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. CTRL_REG6_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 26. CTRL_REG6_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 27. CTRL_REG7_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 28. CTRL_REG7_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 29. STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 30. STATUS_REG_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 31. OFF_X default valu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 32. OFF_Y default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 33. OFF_Z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 34. CS_X default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 35. CS_Y default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 36. CS_Z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 37. LC_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 38. LC_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 39. STAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 40. STAT register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 41. VFC_1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 42. VFC_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 43. VFC_3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 44. VFC_4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 45. THRS3 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 46. FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 47. FIFO_CTRL_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 48. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Doc ID 023426 Rev 1 7/76

List of tables LSM330

Table 49. FIFO_SRC_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 50. IFO_SRC_REG_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 51. CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 52. CTRL_REG2_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 53. STx_1 registers default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 54. TIM4_1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 55. TIM4_1 default valu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 56. TIM3_1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 57. TIM2_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 58. TIM2_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 59. TIM1_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 60. TIM1_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 61. THRS2_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 62. THRS1_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 63. MASKB_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 64. MASKB_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 65. MASKA_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 66. MASKA_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 67. SETT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 68. SETT1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 69. PR1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 70. PR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 71. TC1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 72. TC1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 73. OUTS1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 74. OUTS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 75. PEAK1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 76. CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 77. CTRL_REG3_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 78. STx_2 registers default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 79. TIM4_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 80. TIM3_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 81. TIM2_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 82. TIM2_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 83. TIM1_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 84. TIM1_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 85. THRS2_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 86. THRS1_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 87. MASKB_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 88. MASKB_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 89. MASKA_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 90. MASKA_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 91. SETT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 92. SETT2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 93. PR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 94. PR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 95. TC2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 96. TC2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 97. OUTS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 98. OUTS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 99. PEAK2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 100. DES2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

8/76 Doc ID 023426 Rev 1

LSM330 List of tables

Table 101. WHO_AM_I_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 102. CTRL_REG1_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 103. CTRL_REG1_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 104. DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 105. Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 106. CTRL_REG2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 107. CTRL_REG2_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 108. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 109. High-pass filter cut-off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 110. CTRL_REG3_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 111. CTRL_REG3_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 112. CTRL_REG4_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 113. CTRL_REG4_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 114. CTRL_REG5_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 115. CTRL_REG5_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 116. REFERENCE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 117. REFERENCE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 118. OUT_TEMP_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 119. OUT_TEMP_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 120. STATUS_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 121. STATUS_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 122. FIFO_CTRL_REG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 123. FIFO_CTRL_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 124. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 125. FIFO_SRC_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 126. FIFO_SRC_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 127. INT1_CFG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 128. INT1_CFG_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 129. INT1_SRC_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 130. INT1_SRC_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 131. INT1_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 132. INT1_THS_XH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 133. INT1_THS_XL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 134. INT1_THS_XL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 135. INT1_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 136. INT1_THS_YH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 137. INT1_THS_YL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 138. INT1_THS_YL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 139. INT1_THS_ZH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 140. INT1_THS_ZH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 141. INT1_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 142. INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 143. INT1_DURATION_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 144. INT1_DURATION_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 145. LGA (3.5x3x1 mm) 24 lead mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 146. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Doc ID 023426 Rev 1 9/76

List of figures LSM330

List of figures

Figure 1. LSM330 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Angular rate sensor digital block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0) . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. LSM330 electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Multiple-byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 20. INT1_Sel and Out_Sel configuration block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 21. Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 22. Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 23. LGA 3.5x3x1 24 leads drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

10/76 Doc ID 023426 Rev 1

LSM330 Block diagram and pin description

Y+

Z+

Y-

Z-

X+

X-

MUX

I (a)

+

-

CHARGE

AMPLIFIER

Sensing Block Sensing Interface

I2C/SPI

I (

Ω)

Drive+

Drive-

Feedback+

Feedback-

DEMODULATOR

VOLTAGE

AUTOMATI C

GAIN

CONTROL

LOW-PASS

FILTER

GAIN

AMPLIFIER

ANALOG
CONDITION ING

CONTROL LOGIC

&

INTERRUPT GEN.

CLOCK

TRIMMING

CIRCUITS

REFERENCE

GENERATOR

PHASE

+

-

CHARGE

AMPLIFIER

Y+

Z+

Y-

Z-

X+

X-

MUX

CS_G

SDA/SDI_A/G

SDO_G

INT1_A

INT2_A

INT1_G

DEN_G

DRDY_G/INT2_G

CS_A

SDO_A

SCL_A/G

ADC1

DIGITAL
FILTER

LOW-PASS

FILTER

ADC2

STATE

MACHINES

AND

CONTROL

LOGIC

AM14723V1

1 Block diagram and pin description

1.1 Block diagram

Figure 1. LSM330 block diagram

Doc ID 023426 Rev 1 11/76

Block diagram and pin description LSM330

1

X

6

13

18

VDD_IO

VDD

VDD

VDD

CAP

GND

GND

RES

SDO_A

CS_G

CS_A

DRDY_G/INT2_G

INT1_G

INT1_A

INT2_A

DEN_G

RES

RES

RES

RES

SCL_A/G

VDD_IO

SDA/SDI_A/G

SDO_G

(BOTTOM VIEW)

1

X

+Ω

Z

+Ω

X

+Ω

Y

Y

1

X

Z

DIRECTION OF
DETECTABLE
ACCELERATIONS

DIRECTION OF
DETECTABLE
ANGULAR RATE

Z

Y

X

AM14724V1

1.2 Pin description

Figure 2. Pin connection

Table 2. Pin description

Pin# Name Function

(1)

1 Vdd_IO

2SCL_A/GI

3 Vdd_IO

4SDA/SDI_A/G

5SDO_G

6SDO_A

7CS_G

8CS_A

12/76 Doc ID 023426 Rev 1

9

DRDY_G/

INT2_G

Power supply for IO pins

2

C serial clock (SCL)/SPI serial port clock (SPC)

(1)

Power supply for IO pins

I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)

Gyroscope:
SPI serial data output (SDO)

2

I

C least significant bit of the device address (SA0)

Accelerometer:
SPI serial data output (SDO)

2

I

C least significant bit of the device address (SA0)

Gyroscope: SPI enable

2

C/SPI mode selection (1: SPI idle mode / I2C communication

I
enabled; 0: SPI communication mode / I

Accelerometer: SPI enable

2

I

C/SPI mode selection (1: SPI idle mode / I2C communication

enabled; 0: SPI communication mode / I

Gyroscope Data Ready/FIFO Interrupt
(Watermark/Overrun/Empty)

2

C disabled)

2

C disabled)

LSM330 Block diagram and pin description

Table 2. Pin description (continued)

Pin# Name Function

10 INT1_G Gyroscope interrupt signal

11 INT1_A Accelerometer interrupt1 signal

12 INT2_A Accelerometer interrupt2 signal

13 DEN_G Gyroscope Data Enable

14 Res Reserved. Connect to GND

15 Res Reserved. Connect to GND

16 Res Reserved. Connect to GND

17 Res Reserved. Connect to GND

18 Res Reserved. Connect to GND

19 GND 0 V supply

20 GND 0 V supply

21 CAP Connect to GND with ceramic capacitor

22 Vdd

23 Vdd

24 Vdd

(3)

(3)

(3)

Power supply

Power supply

Power supply

(2)

1. 100 nF filter capacitor recommended.

2. 10 nF (+/- 10%), 25V. 1nF minimum value has to be guaranteed under 11V bias condition1.

3. 100 nF plus 10 µF capacitors recommended.

Doc ID 023426 Rev 1 13/76

Module specifications LSM330

2 Module specifications

2.1 Mechanical characteristics

@ Vdd = 3V, T = 25 °C unless otherwise noted

Table 3. Mechanical characteristics

Symbol Parameter Test conditions Min. Typ.

FS bit set to 000 ±2.0

FS bit set to 001 ±4.0

LA_FS

G_FS

LA_So Linear acceleration sensitivity

G_So Angular rate sensitivity

LA_TyOff

G_TyOff

Top Operating temperature range -40 +85 °C

1. Typical specifications are not guaranteed.

2. Verified by wafer level test and measurement of initial offset and sensitivity.

3. Typical zero-g level offset value after MSL3 preconditioning.

4. Offset can be eliminated by enabling the built-in high-pass filter.

Linear acceleration measurement

(2)

range

Angular rate
measurement range

Linear acceleration typical zero-g
level offset accuracy

Angular rate typical zero-rate

(4)

level

(3)

(3)

FS bit set to 010 ±6.0

FS bit set to 011 ±8.0

FS bit set to 100 ±16.0

FS bit set to 00 ±250

FS bit set to 10 ±2000

FS bit set to 000 0.061

FS bit set to 001 0.122

FS bit set to 010 0.183

FS bit set to 011 0.244

FS bit set to 100 0.732

FS = ±250 dps 8.75

FS = ±500 dps 17.50

FS = ±2000 dps 70

FS bit set to 000 ±60 mg

FS = 250 dps ±10

FS = 2000 dps ±25

(a)

(1)

Max. Unit

g

dpsFS bit set to 01 ±500

mg/digit

mdps/

digit

dpsFS = 500 dps ±15

a. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.4 V to 3.6 V.

14/76 Doc ID 023426 Rev 1

LSM330 Module specifications

2.2 Electrical characteristics

@ Vdd = 3 V, T = 25 °C unless otherwise noted

Table 4. Electrical characteristics

Symbol Parameter Test conditions Min. Typ.

Vdd Supply voltage 2.4 3.6 V

Vdd_IO Power supply for I/O 1.71 Vdd+0.1 V

(1)

Max. Unit

LA_Idd

LA_IddPdn

G_Idd

G_IddLowP

G_IddPdn

VIH Digital high level input voltage 0.8*Vdd_IO V

VIL Digital low level input voltage 0.2*Vdd_IO V

VOH High level output voltage 0.9*Vdd_IO V

VOL Low level output voltage 0.1*Vdd_IO V

Top Operating temperature range -40 +85

1. Typical specifications are not guaranteed.

2. Sleep mode introduces a faster turn-on time compared to Power-down mode.

Accelerometer current
consumption in Normal mode

Accelerometer current
consumption in Power-down
mode

Gyroscope current
consumption in Normal mode

Gyroscope supply current
in Sleep mode

Gyroscope current
consumption in Power-down
mode

(2)

1.6 kHz ODR 250

3.125 Hz ODR 10

1µA

6.1 mA

2mA

5µA

µA

°C

2.3 Temperature sensor characteristics

@ Vdd = 3V, T = 25 °C unless otherwise noted

Table 5. Temperature sensor characteristics

Symbol Parameter Test condition Min. Typ.

TSDr

TODR Temperature refresh rate 1 Hz

Top Operating temperature range -40 +85 °C

1. Typical specifications are not guaranteed.

Temperature sensor output
change vs. temperature

-

b. The product is factory calibrated at 3.0 V.

Doc ID 023426 Rev 1 15/76

(b)

(1)

-1 °C/digit

Max. Unit

Module specifications LSM330

SPC

CS

SD I

SD O

t

su (CS)

t

v(SO)

t

h(SO )

t

h(SI)

t

su (SI)

t

h(CS)

t

dis(SO)

t

c(SPC )

MSB IN

MSB OUT

LSB OUT

LSB IN

(2)

(2)

(2)

(2)

(2)

(2)

(2)

(2)

2.4 Communication interface characteristics

2.4.1 SPI - serial peripheral interface

Subject to general operating conditions for Vdd and TOP.

Table 6. SPI slave timing values

(2)

Symbol

Parameter

(1)

tc(SPC) SPI clock cycle 100 ns

fc(SPC) SPI clock frequency 10 MHz

tsu(CS) CS setup time 6

th(CS) CS hold time 8

tsu(SI) SDI input setup time 5

th(SI) SDI input hold time 15

tv(SO) SDO valid output time 50

th(SO) SDO output hold time 9

tdis(SO) SDO output disable time 50

Val ue

Unit

Min Max

ns

1. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.

2. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not
tested in production.

(c)

Figure 3. SPI slave timing diagram

2. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.

c. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

16/76 Doc ID 023426 Rev 1

LSM330 Module specifications

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2.4.2 I2C - inter IC control interface

Subject to general operating conditions for Vdd and TOP.

Table 7. I2C slave timing values

Symbol Parameter

(1)

I2C standard mode

(1)

I2C fast mode

Min. Max. Min. Max.

(1)

Unit

f

(SCL)

t

w(SCLL)

t

w(SCLH)

t

su(SDA)

t

h(SDA)

t

r(SDA) tr(SCL)

t

f(SDA) tf(SCL)

t

h(ST)

t

su(SR)

t

su(SP)

t

w(SP:SR)

1. SCL (SCL_A/G pin), SDA (SDA_A/G pin).

2. Cb = total capacitance of one bus line, in pF

Figure 4. I

SCL clock frequency 0 100 0 400 KHz

SCL clock low time 4.7 1.3

SCL clock high time 4.0 0.6

SDA setup time 250 100 ns

SDA data hold time 0.01 3.45 0 0.9 µs

SDA and SCL rise time 1000

SDA and SCL fall time 300

START condition hold time 4 0.6

Repeated START condition
setup time

STOP condition setup time 4 0.6

Bus free time between STOP
and START condition

2

C slave timing diagram

(d)

20 + 0.1C

20 + 0.1C

4.7 0.6

4.7 1.3

b

b

(2)

(2)

µs

300

ns

300

µs

d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

Doc ID 023426 Rev 1 17/76

Module specifications LSM330

This is a mechanical shock sensitive device, improper handling can cause permanent
damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to
the part.

2.5 Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 8. Absolute maximum ratings

Symbol Ratings Maximum value Unit

Vdd Supply voltage -0.3 to 4.8 V

Vdd_IO I/O pins supply voltage -0.3 to 4.8 V

(1)

Vin

Input voltage on any control pin (SCL_A/G, SDA_A/G,
SDO_A, SDO_G, CS_A, CS_G, DEN_G)

-0.3 to Vdd_IO +0.3 V

3000 g for 0.5 ms

A

POW

Acceleration (any axis, powered, Vdd = 3 V)

10000 g for 0.1 ms

3000 g for 0.5 ms

A

T

UNP

T

STG

Acceleration (any axis, unpowered)

10000 g for 0.1 ms

Operating temperature range -40 to +85 °C

OP

Storage temperature range -40 to +125 °C

ESD Electrostatic discharge protection 2 (HBM) kV

1. Supply voltage on any pin should never exceed 4.8 V.

18/76 Doc ID 023426 Rev 1

LSM330 Terminology

3 Terminology

3.1 Sensitivity

Linear acceleration sensitivity can be determined e.g. by applying 1 g acceleration to the
device. Because the sensor can measure DC accelerations, this can be done easily by
pointing the selected axis towards the ground, noting the output value, rotating the sensor
180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g
acceleration is applied to the sensor. Subtracting the larger output value from the smaller
one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value
changes very little over temperature and over time. The sensitivity tolerance describes the
range of sensitivities of a large number of sensors.

Angular Rate Sensitivity describes the angular rate gain of the sensor and can be
determined by applying a defined angular velocity to the device. This value changes very
little overtemperature and also very little overtime.

3.2 Zero-g and zero rate level

Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output
signal from the ideal output signal if no acceleration is present. A sensor in a steady state on
a horizontal surface will measure 0 g on both the X axis and Y axes, whereas the Z axis will
measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content
of OUT registers 00h, data expressed as 2’s complement number). A deviation from the
ideal value in this case is called zero-g offset.

Offset is to some extent a result of stress to MEMS sensor and therefore the offset can
slightly change after mounting the sensor onto a printed circuit board or exposing it to
extensive mechanical stress. Offset changes little over temperature, see “Linear
acceleration zero-g level change vs. temperature” in Ta bl e 3 . The zero-g level tolerance
(TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.

Angular rate zero-rate level describes the actual output value if there is no angular rate
present. zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the
sensor and therefore zero-rate level can slightly change after mounting the sensor onto a
printed circuit board or after exposing it to extensive mechanical stress. This value changes
very little overtemperature and overtime.

Doc ID 023426 Rev 1 19/76

Functionality LSM330

4 Functionality

The LSM330 is a system-in-package featuring a 3D digital accelerometer with two
embedded state machines and a 3D digital gyroscope, together with two FIFO memory
block available to manage linear acceleration and angular rate data.

The device includes specific sensing elements and two IC interfaces capable to measuring
both the acceleration and angular rate applied to the module and to provide a signal to
external applications through an SPI/I

The various sensing elements are manufactured using specialized micromachining
processes, while the IC interfaces are developed using a CMOS technology that allows the
design of a dedicated circuit which is trimmed to better match the sensing element
characteristics.

4.1 Power modes

The linear acceleration sensor and the angular rate sensor can be either activated or
separately set in Power-down/ sleep mode for applications optimized for power saving.

The acceleration sensor operating modes can be selected between normal or power-down
trough the CTRL_REG5_A (20h); the angular rate sensor operating mode can be selected
among normal power-down or sleep mode, through CTRL_REG1_G (20h).

2

C serial interface.

4.2 Linear acceleration sensor digital main blocks

4.2.1 State machine

The LSM330 embeds two state machines able to run a user defined program.

The program is composed by a set of instructions that define the transition to successive
states. Conditional branches are possible.

From each state (n) it is possible to have transition to next state (n+1) or to reset state.
Transition to Reset Point happens when “RESET condition” is true; Transition to next step
happens when “NEXT condition” is true.

Interrupt is triggered when Output/Stop/Continue state is reached.

Each State machine allows to implement in a flexible way gesture recognition, Free Fall,
Wake-up, 4D/6D orientation, pulse counter and step recognition, click/double click,
shake/double shake, face up/face down, turn/double turn:

– Code and parameters are loaded by host into dedicated memory areas for the

state program

– State program with timing based on ODR or decimated time

– Possibiliy of conditional branches

20/76 Doc ID 023426 Rev 1

LSM330 Functionality

State 1

State 2

next

State 3

next

State n

next

reset

reset

reset

reset

START

OUTPUT/STOP/CONTINUE

INT set

AM14725v1

Table 9. LSM330 accelerometer state machines: sequence of state to execute an

algorithm

4.2.2 FIFO

LSM330 embeds 32 slots of data FIFO for each of the three acceleration output

channels: X, Y and Z. This allows consistent power saving for the system, since the host
processor does not need to continuously poll data from the sensor, but it can wake up only
when needed and burst the significant data out from the FIFO. In order to use FIFO it is
necessary to enable FIFO_EN bit in CTRL_REG7_A (25h) register.

FIFO buffer can work accordingly in five different modes: Bypass mode, FIFO mode, Stream
mode, Stream-to-FIFO mode and Bypass-to-Stream mode. Each mode is selected by
FMODE [2:0] bits in the FIFO_CTRL_REG_A (2Eh) register. Programmable watermark
level, FIFO empty or FIFO overrun events can be enabled to generate dedicated interrupts
on the INT1_A/INT2_A pin (configured through INT2_EN and INT1_EN bits in the

CTRL_REG4_A (23h) register).

When FIFO is empty, EMPTY bit in FIFO_SRC_REG_A (2Fh) is equal to '1' and no samples
are available.

If the application requires a lower number of samples a programmable watermark level can
be set. In FIFO_SRC_REG_A (2Fh) WTM bit is high if a new data arrives and FSS [4:0] bit
in FIFO_SRC_REG_A (2Fh) is greater than or equal to WTMP [4:0] bit in

FIFO_CTRL_REG_A (2Eh) register. In FIFO_SRC_REG_A (2Fh) WTM bit goes to '0' if

reading X, Y, Z data slot from FIFO and FSS [4:0] bit in FIFO_SRC_REG_A (2Fh) is minor
than or equal to WTMP [4:0] bit in FIFO_CTRL_REG_A (2Eh) register.

When FIFO is completely filled, OVRN_FIFO bit in FIFO_SRC_REG_A (2Fh) is equal to '1'
and FIFO slot is overwritten.

Doc ID 023426 Rev 1 21/76

Functionality LSM330

4.2.3 Bypass mode

In Bypass mode, the FIFO is not operational and it remains empty. For each channel only
the first address is used. The remaining FIFO slots are empty.

Bypass mode must be used in order to reset the FIFO buffer when a different mode is
operating (i.e. FIFO mode).

4.2.4 FIFO mode

In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels
until it is full (32 samples set stored). When the FIFO is full it stops collecting data from the
input channels and the FIFO content remains unchanged.

An overrun interrupt can be enabled, P1_OVERRUN = '1' in CTRL_REG7_A (25h) register,
in order to be raised when the FIFO stops collecting data. When overrun interrupt occurs,
the first data has been overwritten and the FIFO stops collecting data from the input
channels.

At the end of the reading procedure it is necessary to transit from Bypass mode to reset
FIFO content. . After this reset command it is possible to restart FIFO mode writing FMODE
[2:0] the value '001' in FIFO_CTRL_REG_A (2Eh) register.

FIFO buffer can memorize 32 X, Y and Z data but the depth of the FIFO can be reduced by
a programmable watermark. In order to enable FIFO watermark, WTM_EN bit in

CTRL_REG7_A (25h) is high and the FIFO depth is set in WTMP [4:0] bits in
FIFO_CTRL_REG_A (2Eh) register. The watermark interrupt can be enable in INT1_A pad

if P1_WTM bit in CTRL_REG7_A (25h) register is enable.

4.2.5 Stream mode

In Stream mode FIFO continues filling data from X, Y, and Z accelerometer channels, when
the buffer is full (32 samples set stored) the FIFO buffer index restarts from the beginning
and older data is replaced by the current. The oldest values continue to be overwritten until
a read operation makes free FIFO slots available.

An overrun interrupt can be enabled, P1_OVERRUN = '1' in CTRL_REG7_A (25h) register,
in order to read the whole FIFO content at once. If in the application it is mandatory not to
lose data and it is not possible to read at least one sample for each axis within one ODR
period, a watermark interrupt can be enabled in order to read partially the FIFO and let free
memory slots for data incoming.

Setting the WTMP [4:0] bit in FIFO_CTRL_REG_A (2Eh) register to N value, the number of
X, Y and Z data samples that should be read at watermark interrupt rising is up to (N+1).

In the latter case reading all FIFO content before an overrun interrupt has occurred, the first
data read is equal to the last already read in previous burst, so the number of new data
available in FIFO depends on previous reading (see FIFO_SRC_REG_A (2Fh)) .

At the end of the reading procedure it is necessary to transit from Bypass mode to reset
FIFO content.

4.2.6 Stream-to-FIFO mode

In Stream-to-FIFO mode FIFO behavior changes according to interrupt generated by the
configuration of the two state machine by INT_SM1and INT_SM2 bits in STAT (18h) register.

22/76 Doc ID 023426 Rev 1

LSM330 Functionality

ADC

LPF1

HPF

0

1

HPen

LPF2

10
11

01

00

Out_Sel

DataReg

00

11

10

01

Interrupt

generator

INT_Sel

I2C
SPI

INT1

SCR REG

CONF REG

FIFO

32x16x3

AM07230v1

When INT_SM1, INT_SM2 bits in STAT (18h) register are equal to '1' FIFO operates in FIFO
mode, when INT_SM1, INT_SM2 bit in STAT (18h) register are equal to '0' FIFO operates in
Stream mode.

4.2.7 Bypass-to-stream mode

In Bypass-to-stream mode, the FIFO starts operating in Bypass mode and once a trigger
event occurs (STAT (18h) the FIFO starts operating in Stream mode.

4.2.8 Retrieve data from FIFO

FIFO data is read through OUT_X_L_A (28h) and OUT_X_H_A (29h), OUT_Y_L_A (2Ah)

and OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh). When the FIFO is

in Stream, Trigger or FIFO mode, a read operation to the OUT_X_L_A (28h) and

OUT_X_H_A (29h), OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) or OUT_Z_L_A (2Ch) and
OUT_Z_H_A (2Dh) registers provides the data stored in the FIFO. Each time data is read

from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L_A (28h) and

OUT_X_H_A (29h), OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch)
and OUT_Z_H_A (2Dh) registers and both single read and read_burst operations can be

used.

4.3 Angular rate sensor digital main blocks

Figure 5. Angular rate sensor digital block diagram

Doc ID 023426 Rev 1 23/76

Functionality LSM330

l

x

0

y

z

0

y

0

x

1

y

1

z

1

x

2

y

2

z

2

x

31

y

31

z

31

xi,yi,z

i

empty

AM07231v1

4.3.1 FIFO

LSM330 embeds a 32 slots of 16 bit data FIFO buffer for each of the three output channels,
yaw, pitch and roll. This allows a consistent power saving for the system, since the host
processor does not need to continuously poll data from the sensor, but it can wake up only
when needed and burst the significant data out from the FIFO.

In order to use FIFO it is necessary to enable FIFO_EN bit in CTRL_REG5_G (24h)
register. FIFO buffer can work accordingly to five different modes: Bypass mode, FIFO
mode, Stream mode, Bypass-to-Stream mode and Stream-to-FIFO mode. Each mode is
selected by the FM[2:0] bits into the FIFO_CTRL_REG_G (2Eh) register.

Programmable watermark level, FIFO empty or FIFO full events can be enabled to generate
dedicated interrupts on DRDY_G/INT2_G pin (configuration through CTRL_REG3_G (22h))
and event detection information are available into FIFO_SRC_REG_G (2Fh). Watermark
level can be configurated to WTM[4:0] bits into FIFO_CTRL_REG_G (2Eh).

4.3.2 Bypass mode

In bypass mode, the FIFO is not operational and for this reason it remains empty. As

described in the next figure, for each channel only the first address is used. The remaining
FIFO slots are empty. When a new data is available the old one is overwritten.

Figure 6. Bypass mode

4.3.3 FIFO mode

In FIFO mode, data from yaw, pitch and roll channels are stored into the FIFO. A watermark
interrupt can be enabled (I2_WTM bit into CTRL_REG3_G (22h)) in order to be raised when
the FIFO is filled to the level specified into the WTM[4:0] bits of FIFO_CTRL_REG_G (2Eh)
register. The FIFO continues filling until it is full (32 slots of 16 data for Yaw, Pitch and Roll).
When full, the FIFO stops collecting data from the input channels. To restart collecting data
it is needed to write FIFO_CTRL_REG_G (2Eh) back to Bypass mode. FIFO mode is
represented in the following figure.

24/76 Doc ID 023426 Rev 1

LSM330 Functionality

x

0

y

z

0

y

0

x

1

y

1

z

1

x

2

y

2

z

2

x

31

y

31

z

31

xi,yi,z

i

AM07232v1

Figure 7. FIFO mode

4.3.4 Stream mode

In the stream mode, data from yaw, pitch and roll measurement are stored into the FIFO. A
watermark interrupt can be enabled and set as in the FIFO mode. FIFO continues filling until
it is full (32 slots of 16 data for Yaw, Pitch and Roll). When full, the FIFO discards the older
data as the new arrive. Programmable watermark level events can be enabled to generate
dedicated interrupts on DRDY_G/INT2_G pin (configuration through CTRL_REG3_G

(22h)). Stream mode is represented in the following figure.

Doc ID 023426 Rev 1 25/76

Functionality LSM330

Figure 8. Stream mode

xi,yi,z

i

x

x

4.3.5 Bypass-to-stream mode

x

0

x

1

x

2

30

31

y

0

y

1

y

2

y

30

y

31

z

0

z

1

z

2

z

30

z

31

AM07234v1

In Bypass-to-stream mode, the FIFO starts operating in Bypass mode and once a trigger
event occurs (related to INT1_CFG_G (30h) register events) the FIFO starts operating in
Stream mode. Refer the following figure.

Figure 9. Bypass-to-stream mode

xi,yi,z

Empty

i

x

x

x

x

y

y

0

y

1

y

2

y

31

z

i

0

1

2

31

0

z

1

z

2

z

31

Bypass mode

Trigger event

xi,yi,z

i

x

x

x

x

x

y

0

1

2

30

31

0

y

1

y

2

y

30

y

31

Stream mode

z

0

z

1

z

2

z

30

z

31

AM07235v1

26/76 Doc ID 023426 Rev 1

LSM330 Functionality

4.3.6 Stream-to-FIFO mode

In Stream-to-FIFO mode, data from yaw, pitch and roll measurement are stored into the
FIFO. A watermark interrupt can be enabled on pin DRDY_G/INT2_G setting I2_WTM bit
into CTRL_REG3_G (22h) in order to be raised when the FIFO is filled to the level specified
into the WTM [4:0] bits of FIFO_CTRL_REG_G (2Eh). The FIFO continues filling until it's full
(32 slots of 16 data for Yaw, Pitch and Roll). When full, the FIFO discards the older data as
the new arrive. Once trigger event occurs (related to INT1_CFG_G (30h) register events),
the FIFO starts operating in FIFO mode. Refer to the following figure.

Figure 10. Trigger stream mode

xi,yi,z

i

x

0

x

1

x

2

x

30

x

31

y

0

y

1

y

2

y

30

y

31

Stream Mode

4.3.7 Retrieve data from FIFO

FIFO data is read through OUT_X_L_G (28h), OUT_X_H_G (29h) and OUT_Y_L_G (2Ah),

OUT_Y_H_G (2Bh) and OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh). When the FIFO is in

stream, stream-to-FIFO or FIFO mode, a read operation to the OUT_X_L_G (28h),

OUT_X_H_G (29h), OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) and OUT_Z_L_G (2Ch),
OUT_Z_H_G (2Dh) regiters provides the data stored into the FIFO.

xi,yi,z

z

0

z

1

z

2

z

30

z

31

i

x

x

x

x

y

y

0

y

1

y

2

y

31

z

i

0

1

2

31

0

z

1

z

2

z

31

FIFO Mode

Trigger event

AM07236v1

Each time data is read from the FIFO, the oldest Pitch, Roll and Yaw data are placed into the

OUT_X_L_G (28h), OUT_X_H_G (29h), OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) and
OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) registers and both single read and read_burst (X, Y

and Z with autoincremental address) operations can be used. When data included into
OUT_Z_H_G (2Dh) is read, the system restarts to read information from OUT_X_L_G
(28h).

4.3.8 Level-sensitive / edge-sensitive data enable

The LSM330 allows external trigger level recognition through the enabling of the EXTRen
and LVLen bits in the CTRL_REG2_G register. Two different modes can be used: Level­sensitive or Edge-sensitive trigger.

Doc ID 023426 Rev 1 27/76

Functionality LSM330

xi(15-1)

xi,yi,z

i

D
E
N

y

i

(15-0)

Z

i

(15-0)

x

i-N+1

D
E
N

(15-1)

y

i-N+1

(15-0)

z

i-N+1

(15-0)

xi(15-0)

xi,yi,z

i

D
E
N

y

i

(15-1)

Z

i

(15-0)

xi(15-0)

xi,yi,z

i

D
E
N

y

i

(15-0)

Z

i

(15-1)

x

i-N+1

D
E
N

(15-0)

y

i-N+1

(15-0)

z

i-N+1

(15-1)

x

i-N+1

D
E
N

y

i-N+1

Z

i-N+1

(15-0)

(15-1)

(15-0)

Level-sensitive
Trigger enabled
on X-Axis

Level-sensitive
Trigger enabled
on Y-axis

Level-sensitive
Trigger enabled
on Z-axis

Xen=1,Yen=Zen=0

Yen=1, Xen=Zen=0

Zen=1,

Xen=Yen=0

AM10162V1

Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0)

4.3.9 Level-sensitive trigger stamping

4.3.10 Edge-sensitive trigger

Once enabled, DEN level replaces the LSb of the X, Y or Z axes, configurable through the
Xen, Yen, Zen bits in the CTRL_REG1_G register. Data is stored in the FIFO with the
internally-selected ODR.

Once enabled by setting EXTRen = 1, FIFO is filled with the pitch, roll and yaw data on the
rising edge of the DEN input signal. When selected ODR is 800 Hz, the maximum DEN
sample frequency is f

DEN

= 1/T

DEN

= 400 Hz.

28/76 Doc ID 023426 Rev 1

LSM330 Functionality

Figure 12. Edge-sensitive trigger

4.4 Factory calibration

The IC interface is factory calibrated for sensitivity and zero level. The trimming values are
stored in the device in non volatile memory. Any time the device is turned on, the trimming
parameters are downloaded to the registers to be used during normal operation. This allows
use of the device without further calibration.

Doc ID 023426 Rev 1 29/76

Application hints LSM330

RES

GND

GND

CAP

VDD

VDD

VDD

VDD_IO

RES

RES

RES

RES

(TOP VIEW)

1

316

18

DEN_G

INT2_A

INT1_A

INT_G

DRDY_G/INT2_G

CS_A

CS_G

SDO_A

SCL_A/G

VDD_IO

SDA/SDI_A/G

SDO_G

10nF(25V)

*C1

100 nF

GND

GND

10 µF

C3 C4

Vdd

Vdd_IO

GND

100 nF

C2

GND

GND

* C1 must guarantee 1 nF value under
11 V bias condition

Vdd_IO

I2C configuration

SCL

SDA

Rpu= 10kOhmRpu

Pull-up to be added

AM14726V1

5 Application hints

Figure 13. LSM330 electrical connection

5.1 External capacitors

The device core is supplied through the Vdd line. Power supply decoupling capacitors (C2,
C3=100 nF ceramic, C4=10 µF Al) should be placed as near as possible to the supply pin of
the device (common design practice).

All voltage and ground supplies must be present at the same time to achieve proper
behavior of the IC (refer to Figure 13).

30/76 Doc ID 023426 Rev 1

LSM330 Application hints

The functionality of the device and the measured acceleration/angular rate data is
selectable and accessible through the SPI/I

The functions, the threshold and the timing of the two interrupt pins for each sensor can be
completely programmed by the user through the SPI/I

5.2 Soldering information

The LGA package is compliant with ECOPACK®, RoHS and “Green” standards. It is
qualified for soldering heat resistance according to JEDEC J-STD-020D.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com/mems

2

C interface.

2

C interface.

.

Doc ID 023426 Rev 1 31/76

Digital interfaces LSM330

6 Digital interfaces

The registers embedded in the LSM330 may be accessed through both the I2C and SPI
serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.

To select/exploit the I

Table 10. Serial interface pin description

Pin name Pin description

2

C interface, the CS line must be tied high (i.e. connected to Vdd_IO).

CS_A

CS_G

SCL_A/G

SDA_A/G

SDO_A
SDO_G

Linear acceleration SPI enable
Linear acceleration I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)

Angular rate SPI enable
Angular rate I

I2C serial clock (SCL)
SPI serial port clock (SPC)

2

I

C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)

2

I

C least significant bit of the device address (SA0)
SPI serial data output (SDO)

6.1 I2C serial interface

The LSM330 I2C is a bus slave. The I2C is employed to write the data to the registers,
whose content can also be read back.

The relevant I

Table 11. Serial interface pin description

2

C terminology is provided in the table below.

Term Description

2

C/SPI mode selection (1: I2C mode; 0: SPI enabled)

Transmitter The device which sends data to the bus

Receiver The device which receives data from the bus

Master

Slave The device addressed by the master

The device which initiates a transfer, generates clock signals and terminates a
transfer

There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the
Serial Data line (SDA). The latter is a bidirectional line used for sending and receiving the
data to/from the interface.

32/76 Doc ID 023426 Rev 1

LSM330 Digital interfaces

6.1.1 I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits, and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.

2

The I

C embedded in the LSM330 behaves like a slave device and the following protocol
must be adhered to. After the start condition (ST), a slave address is sent. Once a slave
acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the 7
LSb represent the actual register address while the MSb enables address auto increment. If
the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased to
allow multiple data read/write.

Table 12. Transfer when master is writing one byte to slave

Master ST SAD + W SUB DATA SP

Slave SAK SAK SAK

Table 13. Transfer when master is writing multiple bytes to slave

Master ST SAD + W SUB DATA DATA SP

Slave SAK SAK SAK SAK

Table 14. Transfer when master is receiving (reading) one byte of data from slave

Master ST SAD + W SUB SR SAD + R NMAK SP

Slave SAK SAK SAK DATA

Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave

Master ST SAD+W SUB SR SAD+R MAK MAK NMAK SP

Slave SAK SAK SAK DATA DATA DATA

Data is transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of
bytes sent per transfer is unlimited. Data is transferred with the most significant bit (MSb)
first. If a receiver cannot receive another complete byte of data until it has performed some
other function, it can hold the clock line, SCL, LOW to force the transmitter into a wait state.

Doc ID 023426 Rev 1 33/76

Digital interfaces LSM330

Data transfer only continues when the receiver is ready for another byte and releases the
data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.

In order to read multiple bytes, it is necessary to assert the most significant bit of the sub­address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.

In the communication format presented, MAK is Master Acknowledge and NMAK is No
Master Acknowledge.

Default address:

The SDO/SA0 pins (SDO_A / SDO_G) can be used to modify the least significant bits of the
device address.The linear acceleration sensor slave address is 00111xxb whereas the xx
bits are modified by the SDO_A pin: If SDO/A pin is connected to voltage supply, the
address is 0011101b otherwise if SDO/A pin is connected to ground, the address is
0011110b.This solution allows to connect and address two different accelerometers to the
same I2C line.

The angular rate sensor slave address is 110101xb, whereas the x bit is modified by the
SDO/G bit: If the SDO_G pin is connected to voltage supply, LSb is ‘1’ (address 1101011b),
otherwise, if the SDO_G pin is connected to ground, the LSb value is ‘0’ (address
1101010b).

The slave addresses is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’
(Write) the master will transmit to the slave with direction unchanged. Ta b le and Ta b le 1 7
explain how the SAD+Read/Write bit pattern arecomposed, listing all the possible
configurations.

Linear acceleration sensor: the default (factory) 7-bit slave address is
00111xxb.

Table 16. Linear acceleration SAD+Read/Write patterns

Command SAD[6:2] SAD[1] = SDO_A SAD[0] = SDO_A R/W SAD+R/W

Read 00111 1 0 1

Write 00111 1 0 0

Read 00111 0 1 1

Write 00111 0 1 0

00111101

(3Dh)

00111100

(3Ch)

00111011

(3Bh)

00111010

(3Ah)

34/76 Doc ID 023426 Rev 1

LSM330 Digital interfaces

CS

SPC

SDI

SDO

RW

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

MS

AM10129V1

Angular rate sensor: the default (factory) 7-bit slave address is 110101xb.

Table 17. Angular rate SAD+Read/Write patterns

Command SAD[6:1] SAD[0] = SDO_G R/W SAD+R/W

Read 110101 0 1 11010101 (D5h)

Write 110101 0 0 11010100 (D4h)

Read 110101 1 1 11010111 (D7h)

Write 110101 1 0 11010110 (D6h)

6.2 SPI bus interface

The LSM330 SPI is a bus slave. The SPI allows writing and reading the registers of the
device.

The serial interface interacts with the external world through 4 wires: CS(CS_A,CS_G),

SPC, SDI and SDO (SDO_A,SDO_G); (SPC, SDI are common).

Figure 14. Read and write protocol

CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the

transmission and returns high at the end. SPC is the serial port clock and is controlled by
the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are
respectively the serial port data input and output. These lines are driven at the falling edge
of SPC and should be captured at the rising edge of SPC.

Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in case of multiple-byte read/write. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS, while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.

bit 0: RW

bit. When 0, the data DI(7:0) is written to the device. When 1, the data DO(7:0)

from the device is read. In the latter case, the chip drives SDO at the start of bit 8.

bit 1: MS

bit. When 0, the address remains unchanged in multiple read/write commands.

When 1, the address is auto-incremented in multiple read/write commands.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

Doc ID 023426 Rev 1 35/76

Digital interfaces LSM330

CS

SPC

SDI

SDO

RW

DO7 DO6 DO5 DO4 DO3DO2 DO1 DO0

AD5 AD4 AD3 AD2 AD1 AD0

MS

AM10130V1

bit 8-15: data DI(7:0) (Write mode). This is the data that will be written to the device (MSb
first).

bit 8-15: data DO(7:0) (Read mode). This is the data that will be read from the device (MSb
first).

In multiple read/write commands, further blocks of 8 clock periods will be added. When the
MS

bit is ‘0’, the address used to read/write data remains the same for every block. When

the MS

bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

6.2.1 SPI read

Figure 15. SPI read protocol

Note: Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A /

SDO_G.

The SPI read command is performed with 16 clock pulses. A multiple-byte read command is
performed by adding blocks of 8 clock pulses to the previous one.

bit 0: READ bit. The value is 1.

bit 1: MS

bit. When 0, do not increment address; when 1, increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (Read mode). This is the data that will be read from the device (MSb

first).

bit 16-... : data DO(...-8). Further data in multiple-byte reading.

36/76 Doc ID 023426 Rev 1

LSM330 Digital interfaces

C S

SPC

SDI

SDO

RW

DO7DO6DO5DO4DO3 DO 2 DO1 DO 0

AD5 AD4AD3 AD2 AD1 AD0

DO15 DO 14 DO 13 DO12 DO 11 DO 10 D O9 D O8

M S

AM10131V1

CS

SPC

SDI

RW

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

AD5 AD 4 AD 3 AD2 AD1 AD0MS

AM10132V1

Figure 16. Multiple-byte SPI read protocol (2-byte example)

6.2.2 SPI write

Figure 17. SPI write protocol

Note: Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A /

SDO_G.

The SPI write command is performed with 16 clock pulses. A multiple-byte write command
is performed by adding blocks of 8 clock pulses to the previous one.

bit 0: WRITE bit. The value is 0.

bit 1: MS

bit. When 0, do not increment address; when 1, increment address in multiple

writing.

bit 2 -7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (Write mode). This is the data that will be written to the device (MSb

first).

bit 16-... : data DI(...-8). Further data in multiple-byte writing.

Doc ID 023426 Rev 1 37/76

Digital interfaces LSM330

CS

SPC

SDI

RW

AD5 AD4 AD3 AD2 AD1 AD 0

DI7 DI6 DI 5 D I4 DI 3 DI 2 DI 1 DI 0 DI 15 D I1 4 DI13 DI12 DI 11 DI 10 DI9 DI 8

MS

AM10133V1

CS

SPC

SDI/O

RW

DO7 DO6 DO5 DO4 DO3 DO 2 DO 1 DO 0

AD5 AD4 AD3 AD2 AD1 AD 0MS

AM10134V1

Figure 18. Multiple bytes SPI write protocol (2 bytes example)

6.2.3 SPI read in 3-wire mode

3-wire mode is entered by setting the SIM bits to ‘1’ (SPI serial interface mode selection) in
the CTRL_REG6_A (24h) and CTRL_REG4_G (23h) .

Figure 19. SPI read protocol in 3-wire mode

Note: Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A /

SDO_G.

The SPI read command is performed with 16 clock pulses:

bit 0: READ bit. The value is 1.

bit 1: MS

bit. When 0, do not increment address; when 1, increment address in multiple

reading.

bit 2-7: address AD(5:0). This is the address field of the indexed register.

bit 8-15: data DO(7:0) (Read mode). This is the data that will be read from the device (MSb

first).

Multiple read command is also available in 3-wire mode.

38/76 Doc ID 023426 Rev 1

LSM330 Register mapping

7 Register mapping

The table below provides a listing of the 8/16-bit registers embedded in the device, and their
related addresses:

Table 18. Register address map

Name

WHO_AM_I_A Ta bl e 1 5 r 0F 000 1111 01000000

CTRL_REG4_A Ta b le 1 5 r/w 23 010 0011 00000000

CTRL_REG5_A Ta b le 1 5 r/w 20 010 0000 00000111

CTRL_REG6_A Ta b le 1 5 r/w 24 010 0100 00000000

CTRL_REG7_A Ta b le 1 5 r/w 25 010 0101 00000000

STATUS_REG_A Ta b le 1 5 r 27 010 0111 output

OFF_X Ta bl e 1 5 r/w 10 001 0000 output

OFF_Y Ta bl e 1 5 r/w 11 001 0001 output

OFF_Z Ta b le 1 5 r/w 12 001 0010 output

CS_X Ta bl e 1 5 r/w 13 001 0011 00000001

CS_Y Ta bl e 1 5 r/w 14 001 0100 00000001

CS_Z Ta bl e 1 5 r/w 15 001 0101 00000001

Slave

address

Typ e

Register address

Default Comment

Hex Binary

Who am I

linear

acceleration

sensor

register

Linear

Acceleration

Sensor

Control

Registers

Status

register

Axis offset

correction

Constant Shift

registers

LC_L Ta bl e 1 5 r/w 16 001 0110 00000001

LC_H Ta bl e 1 5 r/w 17 001 0111 00000000

STAT Ta bl e 1 5 r 18 001 1000 output Interrupt Sync

VFC_1 Ta b l e 1 5 r/w 1B 001 1011 00000000

VFC_2 Ta b l e 1 5 r/w 1C 001 1100 00000000

VFC_3 Ta b l e 1 5 r/w 1D 001 1101 00000000

VFC_4 Ta b l e 1 5 r/w 1E 001 1110 00000000

THRS3 Ta b l e 1 5 r/w 1F 001 1111 00000000

Doc ID 023426 Rev 1 39/76

Long Counter

Registers

Vec t o r F ilter

Coefficient

Thresold

value 3

Register mapping LSM330

Table 18. Register address map (continued)

Name

OUT_X_L_A Ta bl e 1 5 r 28 010 1000 output

OUT_X_H_A Ta b le 1 5 r 29 010 1001 output

OUT_Y_L_A Ta bl e 1 5 r 2A 010 1010 output

OUT_Y_H_A Ta b le 1 5 r 2B 010 1011 output

OUT_Z_L_A Tab le 1 5 r 2C 010 1100 output

OUT_Z_H_A Ta b le 1 5 r 2D 010 1101 output

FIFO_CTRL_REG_A Ta b le 1 5 r/w 2E 010 1110 00000000 Linear

FIFO_SRC_REG_A Ta bl e 1 5 r 2F 010 1111 output

CTRL_REG2_A Ta b le 1 5 r/w 21 010 0001 00000000

STx_1 Ta bl e 1 5 r/w 40-4F

TIM4_1 Ta bl e 1 5 r/w 50 101 0000 00000000

TIM3_1 Ta bl e 1 5 r/w 51 101 0001 00000000

TIM2_1 Ta bl e 1 5 r/w 52-53

TIM1_1 Ta bl e 1 5 r/w 54-55

THRS2_1 Ta bl e 1 5 r/w 56 101 0110 00000000

THRS1_1 Ta bl e 1 5 r/w 57 101 0111 00000000

MASKB_1 Ta b le 1 5 r/w 59 101 1001 00000000

MASKA_1 Ta b le 1 5 r/w 5A 101 1010 00000000

Slave

address

Typ e

Register address

Hex Binary

100 0000
100 1111

101 0010
101 0011

101 0100
101 0101

Default Comment

Linear

Acceleration

Sensor

Output

registers

Acceleration

Sensor FIFO

Registers

SM1 Control

Register

SM1 Code

00000000

00000000

00000000

Register
(X=1-16)

SM1 General

Timers

SM1

Thereshold

Val ue 1

SM1

Thereshold

Val ue 2

SM1 axis and

sign mask

SETT1 Ta b le 1 5 r/w 5B 101 1011 00000000

PR1 Ta b le 1 5 r/w 5C 101 1100 00000000

TC1 Ta b le 1 5 r5D-5E

OUTS1 Ta b le 1 5 r 5F 101 1111 00000000 Main set flag

PEAK1 Ta bl e 1 5 r 19 001 1001 00000000 Peak value

40/76 Doc ID 023426 Rev 1

101 1101
101 1110

SM1

Detection

Settings

Program-

Reset Pointer

00000000 Timer Counter

LSM330 Register mapping

Table 18. Register address map (continued)

Name

CTRL_REG3_A Ta b le 1 5 r/w 22 010 0010 00000000

STx_2 Ta bl e 1 5 r/w 60-6F

TIM4_2 Ta bl e 1 5 r/w 70 111 0000 00000000

TIM3_2 Ta bl e 1 5 r/w 71 111 0001 00000000

TIM2_2 Ta bl e 1 5 r/w 72-73

TIM1_2 Ta bl e 1 5 r/w 74-75

THRS2_2 Ta bl e 1 5 r/w 76 111 0110 00000000

THRS1_2 Ta bl e 1 5 r/w 77 111 0111 00000000

MASKB_2 Ta b le 1 5 r/w 79 111 1001 00000000

MASKA_2 Ta b le 1 5 r/w 7A 111 1010 00000000

Slave

address

Typ e

Register address

Hex Binary

110 0000
110 1111

111 00 1 0

111 0011

111 0100
111 0101

Default Comment

00000000

00000000

00000000

SM2 Control

Register

SM2 Code

Register
(X=1-16)

SM2 General

Timers

SM2

Thereshold

Val ue 1

SM2

Thereshold

Val ue 2

SM2 axis and

sign mask

SM2

SETT2 Ta b le 1 5 r/w 7B 111 1011 00000000

PR2 Ta b le 1 5 r/w 7C 111 1100 00000000

TC2 Ta b le 1 5 r7D-7E

OUTS2 Ta b le 1 5 r 7F 111 1111 00000000 Main set flag

PEAK2 Ta bl e 1 5 r 1A 001 1010 00000000 Peak value

DES2 Ta bl e 1 5 w 78 111 1000 00000000

WHO_AM_I_G Tab l e 1 6 r 0F 000 1111 11010100 Who I am ID

Reserved --10-1F - - -

CTRL_REG1_G Ta b le 1 6 r/w 20 010 0000 00000111

CTRL_REG2_G Ta b le 1 6 r/w 21 010 0001 00000000

CTRL_REG3_G Ta b le 1 6

CTRL_REG4_G Ta b le 1 6 r/w 23 010 0011 00000000

CTRL_REG5_G Ta b le 1 6 r/w 24 010 0100 00000000

r/w 22 010 0010 00000000

111 1101
111 1110

00000000 Timer Counter

Detection

Settings

Program-

Reset Pointer

Decimation

Facto r

Angular Rate

Sensor

Control

Registers

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Register mapping LSM330

Table 18. Register address map (continued)

Name

REFERENCE_G Ta bl e 1 6 r/w 25 010 0101 00000000

OUT_TEMP_G Ta bl e 1 6 r 26 010 0110 output

STATUS_REG_G Ta bl e 1 6 r 27 010 0111 output

OUT_X_L_G Ta b l e 1 6 r 28 010 1000 output

OUT_X_H_G Ta bl e 1 6 r 29 010 1001 output

OUT_Y_L_G Ta b l e 1 6 r 2A 010 1010 output

OUT_Y_H_G Ta bl e 1 6 r 2B 010 1011 output

OUT_Z_L_G Ta bl e 1 6 r 2C 010 1100 output

OUT_Z_H_G Ta b le 1 6 r 2D 010 1101 output

FIFO_CTRL_REG_G Ta bl e 1 6 r/w 2E 010 1110 00000000 Angular rate

FIFO_SRC_REG_G Ta b le 1 6 r 2F 010 1111 output

INT1_CFG_G Ta bl e 1 6 r/w 30 011 0000 00000000

Slave

address

Typ e

Register address

Default Comment

Hex Binary

Reference

value for
interrupt

generation

Temperature

data output

Status

register

Angular rate

sensor
Output

Registers

sensor FIFO

Registers

INT1_SRC_G Ta bl e 1 6 r/w 31 011 0001 output

INT1_THS_XH_G Ta b le 1 6 r/w 32 011 0010 00000000

INT1_THS_XL_G Ta bl e 1 6 r/w 33 011 0011 00000000

INT1_THS_YH_G Ta b le 1 6 r/w 34 011 0100 00000000

INT1_THS_YL_G Ta bl e 1 6 r/w 35 011 0101 00000000

INT1_THS_ZH_G Ta bl e 1 6 r/w 36 011 0110 00000000

INT1_THS_ZL_G Ta b le 1 6 r/w 37 011 0111 00000000

INT1_DURATION_G Ta bl e 1 6 r/w 38 011 1000 00000000

Registers marked as Reserved must not be changed. Writing to those registers may cause
permanent damage to the device.

The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.

Angular rate

sensor

Interrupt

Registers

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LSM330 Register descriptions

8 Register descriptions

The device contains a set of registers which are used to control its behavior and to retrieve
linear acceleration, angular rate and temperature data. The register addresses, made up of
7 bits, are used to identify them and to write the data through the serial interface.

8.1 WHO_AM_I_A (0Fh)

Who am I linear acceleration sensor register (r)

Table 19. WHO_AM_I_A register default value

01000000

8.2 CTRL_REG4_A (23h)

Linear acceleration sensor control register 4 (r/w)

Table 20. CTRL_REG4_A register

DR_EN IEA IEL INT2_EN INT1_EN VFILT - STRT

Table 21. CTRL_REG4_A register description

DR_EN

IEA

IEL

INT2_EN

INT1_EN

VFILT

STRT

DRDY signal enable on INT1_A. Default Value:0
0 = Data Ready signal disabled, 1 = Data Ready signal routed to INT1_A

Interrupt signal polarity. Default Value:0
0 = Interrupt signal active LOW, 1 = Interrupt signal active HIGH

Interrupt signal lachting. Default Value:0
0 = Interrupt signal latched, 1 = Interrupt signal pulsed

Interrupt 2 enable on INT2_A. Default Value:0
0 = INT2_A signal disabled, 1 = INT2_A signal enable

Interrupt 1 enable on INT1_A. Default Value:0
0 = INT1_A signal disabled, 1 = INT1_A signal enable

Vector Filter enable. Default Value:0
0 = Vector filter disabled, 1 = Vector filter enabled

Soft Reset bit. Default Value:0.
0= no soft reset, 1= Soft Reset (POR function)

8.3 CTRL_REG5_A (20h)

Linear acceleration sensor control register 5 (r/w)

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Register descriptions LSM330

Table 22. CTRL_REG5_A register

ODR3 ODR2 ODR1 ODR0 BDU ZEN YEN XEN

Table 23. CTRL_REG5_A register description

ODR [3:0]

BDU

Output data rate & Power Mode selection. Default Value:0000 (see Table 24)

Block Data Update. Default Value:0
0:continuos update,1:output registers not updated until MSB and LSB reading

Zen

Ye n

Xen

Z axis enable. Default Value:1

(0:Z axis disabled; 1:Z axis enabled)

Y axis enable. Default Value:1
(0:Y axis disabled; 1:Y axis enabled)

X axis enable. Default Value:1

(0:X axis disabled;1:X axis enabled)

ODR [3:0] is used to set Power mode, ODR selection . In the following Ta b le are reported all
frequencies available.

Table 24. CTRL_REG5_A Output Data Rate selection

ODR3 ODR2 ODR1 ODR0 ODR selection

0000Power Down

00013.125 Hz

00106.25 Hz

001112.5 Hz

010025 Hz

010150 Hz

0110100 Hz

0111400 Hz

1000800 Hz

10011600 Hz

BDU bit is used to inhibit output registers update until both upper and lower registers are
read. In default mode (BDU=’0’) the output register values are updated continuosly. If for any
reason it is not sure to read faster than output data rate it is recommended to set BDU bit to
‘1’. In this way the content of output register is not updated until both MSB and LSB are
read, avoiding to read values related to different sample time.

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LSM330 Register descriptions

8.4 CTRL_REG6_A (24h)

Linear acceleration sensor control register 6 (r/w).

Table 25. CTRL_REG6_A register

BW2 BW1 FSCALE2 FSCALE1 FSCALE0 - - SIM

Table 26. CTRL_REG6_A register description

BW [2:1] Anti aliasing filter bandwidth. Default value: 00

00= 800 Hz; 01= 200 Hz; 10:=400 Hz; 11:=50 Hz)

FSCALE [2:0] Full Scale selection. Default value: 000

000= +/- 2G; 001=+/- 4G; 010= +/- 6G; 011= +/- 8G; 100= +/- 16G

SIM SPI Serial Interface Mode selection. Default value: 0

0= 4-wire interface; 1:=3-wire interface

8.5 CTRL_REG7_A (25h)

Linear acceleration sensor control register 7(r/w).

Table 27. CTRL_REG7_A register

BOOT FIFO_EN WTM_EN

ADD_

INC

P1_

EMPTY

P1_WTM

P1_OVER

RUN

BOOT_

INT

Table 28. CTRL_REG7_A register description

BOOT Force reboot, cleared as soon as the reboot is finished. Active High.

Default value: 0

FIFO_EN FIFO Enable. Default value: 0.

0= Disable; 1= Enable

WTM_EN Enable FIFO Watermark level use. Default value: 0.

0= Disable; 1 = Enable

ADD_INC Register address automatically incremented during a multiple byte access with a

serial interface (I2C or SPI).Default value: 0
0=Disable; 1= Enable

P1_EMPTY Enable FIFO Empty indication on INT1_A. Default value: 0.

0= Disable; 1= Enable

P1_WTM FIFO Watermark interrupt on INT1_A. Default value: 0.

0:=Disable; 1= Enable

P1_OVERRUN FIFO Overrun interrupt on INT1_A. Default value: 0.

0= Disable; 1= Enable

P2_BOOT BOOT interrupt on INT2_A. Default value: 0.

0= Disable; 1= Enable

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Register descriptions LSM330

8.6 STATUS_REG_A (27h)

Linear acceleration sensor status register (r).

Table 29. STATUS_REG_A register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 30. STATUS_REG_A register description

ZYXOR X, Y and Z axis Data Overrun. Default value: 0

0=no overrun has occurred; 1= a new set of data has overwritten the previous one

ZOR Z axis Data Overrun. Default value: 0

0= no overrun has occurred; 1= a new set of data for the Z-axis has overwritten the
previous one

YOR Y axis Data Overrun. Default value: 0

0= no overrun has occurred;
1= a new data for the Y-axis has overwritten the previous one

XOR X axis Data Overrun. Default value: 0

0= no overrun has occurred;
1= a new data for the X-axis has overwritten the previous one

ZYXDA X, Y and Z axis new Data Available. Default value: 0

0= a new set of data is not yet available; 1= a new set of data is available

ZDA Z axis new Data Available. Default value: 0

0= a new data for the Z-axis is not yet available;
1=a new data for the Z-axis is available

YDA Y axis new Data Available. Default value: 0

0 = a new data for the Y-axis is not yet available;
1 = a new data for the Y-axis is available

XDA X axis new Data Available. Default value: 0

0 = a new data for the X-axis is not yet available;
1 = a new data for the X-axis is available

8.7 OFF_X (10h)

Offset correction x-axis register, signed value (r/w).

Table 31. OFF_X default valu

00000000

8.8 OFF_Y (11h)

Offset correction y-axis register, signed value (r/w).

Table 32. OFF_Y default value

00000000

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LSM330 Register descriptions

8.9 OFF_Z (12h)

Offset correction z-axis register, signed value (r/w).

Table 33. OFF_Z default value

00000000

8.10 CS_X (13h)

Constant shift signed value x-axis register (r/w).

Table 34. CS_X default value

00000001

8.11 CS_Y (14h)

Constant shift signed value y-axis register (r/w).

Table 35. CS_Y default value

00000001

8.12 CS_Z (15h)

Constant shift signed value z-axis register (r/w).

Table 36. CS_Z default value

00000001

8.13 LC_L (16h) and LC_H (17h)

16 bit long-counter register for interrupt state machine programs timing (r/w)

Table 37. LC_L default value

00000001

Table 38. LC_H default value

00000000

01h=counting stopped, 00h=counter full:interrupt available and counter is set to default

values higher than 00h:counting

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Register descriptions LSM330

8.14 STAT (18h)

Interrupt Synchronization register (r).

Table 39. STAT register

LONG SYNCW SYNC1 SYNC2 INT_SM1 INT_SM2 DOR DRDY

Table 40. STAT register description

LONG

LC interrupt flag.
0 = no interrupt, 1 = Long Counter (LC) interrupt flag common for both SM

SYNCW

SYNC1

SYNC2

INT_SM1

NT_SM2

DOR

DRDY

Synchronization for external Host Controller Interrupt based on output data
0= no action waiting from host; 1= action from host based on output data

0 = SM1 running normally, 1 = SM1 stopped and wait restart request from SM2

0 = SM2 running normally, 1 = SM2 stopped and wait restart request from SM1

SM1- Interrupt Selection.

1= SM1 interrupt generated;0 = SM1 interrupt not generated

SM2- Interrupt Selection.

1= SM2 interrupt generated;0=SM2 interrupt not generated

Data overrun indicates not read data from output register when next data

samples measure start ;0 = no overrun, 1 = data overrun

data overrun bit is reset when next sample is ready

data ready from output register.

0 = data not ready, 1 = data ready

8.15 VFC_1 (1Bh)

Vector coefficient register 1 for DIff filter (r/w).

Table 41. VFC_1 default value

00000000

8.16 VFC_2 (1Ch)

Vector coefficient register 2 for DIff filter (r/w).

Table 42. VFC_2 default value

00000000

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LSM330 Register descriptions

8.17 VFC_3 (1Dh)

Vector coefficient register 3 for DIff filter (r/w).

Table 43. VFC_3 default value

00000000

8.18 VFC_4 (1Eh)

Vector coefficient register 4 for DIff filter (r/w).

Table 44. VFC_4 default value

00000000

8.19 THRS3 (1Fh)

Threshold value register (r/w).

Table 45. THRS3 default value

00000000

8.20 OUT_X_L_A (28h) and OUT_X_H_A (29h)

X-axis linear acceleration output data register (r). The value is expressed as two’s
complement.

8.21 OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh)

Y-axis linear acceleration output data register (r). The value is expressed as two’s
complement.

8.22 OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh)

X-axis linear acceleration output data register (r). The value is expressed as two’s
complement.

8.23 FIFO_CTRL_REG_A (2Eh)

linear acceleration sensor FIFO control register (r/w).

Table 46. FIFO_CTRL_REG_A register

FMODE2 FMODE1 FMODE0 WTMP4 WTMP3 WTMP2 WTMP1 WTMP0

Doc ID 023426 Rev 1 49/76

Register descriptions LSM330

Table 47. FIFO_CTRL_REG_A register description

FMODE [2:0] FIFO mode selection. Default value: 000 (see Tab le 4 8 )

WTMP [4:0] FIFO threshold. Watermark level setting. FIFO depth if the watermark is enable

Table 48. FIFO mode configuration

FMODE2 FMODE1 FMODE0 FIFO Mode

0 0 0 Bypass mode

001FIFO mode

010Stream mode

0 1 1 Stream-to-FIFO mode

1 0 0 Bypass-to-Stream mode

Other configurations are not used.

8.24 FIFO_SRC_REG_A (2Fh)

Linear acceleration sensor FIFO source control register (r).

Table 49. FIFO_SRC_REG_A register

WTM

OVRN_

FIFO

EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

Table 50. IFO_SRC_REG_A register description

WTM Watermark status.

0=FIFO filling is lower than WTM level; 1= FIFO filling is equal or higher than
WTM level

OVRN_FIFO Overrun bit status. 0=FIFO is not completely filled; 1=FIFO is completely filled

EMPTY FIFO empty bit.

0= FIFO not empty; 1:=FIFO empty)

FSS [4:0] FIFO stored data level

8.25 CTRL_REG2_A (21h)

State machine 1 control register (r/w).

Table 51. CTRL_REG2_A register

HYST2_1 HYST1_1 HYST0_1 - SM1_PIN - - SM1_EN

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LSM330 Register descriptions

Table 52. CTRL_REG2_A register description

HYST2_1
HYST1_1
HYST0_1

Hysteresis unsigned value to be added or subtracted from threshold value in SM1
Default Value :000

SM1_PIN

SM1_EN

0 = SM1 interrupt routed to INT1_A pin, 1 = SM1 interrupt routed to INT2_A pin
Default Value :0

0 = SM1 disabled, 1 = SM1 enabled
Default Value :0

8.26 STx_1 (40h-4Fh)

State machine 1 code register (r/w).

State machine 1 system register is composed by 16, 8 bit registers, to implement 16 steps
op-code (STx_1 (x = 1-16)).

Table 53. STx_1 registers default value

00000000

------------------------------------------------------------------------------------------------------------------------------------

00000000

8.27 TIM4_1 (50h)

8 bit general timer (unsigned value) for state machine 1 operation timing register (r/w).

Table 54. TIM4_1b

Table 55. TIM4_1 default valu

00000000

8.28 TIM3_1 (51h)

8 bit general timer (unsigned value) for state machine 1 operation timing register (r/w).

Table 56. TIM3_1 default value

00000000

8.29 TIM2_1 (52h - 53h)

16 bit general timer (unsigned value) for state machine 1 operation timing register (r/w).

Doc ID 023426 Rev 1 51/76

Register descriptions LSM330

Table 57. TIM2_1_L default value

00000000

Table 58. TIM2_1_H default value

00000000

8.30 TIM1_1 (54h - 55h)

16 bit general timer (unsigned value) for state machine 1 operation timing register (r/w).

Table 59. TIM1_1_L default value

00000000

Table 60. TIM1_1_H default value

00000000

8.31 THRS2_1 (56h)

Threshold signed value for state machine 1 operation register (r/w).

Table 61. THRS2_1 default value

00000000

8.32 THRS1_1(57h)

Threshold signed value for state machine 1 operation register (r/w).

Table 62. THRS1_1 default value

00000000

8.33 MASKB_1 (59h)

Axis and sign mask (swap) for state machine 1 motion detection operation register (r/w).

Table 63. MASKB_1 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

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LSM330 Register descriptions

Table 64. MASKB_1 register description

P_X

N_X 0 = X - disabled, 1 = X – enabled. Default Value :0

0 = X + disabled, 1 =X+ enabled.Default Value :0

P_Y

N_Y 0 = Y- disabled, 1 = Y– enabled. Default Value :0

P_Z

N_Z 0 = Z - disabled, 1 = Z – enabled. Default Value :0

P_V

N_V 0 = V - disabled, 1 = V – enabled. Default Value :0

0 = Y+ disabled, 1 = Y+ enabled. Default Value :0

0 = Z+ disabled, 1 = Z + enabled. Default Value :0

0 = V + disabled, 1 = V + enabled. Default Value :0

8.34 MASKA_1(5Ah)

Axis and sign mask (default) for state machine 1 motion detection operation register (r/w).

Table 65. MASKA_1 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 66. MASKA_1 register description

P_X

N_X 0 = X - disabled, 1 = X – enabled. Default Value :0

P_Y

N_Y 0 = Y- disabled, 1 = Y– enabled. Default Value :0

0 = X + disabled, 1 =X+ enabled. Default Value :0

0 = Y+ disabled, 1 = Y+ enabled. Default Value :0

P_Z

N_Z 0 = Z - disabled, 1 = Z – enabled. Default Value :0

P_V

N_V 0 = V - disabled, 1 = V – enabled. Default Value :0

0 = Z+ disabled, 1 = Z + enabled. Default Value :0

0 = V + disabled, 1 = V + enabled. Default Value :0

8.35 SETT1 (5Bh)

Setting of threshold, peak detection and flags for state machine 1 motion detection
operation register (r/w)

Table 67. SETT1 register

P_DET THR3_SA ABS - - THR3_MA R_TAM SITR

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Register descriptions LSM330

Table 68. SETT1 register description

P_DET

THR3_SA

ABS

THR3_MA

R_TAM

SITR

SM1 Peak detection.Default Value:0
0 = peak detection disabled, 1 = peak detection enabled

Default Value:0
0 = no action, 1 = Threshold 3 limit value for axis and sign mask reset (MASKB_1)

Default Value:0
0 = unsigned thresholds, 1 = signed thresholds

Default Value:0
0 = no action, 1 = Threshold 3 limit value for axis and sign mask reset (MASKA_1)

next condition validation flag.Default Value:0
0 = no valid next condition found , 1= valid next condition found and reset

Default Value:0
0 = no actions, 1 = program flow can be modified by STOP and CONT commands

8.36 PR1 (5Ch)

Program and reset pointer for state machine 1 motion detection operation register (r/w)

Table 69. PR1 register

PP3 PP2 PP1 PP0 RP3 RP2 RP1 RP0

Table 70. PR1 register description

PP [3:0] SM1 Program Pointer Address.Default Value:0000

RP [3:0] SM1 Reset Pointer Address.Default Value:0000

8.37 TC1 (5Dh-5E)

16 bit general timer (unsigned output value) for state machine 1 operation timing register (r).

Table 71. TC1_L default value

00000000

Table 72. TC1_H default value

00000000

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LSM330 Register descriptions

8.38 OUTS1 (5Fh)

Output flags on axis for interrupt state machine 1 management register (r).

Table 73. OUTS1 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 74. OUTS1 register description

P_X

N_X 0 = X - not shown, 1 = X – show.Default Value :0

0 = X + not shown, 1 =X+ show.Default Value :0

P_Y

N_Y 0 = Y - not shown, 1 = Y – show.Default Value :0

P_Z

N_Z 0 = Z - not shown, 1 = Z – show.Default Value :0

P_V

N_V 0 = V - not shown, 1 = V – show.Default Value :0

0 = Y + not shown, 1 =Y+ show.Default Value :0

0 = Z + not shown, 1 =Z+ show.Default Value :0

0 = V + not shown, 1 = V + show.Default Value :0

8.39 PEAK1 (19h)

Peak detection value register for state machine 1 operation register (r).

Table 75. PEAK1 default value

00000000

Peak detected value for next condition SM1

8.40 CTRL_REG3_A (22h)

State machine 2 control register (r/w).

Table 76. CTRL_REG3_A register

HYST2_2 HYST1_2 HYST0_2 - SM2_PIN - - SM2_EN

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Register descriptions LSM330

Table 77. CTRL_REG3_A register description

HYST2_2
HYST1_2
HYST0_2

Hysteresis unsigned value to be added or subtracted from threshold value in SM2
Default Value= 000

SM2_PIN

SM2_EN

0 = SM2 interrupt routed to INT1_A, 1 = SM2 interrupt routed to INT1_A pin
Default Value=0

0 = SM2 disabled, 1 = SM2 enabled
Default Value=0

8.41 STx_2 (60h-6Fh)

State machine 2 code register (r/w).

State machine 2 system register is composed by 16, 8 bit register, to implement 16 steps
op-code (STx_2 (x = 1-16)).

Table 78. STx_2 registers default value

00000000

------------------------------------------------------------------------------------------------------------------------------------

00000000

8.42 TIM4_2 (70h)

8 bit general timer (unsigned value) for state machine 2 operation timing register (r/w).

Table 79. TIM4_2 default value

00000000

8.43 TIM3_2 (71h)

8 bit general timer (unsigned value) for state machine 2 operation timing (r/w).

Table 80. TIM3_2 default value

00000000

8.44 TIM2_2 (72h - 73h)

16 bit general timer (unsigned value) for state machine 2 operation timing register (r/w).

Table 81. TIM2_2_L default value

00000000

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LSM330 Register descriptions

Table 82. TIM2_2_H default value

00000000

8.45 TIM1_2 (74h - 75h)

16 bit general timer (unsigned value) for state machine 2 operation timing register (r/w).

Table 83. TIM1_2_L default value

00000000

Table 84. TIM1_2_H default value

00000000

8.46 THRS2_2 (76h)

Threshold signed value for state machine 2 operation register (r/w).

Table 85. THRS2_2 default value

00000000

8.47 THRS1_2 (77h)

Threshold signed value for state machine 2 operation register (r/w).

Table 86. THRS1_2 default value

00000000

8.48 MASKB_2 (79h)

Axis and sign mask (swap) for state machine 2 motion detection operation register (r/w).

Table 87. MASKB_2 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

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Register descriptions LSM330

Table 88. MASKB_2 register description

P_X 0 = X + disabled, 1 =X+ enabled. Default Value :0

N_X 0 = X - disabled, 1 = X – enabled. Default Value :0

P_Y 0 = Y+ disabled, 1 = Y+ enabled. Default Value :0

N_Y 0 = Y- disabled, 1 = Y– enabled. Default Value :0

P_Z 0 = Z+ disabled, 1 = Z + enabled. Default Value :0

N_Z 0 = Z - disabled, 1 = Z – enabled. Default Value :0

P_V 0 = V + disabled, 1 = V + enabled. Default Value :0

N_V 0 = V - disabled, 1 = V – enabled. Default Value :0

8.49 MASKA_2 (7Ah)

Axis and sign mask (default) for state machine 2 motion detection operation register (r/w).

Table 89. MASKA_2 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Table 90. MASKA_2 register description

P_X 0 = X + disabled, 1 =X+ enabled. Default Value :0

N_X 0 = X - disabled, 1 = X – enabled. Default Value :0

P_Y 0 = Y+ disabled, 1 = Y+ enabled. Default Value :0

N_Y 0 = Y- disabled, 1 = Y– enabled. Default Value :0

P_Z 0 = Z+ disabled, 1 = Z + enabled. Default Value :0

N_Z 0 = Z - disabled, 1 = Z – enabled. Default Value :0

P_V 0 = V + disabled, 1 = V + enabled. Default Value :0

N_V 0 = V - disabled, 1 = V – enabled. Default Value :0

8.50 SETT2 (7Bh)

Setting of threshold, peak detection and flags for state machine 2 motion detection
operation register (r/w).

Table 91. SETT2 register

P_DET THR3_SA ABS - - THR3_MA R_TAM SITR

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LSM330 Register descriptions

Table 92. SETT2 register description

P_DET

THR3_SA

ABS

THR3_MA

R_TAM

SITR

8.51 PR2 (7Ch)

Program and reset pointer for state machine 2 motion detection operation register (r/w).

Table 93. PR2 register

PP3 PP2 PP1 PP0 RP3 RP2 RP1 RP0

SM2 Peak detection.Default Value:0

0 = peak detection disabled, 1 = peak detection enabled

Default Value:0
0 = no action, 1 = Threshold 3 limit value for axis and sign mask reset (MASKB_2)

Default Value:0

0 = unsigned thresholds, 1 = signed thresholds

Default Value:0
0 = no action, 1 = Threshold 3 limit value for axis and sign mask reset (MASKA_2)

next condition validation flag.Default Value:0

0 = no valid next condition found , 1= valid nextc ondition found and reset

Default Value:0
0 = no actions, 1 = program flow can be modified by STOP and CONT commands

Table 94. PR2 register description

PP [3:0] SM2 Program Pointer Address.Default Value :0

RP [3:0] SM2 Reset Pointer Address.Default Value :0

8.52 TC2 (7Dh-7E)

16 bit general timer (unsigned output value) for state machine 2 operation timing register (r).

Table 95. TC2_L default value

00000000

Table 96. TC2_H default value

00000000

8.53 OUTS2 (7Fh)

Output flags on axis for interrupt SM2 management register (r).

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Register descriptions LSM330

Table 97. OUTS2 register

P_X N_X P_Y N_Y P_Z N_Z P_V N_V

Read action of this register, depending on the flag will affect SM2 interrupt functions.

Table 98. OUTS2 register description

P_X 0 = X + noshow, 1 =X+ show. Default Value :0

N_X 0 = X - noshow, 1 = X – show. Default Value :0

P_Y 0 = Y + noshow, 1 =Y+ show. Default Value :0

N_Y 0 = Y - noshow, 1 = Y – show. Default Value :0

P_Z 0 = Z + noshow, 1 =Z+ show. Default Value :0

N_Z 0 = Z - noshow, 1 = Z – show. Default Value :0

P_V 0 = V + noshow, 1 = V + show. Default Value :0

N_V 0 = V - noshow, 1 = V – show. Default Value :0

8.54 PEAK2 (1Ah)

Peak detection value register for state machine 2 operation register (r).

Table 99. PEAK2 default value

00000000

Peak detected value for next condition SM2.

8.55 DES2 (78h)

Decimation counter value register for SM2 operation (w).

Table 100. DES2 default value

00000000

8.56 WHO_AM_I_G (0Fh)

Who am I angular rate sensor register (r)

Table 101. WHO_AM_I_G register

11010100

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LSM330 Register descriptions

8.57 CTRL_REG1_G (20h)

Angular rate sensor control register 1 (r/w).

Table 102. CTRL_REG1_G register

DR1 DR0 BW1 BW0 PD Zen Xen Yen

Table 103. CTRL_REG1_G description

DR [1:0] Output data rate selection.Default value:00. Refer toTable 104

BW [1:0] Bandwidth selection.Default value:00. Refer to Table 104

PD

Zen Z axis enable. Default value: 1

Yen Y axis enable. Default value: 1

Xen X axis enable. Default value: 1

Power-down mode enable. Default value: 0
(0: Power-down mode, 1: Normal mode or Sleep mode)

(0: Z axis disabled; 1: Z axis enabled)

(0: Y axis disabled; 1: Y axis enabled)

(0: X axis disabled; 1: X axis enabled)

DR [1:0] is used to set ODR selection. BW [1:0] is used to set bandwidth selection.

The table below provides all the frequencies resulting from the DR / BW bit combinations.

Table 104. DR and BW configuration setting

DR [1:0] BW [1:0] ODR [Hz] Cut-off [Hz]

00 00 95 12.5

00 01 95 25

00 10 95 25

00 11 95 25

01 00 190 12.5

01 01 190 25

01 10 190 50

01 11 190 70

10 00 380 20

10 01 380 25

10 10 380 50

10 11 380 100

11 00 760 30

11 01 760 35

(1)

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Register descriptions LSM330

Table 104. DR and BW configuration setting (continued)

DR [1:0] BW [1:0] ODR [Hz] Cut-off [Hz]

11 10 760 50

11 11 760 100

1. Values in the table are indicative and they can vary proportionally with the specific ODR value

(1)

The combination of PD, Zen, Yen, Xen is used to set the angular rate sensor in different
modes (Power-down / Normal / Sleep mode) according to the following table:

Table 105. Power mode selection configuration

Mode PD Zen Yen Xen

Power-down 0 - - -

Sleep1000

Normal1---

8.58 CTRL_REG2_G (21h)

Angular rate sensor control register 2 (r/w).

Table 106. CTRL_REG2_G register

EXTRen LVLen HPM1 HPM0 HPCF3 HPCF2 HPCF1 HPCF0

Table 107. CTRL_REG2_G description

EXTRen

LV Le n

HPM [1:0]

HPCF [3:0]

Edge-sensitive trigger Enable: Default value: 0
(0: external trigger disabled; 1: External trigger enabled)

Level-sensitive trigger Enable: Default value: 0
(0: level sensitive trigger disabled; 1: level sensitive trigger enabled)

High-pass filter mode selection. Default value: 00
Refer to Tab le 1 0 8

High-pass filter cut-off frequency selection. Default value: 0000
Refer to Tab le 1 0 9

Table 108. High-pass filter mode configuration

HPM1 HPM0 High-pass filter mode

0 0 Normal mode (reset reading REFERENCE_G (25h) register)

0 1 Reference signal for filtering

1 0 Normal mode

1 1 Autoreset on interrupt event

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LSM330 Register descriptions

Table 109. High-pass filter cut-off frequency configuration [Hz]

HPCF[3:0] ODR=95 Hz ODR=190 Hz ODR=380 Hz ODR=760 Hz

0000 7.2 13.5 27 51.4

0001 3.5 7.2 13.5 27

0010 1.8 3.5 7.2 13.5

0011 0.9 1.8 3.5 7.2

0100 0.45 0.9 1.8 3.5

0101 0.18 0.45 0.9 1.8

0110 0.09 0.18 0.45 0.9

0111 0.045 0.09 0.18 0.45

1000 0.018 0.045 0.09 0.18

1001 0.009 0.018 0.045 0.09

1. Values in the table are indicative and they can vary proportionally with the specific ODR value

8.59 CTRL_REG3_G (22h)

Angular rate sensor control register 3 (r/w).

Table 110. CTRL_REG3_G register

I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty

(1)

Table 111. CTRL_REG3_G description

I1_Int1 Interrupt enable on INT1_G pin. Default value 0. (0: Disable; 1: Enable)

I1_Boot Boot status available on INT1_G. Default value 0. (0: Disable; 1: Enable)

H_Lactive Interrupt active configuration on INT1_G. Default value 0. (0: High; 1: Low)

PP_OD Push-pull / Open drain. Default value: 0. (0: Push-pull; 1: Open drain)

I2_DRDY Date ready on DRDY_G/INT2_G. Default value 0. (0: Disable; 1: Enable)

I2_WTM FIFO watermark interrupt on DRDY_G/INT2_G. Default value: 0.

(0: Disable; 1: Enable)

I2_ORun FIFO overrun interrupt on DRDY_G/INT2_G Default value: 0. (0: Disable; 1: Enable)

I2_Empty FIFO empty interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable)

8.60 CTRL_REG4_G (23h)

Angular rate sensor control register 4 (r/w).

Table 112. CTRL_REG4_G register

BDU BLE FS1 FS0 0 0 0 SIM

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Register descriptions LSM330

Table 113. CTRL_REG4_G description

BDU Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSb and LSb
reading)

BLE Big/little endian data selection. Default value 0.

(0: Data LSb @ lower address; 1: Data MSb @ lower address)

FS [1:0] Full scale selection. Default value: 00

(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

SIM 3-wire SPI Serial interface read mode enable. Default value: 0

(0: 3-wire Read mode disabled; 1: 3-wire read enabled).

8.61 CTRL_REG5_G (24h)

Angular rate sensor control register 5 (r/w).

Table 114. CTRL_REG5_G register

BOOT FIFO_EN -- HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0

Table 115. CTRL_REG5_G description

BOOT Reboot memory content. Default value: 0

(0: Normal mode; 1: reboot memory content)

FIFO_EN FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

HPen High-pass filter Enable. Default value: 0

(0: HPF disabled; 1: HPF enabled, see Figure 20)

INT1_Sel [1:0] INT1 selection configuration. Default value: 0

(see Figure 20)

Out_Sel [1:0] Out selection configuration. Default value: 0

(see Figure 20)

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LSM330 Register descriptions

ADC

LPF1

HPF

0

1

HPen

LPF2

10
11

01

00

Out_Sel <1:0>

DataReg

FIFO

32x16x3

00

11

10

01

Interrupt

generator

INT1_Sel <1:0>

AM07949V2

Figure 20. INT1_Sel and Out_Sel configuration block diagram

8.62 REFERENCE_G (25h)

Interrupt reference value register (r/w).

Table 116. REFERENCE_G register

Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0

Table 117. REFERENCE_G register description

Ref [7:0] Reference value for interrupt generation. Default value: 0

8.63 OUT_TEMP_G (26h)

Temperature data output register (r).

Table 118. OUT_TEMP_G register

Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0

Table 119. OUT_TEMP_G register description

Temp [7:0] Temperature data (1LSb/deg - 8-bit resolution).The value is expressed as

two’s complement.

8.64 STATUS_REG_G (27h)

Angular rate sensor register (r).

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Register descriptions LSM330

Table 120. STATUS_REG_G register

ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA

Table 121. STATUS_REG_G register description

X, Y, Z-axis data overrun. Default value: 0

ZYXOR

(0: no overrun has occurred; 1: new data has overwritten the previous data before it was
read)

ZOR

YOR

XOR

ZYXDA X, Y, Z -axis new data available. Default value: 0

ZDA Z axis new data available. Default value: 0

YDA Y axis new data available. Default value: 0

XDA X axis new data available. Default value: 0

Z axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)

Y axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data)

X axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data)

(0: a new set of data is not yet available; 1: a new set of data is available)

(0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available)

(0: new data for the Y-axis is not yet available;1: new data for the Y-axis is available)

(0: new data for the X-axis is not yet available; 1: new data for the X-axis is available)

8.65 OUT_X_L_G (28h), OUT_X_H_G (29h)

X-axis angular rate output data register (r). The value is expressed as two’s complement.

8.66 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh)

Y-axis angular rate output data register (r). The value is expressed as two’s complement.

8.67 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh)

Z-axis angular rate output data register (r). The value is expressed as two’s complement.

8.68 FIFO_CTRL_REG_G (2Eh)

Angular rate sensor FIFO control register (r/w).

Table 122. FIFO_CTRL_REG_G register

FM2 FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0

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LSM330 Register descriptions

Table 123. FIFO_CTRL_REG_G register description

FM [2:0] FIFO mode selection. Default value: 000 (see Tab l e 1 24 )

WTM [4:0] FIFO threshold. Watermark level setting

Table 124. FIFO mode configuration

FM2 FM1 FM0 FIFO mode

000Bypass mode

001FIFO mode

010Stream mode

011Stream-to-FIFO mode

100Bypass-to-stream mode

8.69 FIFO_SRC_REG_G (2Fh)

Angular rate sensor FIFO source control register (r).

Table 125. FIFO_SRC_REG_G register

WTM OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0

Table 126. FIFO_SRC_REG_G register description

WTM Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal

or higher than WTM level)

OVRN Overrun bit status.

(0: FIFO is not completely filled; 1:FIFO is completely filled)

EMPTY FIFO empty bit.

(0: FIFO not empty; 1: FIFO empty)

FSS [4:0] FIFO stored data level

8.70 INT1_CFG_G (30h)

Angular rate sensor FIFO source control register (r/w).

Table 127. INT1_CFG_G register

AND/OR LIR ZHIE ZLIE YHIE YLIE XHIE XLIE

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Register descriptions LSM330

Table 128. INT1_CFG_G description

AND/OR

AND/OR combination of interrupt events. Default value: 0
(0: OR combination of interrupt events 1: AND combination of interrupt events

LIR

ZHIE

ZLIE

YHIE

YLIE

XHIE

XLIE

Latch Interrupt request. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
Cleared by reading INT1_SRC_G reg.

Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value higher

than preset threshold)

Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value lower than

preset threshold)

Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value higher

than preset threshold)

Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value lower than

preset threshold)

Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value higher

than preset threshold)

Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request; 1: enable interrupt request on measured value lower than

preset threshold)

8.71 INT1_SRC_G (31h)

Angular rate sensor interrupt source register (r).

Table 129. INT1_SRC_G register

0 IA ZHZLYHYLXHXL

Table 130. INT1_SRC_G register description

IA

ZH Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred)

ZL Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred)

YH Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred)

YL Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred)

XH X high. Default value: 0 (0: no interrupt, 1: X High event has occurred)

XL X low. Default value: 0 (0: no interrupt, 1: X Low event has occurred)

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Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)

LSM330 Register descriptions

Reading at this address clears the INT1_SRC_G (31h) IA bit (and eventually the interrupt
signal on the INT1_G pin) and allows the refreshing of data in the INT1_SRC_G register if
the latched option was chosen.

8.72 INT1_THS_XH_G (32h)

Angular rate sensor interrupt threshold x-axis high register (r/w).

Table 131. INT1_THS_XH_G register

- THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8

Table 132. INT1_THS_XH_G description

THSX [14:8] Interrupt threshold. Default value: 000 0000

8.73 INT1_THS_XL_G (33h)

Angular rate sensor interrupt threshold x-axis low register (r/w).

Table 133. INT1_THS_XL_G register

THSX7 THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0

Table 134. INT1_THS_XL_G description

THSX [7:0] Interrupt threshold. Default value: 0000 0000

8.74 INT1_THS_YH _G (34h)

Angular rate sensor interrupt threshold y-axis high register (r/w).

Table 135. INT1_THS_YH_G register

- THSY14 THSY13 THSY12 THSY11 THSY10 THSY9 THSY8

Table 136. INT1_THS_YH_G description

THSY [14:8] Interrupt threshold. Default value: 000 0000

8.75 INT1_THS_YL_G (35h)

Angular rate sensor interrupt threshold y-axis low register (r/w).

Doc ID 023426 Rev 1 69/76

Register descriptions LSM330

Table 137. INT1_THS_YL_G register

THSY7 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0

Table 138. INT1_THS_YL_G description

THSY [7:0] Interrupt threshold. Default value: 0000 0000

8.76 INT1_THS_ZH_G (36h)

Angular rate sensor interrupt threshold z-axis high register (r/w).

Table 139. INT1_THS_ZH_G register

- THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8

Table 140. INT1_THS_ZH_G description

THSZ [14:8] Interrupt threshold. Default value: 000 0000

8.77 INT1_THS_ZL_G (37h)

Angular rate sensor interrupt threshold z-axis low register (r/w).

Table 141. INT1_THS_ZL_G register

THSZ7 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0

Table 142. INT1_THS_ZL_G description

THSZ [7:0] Interrupt threshold. Default value: 0000 0000

8.78 INT1_DURATION_G (38h)

Angular rate sensor interrupt duration register (r/w).

Table 143. INT1_DURATION_G register

WAIT D6 D5 D4 D3 D2 D1 D0

Table 144. INT1_DURATION_G description

WAIT WAIT enable. Default value: 0 (0: disable; 1: enable)

D [6:0] Duration value. Default value: 000 0000

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LSM330 Register descriptions

D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps

and maximum values depend on the ODR chosen.

WAIT bit has the following meaning:

Wait =’0’: the interrupt falls immediately if signal crosses the selected threshold

Wait =’1’: if the signal crosses the selected threshold, the interrupt falls only after the
duration has counted the number of samples at the selected data rate, written into the
duration counter register.

Figure 21. Wait disabled

Doc ID 023426 Rev 1 71/76

Register descriptions LSM330

Figure 22. Wait enabled

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LSM330 Package information

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

®

packages, depending on their level of environmental compliance. ECOPACK

®

Doc ID 023426 Rev 1 73/76

Package information LSM330

8379971_A

Table 145. LGA (3.5x3x1 mm) 24 lead mechanical data

mm

Dim.

Min. Typ. Max.

A1 1.000 1.027

A2 0.800

A3 0.200

D1 2.850 3.000 3.150

E1 3.350 3.500 3.650

L1 3.010

L2 1.290

N1 0.430

M 0.040 0.100

M1 0.070 0.130

P2 0.200 0.250 0.300

a 45°

T1 0.300 0.350 0.400

T2 0.180 0.230 0.280

K0.050

L1 1.27 1.40

L2 1.30 1.75

R0.4

V2 0° 8°

Figure 23. LGA (3.5x3x1 mm) lead drawing

74/76 Doc ID 023426 Rev 1

LSM330 Revision history

10 Revision history

Table 146. Document revision history

Date Revision Changes

10-Jul-2012 1 Initial release.

Doc ID 023426 Rev 1 75/76

LSM330

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