ST LSM330 User Manual

LSM330

iNEMO inertial module: 3D accelerometer and 3D gyroscope

Features

■Analog supply voltage: 2.4 V to 3.6 V

■Digital supply voltage IOs: 1.8 V

■Power-down and sleep modes

■2 Embedded programmable state machines

■3 independent acceleration channels and 3 angular rate channels

■±2 g/±4 g/±6 g/±8 g/±16 g selectable full scale

■±250/±500/±2000 dps selectable full scale

■SPI/I2C serial interface

■Embedded Temperature Sensor

■Embedded FIFOs

■ECOPACK® RoHS and “Green” compliant

Application

■GPS navigation systems

■Impact recognition and logging

■Gaming and virtual reality input devices

■Motion activated functions

Datasheet — target specification

LGA-24L (3x3.5x1 mm)

The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics.

The LSM330 has an user-selectable full scale acceleration range of ±2 g/±4 g/±6 g/±8 g/±16 g and angular rate range of ±250/±500/±2000 d.The accelerometer and gyroscope sensors can be either activated or separately put in Powerdown/ sleep mode for applications optimized for power saving.

The LSM330 is available in a plastic land grid array (LGA) package.

■Intelligent power saving for handheld devices

■Vibration monitoring and compensation

■Free-fall detection

■6D orientation detection

Description

Table 1.	Device summary
Part number		Temperature	Package	Packing
		range [°C]
LSM330		-40 to +85	LGA-24L	Tray
				Tape
LSM330TR		-40 to +85	(3x3.5x1mm)
				and reel

The LSM330 is a system-in-package featuring a 3D digital accelerometer with two embedded state machines that can be programmed to implement autonomous applications and a 3D digital gyroscope.

ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes.

July 2012

Doc ID 023426 Rev 1

1/76

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

www.st.com

Contents	LSM330

Contents

1	Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 7
	1.1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	1.2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
2	Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10

2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3	Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	3.1	Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.2	Zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
4	Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16

4.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Linear acceleration sensor digital main blocks . . . . . . . . . . . . . . . . . . . . . 16

4.2.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.3 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.5 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.6 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.7 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.8 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3 Angular rate sensor digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.1 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.2 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.3 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.4 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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4.3.5 Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.6 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.7 Retrieve data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.8 Level-sensitive / edge-sensitive data enable . . . . . . . . . . . . . . . . . . . . . 23 4.3.9 Level-sensitive trigger stamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.10 Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5	Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
	5.1	External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	26
	5.2	Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
6	Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28
	6.1	I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28

6.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

		6.2.1	SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
		6.2.2	SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
		6.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
7	Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			35
8	Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			39
	8.1	WHO_AM_I_A (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
	8.2	CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
	8.3	CTRL_REG5_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		39
	8.4	CTRL_REG6_A (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	8.5	CTRL_REG7_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		41
	8.6	STATUS_REG_A (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	8.7	OFF_X (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	8.8	OFF_Y (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		42
	8.9	OFF_Z (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	8.10	CS_X (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	8.11	CS_Y (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43
	8.12	CS_Z (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		43

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8.13	LC_L (16h) and LC_H (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 43
8.14	STAT (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 44
8.15	VFC_1 (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 44
8.16	VFC_2 (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 44
8.17	VFC_3 (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 45
8.18	VFC_4 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 45
8.19	THRS3 (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 45
8.20	OUT_X_L_A (28h) and OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . .	. . . 45
8.21	OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . .	. . . 45
8.22	OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . .	. . . 45
8.23	FIFO_CTRL_REG_A (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 45
8.24	FIFO_SRC_REG_A (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 46
8.25	CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 46
8.26	STx_1 (40h-4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 47
8.27	TIM4_1 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 47
8.28	TIM3_1 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 47
8.29	TIM2_1 (52h - 53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 47
8.30	TIM1_1 (54h - 55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 48
8.31	THRS2_1 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 48
8.32	THRS1_1(57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 48
8.33	MASKB_1 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 48
8.34	MASKA_1(5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 49
8.35	SETT1 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 49
8.36	PR1 (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 50
8.37	TC1 (5Dh-5E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 50
8.38	OUTS1 (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 51
8.39	PEAK1 (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 51
8.40	CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 51
8.41	STx_2 (60h-6Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 52
8.42	TIM4_2 (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 52
8.43	TIM3_2 (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 52
8.44	TIM2_2 (72h - 73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 52
8.45	TIM1_2 (74h - 75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 53

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8.46	THRS2_2 (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 53
8.47	THRS1_2 (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 53
8.48	MASKB_2 (79h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 53
8.49	MASKA_2 (7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 54
8.50	SETT2 (7Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 54
8.51	PR2 (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 55
8.52	TC2 (7Dh-7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 55
8.53	OUTS2 (7Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 55
8.54	PEAK2 (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 56
8.55	DES2 (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 56
8.56	WHO_AM_I_G (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 56
8.57	CTRL_REG1_G (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 57
8.58	CTRL_REG2_G (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 58
8.59	CTRL_REG3_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 59
8.60	CTRL_REG4_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 59
8.61	CTRL_REG5_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 60
8.62	REFERENCE_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 61
8.63	OUT_TEMP_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 61
8.64	STATUS_REG_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 61
8.65	OUT_X_L_G (28h), OUT_X_H_G (29h) . . . . . . . . . . . . . . . . . . . . .	. . . . 62
8.66	OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) . . . . . . . . . . . . . . . . . . . . .	. . . . 62
8.67	OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) . . . . . . . . . . . . . . . . . . . . .	. . . . 62
8.68	FIFO_CTRL_REG_G (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 62
8.69	FIFO_SRC_REG_G (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 63
8.70	INT1_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 63
8.71	INT1_SRC_G (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 64
8.72	INT1_THS_XH_G (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 65
8.73	INT1_THS_XL_G (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 65
8.74	INT1_THS_YH _G (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 65
8.75	INT1_THS_YL_G (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 65
8.76	INT1_THS_ZH_G (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 66
8.77	INT1_THS_ZL_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 66
8.78	INT1_DURATION_G (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 66

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9	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 69
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 72

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LSM330	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. I2C slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. LSM330 accelerometer state machines: sequence of state to execute an algorithm. . . . . 21 Table 10. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 11. Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 14. Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 33 Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 33 Table 16. Linear Acceleration SAD+Read/Write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Angular rate SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 18. Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 19. WHO_AM_I_A register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 20. CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 21. CTRL_REG4_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22. CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 23. CTRL_REG5_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 24. CTRL_REG5_A Output Data Rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 25. CTRL_REG6_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 26. CTRL_REG6_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 27. CTRL_REG7_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 28. CTRL_REG7_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 29. STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 30. STATUS_REG_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 31. OFF_X default valu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 32. OFF_Y default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 33. OFF_Z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 34. CS_X default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 35. CS_Y default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 36. CS_Z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 37. LC_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 38. LC_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 39. STAT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 40. STAT register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 41. VFC_1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 42. VFC_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 43. VFC_3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 44. VFC_4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 45. THRS3 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 46. FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 47. FIFO_CTRL_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 48. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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Table 49. FIFO_SRC_REG_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 50. IFO_SRC_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 51. CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 52. CTRL_REG2_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 53. STx_1 registers default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 54. TIM4_1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 55. TIM4_1 default valu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 56. TIM3_1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 57. TIM2_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 58. TIM2_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 59. TIM1_1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 60. TIM1_1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 61. THRS2_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 62. THRS1_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 63. MASKB_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 64. MASKB_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 65. MASKA_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 66. MASKA_1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 67. SETT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 68. SETT1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 69. PR1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 70. PR1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 71. TC1_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 72. TC1_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 73. OUTS1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 74. OUTS1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 75. PEAK1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 76. CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 77. CTRL_REG3_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 78. STx_2 registers default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 79. TIM4_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 80. TIM3_2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 81. TIM2_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 82. TIM2_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 83. TIM1_2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 84. TIM1_2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 85. THRS2_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 86. THRS1_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 87. MASKB_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 88. MASKB_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 89. MASKA_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 90. MASKA_2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 91. SETT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 92. SETT2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 93. PR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 94. PR2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 95. TC2_L default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 96. TC2_H default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 97. OUTS2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 98. OUTS2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 99. PEAK2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 100. DES2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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LSM330	List of tables

Table 101. WHO_AM_I_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 102. CTRL_REG1_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 103. CTRL_REG1_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 104. DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 105. Power mode selection configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 106. CTRL_REG2_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 107. CTRL_REG2_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 108. High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 109. High-pass filter cut-off frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 110. CTRL_REG3_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 111. CTRL_REG3_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 112. CTRL_REG4_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 113. CTRL_REG4_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 114. CTRL_REG5_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 115. CTRL_REG5_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 116. REFERENCE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 117. REFERENCE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 118. OUT_TEMP_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 119. OUT_TEMP_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 120. STATUS_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 121. STATUS_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 122. FIFO_CTRL_REG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 123. FIFO_CTRL_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 124. FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 125. FIFO_SRC_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 126. FIFO_SRC_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 127. INT1_CFG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 128. INT1_CFG_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 129. INT1_SRC_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 130. INT1_SRC_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 131. INT1_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 132. INT1_THS_XH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 133. INT1_THS_XL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 134. INT1_THS_XL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 135. INT1_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 136. INT1_THS_YH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 137. INT1_THS_YL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 138. INT1_THS_YL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 139. INT1_THS_ZH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 140. INT1_THS_ZH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 141. INT1_THS_ZL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 142. INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 143. INT1_DURATION_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 144. INT1_DURATION_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 145. LGA (3.5x3x1 mm) 24 lead mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 146. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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List of figures	LSM330

List of figures

Figure 1. LSM330 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Angular rate sensor digital block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. Bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10. Trigger stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. Level-sensitive trigger stamping (LVLen = 1; EXTRen = 0) . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12. Edge-sensitive trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. LSM330 electrical connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 15. SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 16. Multiple-byte SPI read protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 17. SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18. Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 19. SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 20. INT1_Sel and Out_Sel configuration block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 21. Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 22. Wait enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 23. LGA 3.5x3x1 24 leads drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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LSM330	Block diagram and pin description

1 Block diagram and pin description

1.1Block diagram

Figure 1. LSM330 block diagram

I (a)

I (Ω)

Sensing Block

Sensing Interface

X+
Y+		CHARGE
Z+		AMPLIFIER
				STATE
		LOW-PASS		MACHINES
	MUX		ADC2	AND
		FILTER		CONTROL
				LOGIC
Z-

Y-

X-

X+

Y+

CHARGE

AMPLIFIER DEMODULATOR

Z+

LOW-PASS		ADC1		DIGITAL
FILTER				FILTER

MUX

Z-

Y-

X-		ANALOG
		CONDITIONING

Feedback+

Feedback-

AUTOMATIC

Drive- GAIN

CONTROL

VOLTAGE

GAIN

AMPLIFIER

Drive+

PHASE		REFERENCE		TRIMMING
GENERATOR				CIRCUITS

CONTROL LOGIC

& CLOCK INTERRUPT GEN.

I2C/SPI

CS_A

CS_G

SDA/SDI_A/G

SDO_A

SDO_G

INT1_A

INT2_A

INT1_G

DEN_G

DRDY_G/INT2_G

SCL_A/G

AM14723V1

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Block diagram and pin description	LSM330

1.2Pin description

Figure 2. Pin connection

Z Y

DIRECTION OF

DETECTABLE

ACCELERATIONS

X

+Ω Z

Z Y

1

X

+Ω Y DIRECTION OF DETECTABLE ANGULAR RATE

X +Ω X

SRE

GND

GND

CAP

VDD

VDD

VDD

IO_VDD

18

RES

SCL_A/G

RES

(BOTTOM VIEW)

VDD_IO

RES

SDA/SDI_A/G

RES

SDO_G

13

6

G_DEN

A_INT2

A_INT1

G_INT1

_G/INT2_DRDY

A_SC

G_SC

A_DOS

G

AM14724V1

Table 2.	Pin description
Pin#		Name	Function
1		Vdd_IO(1)	Power supply for IO pins
2		SCL_A/G	I2C serial clock (SCL)/SPI serial port clock (SPC)
3		Vdd_IO(1)	Power supply for IO pins
			I2C serial data (SDA)
4		SDA/SDI_A/G	SPI serial data input (SDI)
			3-wire interface serial data output (SDO)
			Gyroscope:
5		SDO_G	SPI serial data output (SDO)
			I2C least significant bit of the device address (SA0)
			Accelerometer:
6		SDO_A	SPI serial data output (SDO)
			I2C least significant bit of the device address (SA0)
			Gyroscope: SPI enable
7		CS_G	I2C/SPI mode selection (1: SPI idle mode / I2C communication
			enabled; 0: SPI communication mode / I2C disabled)
			Accelerometer: SPI enable
8		CS_A	I2C/SPI mode selection (1: SPI idle mode / I2C communication
			enabled; 0: SPI communication mode / I2C disabled)
9		DRDY_G/	Gyroscope Data Ready/FIFO Interrupt
		INT2_G	(Watermark/Overrun/Empty)

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LSM330				Block diagram and pin description
	Table 2.	Pin description		(continued)
	Pin#		Name	Function
	10		INT1_G	Gyroscope interrupt signal
	11		INT1_A	Accelerometer interrupt1 signal
	12		INT2_A	Accelerometer interrupt2 signal
	13		DEN_G	Gyroscope Data Enable
	14		Res	Reserved. Connect to GND
	15		Res	Reserved. Connect to GND
	16		Res	Reserved. Connect to GND
	17		Res	Reserved. Connect to GND
	18		Res	Reserved. Connect to GND
	19		GND	0 V supply
	20		GND	0 V supply
	21		CAP	Connect to GND with ceramic capacitor(2)
	22		Vdd(3)	Power supply
	23		Vdd(3)	Power supply
	24		Vdd(3)	Power supply

1.100 nF filter capacitor recommended.

2.10 nF (+/- 10%), 25V. 1nF minimum value has to be guaranteed under 11V bias condition1.

3.100 nF plus 10 µF capacitors recommended.

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Module specifications	LSM330

2 Module specifications

2.1Mechanical characteristics

@ Vdd = 3V, T = 25 °C unless otherwise noted (a)

Table 3.	Mechanical characteristics
Symbol	Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
		FS bit set to 000		±2.0
		FS bit set to 001		±4.0
	Linear acceleration measurement
LA_FS		FS bit set to 010		±6.0		g
	range(2)
		FS bit set to 011		±8.0
		FS bit set to 100		±16.0
	Angular rate	FS bit set to 00		±250
G_FS
		FS bit set to 01		±500		dps
	measurement range(3)
		FS bit set to 10		±2000
		FS bit set to 000		0.061
		FS bit set to 001		0.122
LA_So	Linear acceleration sensitivity	FS bit set to 010		0.183		mg/digit
		FS bit set to 011		0.244
		FS bit set to 100		0.732
		FS = ±250 dps		8.75		mdps/
G_So	Angular rate sensitivity	FS = ±500 dps		17.50
						digit
		FS = ±2000 dps		70
LA_TyOff	Linear acceleration typical zero-g	FS bit set to 000		±60		mg
	level offset accuracy(3)
		FS = 250 dps		±10
	Angular rate typical zero-rate
G_TyOff		FS = 500 dps		±15		dps
	level(4)
		FS = 2000 dps		±25
Top	Operating temperature range		-40		+85	°C

1.Typical specifications are not guaranteed.

2.Verified by wafer level test and measurement of initial offset and sensitivity.

3.Typical zero-g level offset value after MSL3 preconditioning.

4.Offset can be eliminated by enabling the built-in high-pass filter.

a. The product is factory calibrated at 3.0 V. The operational power supply range is from 2.4 V to 3.6 V.

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LSM330	Module specifications

2.2Electrical characteristics

@ Vdd = 3 V, T = 25 °C unless otherwise noted

Table 4.	Electrical characteristics
Symbol		Parameter	Test conditions	Min.	Typ.(1)	Max.	Unit
Vdd		Supply voltage		2.4		3.6	V
Vdd_IO		Power supply for I/O		1.71		Vdd+0.1	V
LA_Idd		Accelerometer current	1.6 kHz ODR		250		µA
		consumption in Normal mode	3.125 Hz ODR		10
		Accelerometer current
LA_IddPdn		consumption in Power-down			1		µA
		mode
G_Idd		Gyroscope current			6.1		mA
		consumption in Normal mode
G_IddLowP		Gyroscope supply current			2		mA
		in Sleep mode(2)
		Gyroscope current
G_IddPdn		consumption in Power-down			5		µA
		mode
VIH		Digital high level input voltage		0.8*Vdd_IO			V
VIL		Digital low level input voltage				0.2*Vdd_IO	V
VOH		High level output voltage		0.9*Vdd_IO			V
VOL		Low level output voltage				0.1*Vdd_IO	V
Top		Operating temperature range		-40		+85	°C

1.Typical specifications are not guaranteed.

2.Sleep mode introduces a faster turn-on time compared to Power-down mode.

2.3Temperature sensor characteristics

@ Vdd = 3V, T = 25 °C unless otherwise noted (b)

Table 5.	Temperature sensor characteristics
Symbol	Parameter	Test condition	Min.	Typ.(1)	Max.	Unit
TSDr	Temperature sensor output			-1		°C/digit
	change vs. temperature
		-
TODR	Temperature refresh rate			1		Hz
Top	Operating temperature range		-40		+85	°C

1.Typical specifications are not guaranteed.

b.The product is factory calibrated at 3.0 V.

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Module specifications	LSM330

2.4Communication interface characteristics

2.4.1SPI - serial peripheral interface

Subject to general operating conditions for Vdd and TOP.

Table 6.	SPI slave timing values
Symbol		Parameter(1)		Value (2)		Unit
			Min		Max
tc(SPC)		SPI clock cycle	100			ns
fc(SPC)		SPI clock frequency			10	MHz
tsu(CS)		CS setup time	6
th(CS)		CS hold time	8
tsu(SI)		SDI input setup time	5
th(SI)		SDI input hold time	15			ns
tv(SO)		SDO valid output time			50
th(SO)		SDO output hold time	9
tdis(SO)		SDO output disable time			50

1.Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.

2.Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results. Not tested in production.

Figure 3. SPI slave timing diagram(c)
CS	(2)				(2)
	su(CS)		c(SPC)	h(CS)
SPC	(2)				(2)
	su(SI)	h(SI)
SDI	(2)	M SB IN		LSB IN	(2)
		v(SO)	h(SO)		dis(SO)
SDO	(2)	M SB OUT		LSB OUT	(2)

2. Data on CS, SPC, SDI and SDO refer to pins: CS_A, CS_G, SCL_A/G, SDA_A/G, SDO_A / SDO_G.

c.Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.

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LSM330	Module specifications

2.4.2I2C - inter IC control interface

Subject to general operating conditions for Vdd and TOP.

Table 7.	I2C slave timing values
Symbol		Parameter(1)	I2C standard mode (1)		I2C fast mode (1)			Unit
			Min.	Max.	Min.		Max.
f(SCL)		SCL clock frequency	0	100	0		400	KHz
tw(SCLL)		SCL clock low time	4.7		1.3			µs
tw(SCLH)		SCL clock high time	4.0		0.6
tsu(SDA)		SDA setup time	250		100			ns
th(SDA)		SDA data hold time	0.01	3.45	0		0.9	µs
tr(SDA) tr(SCL)		SDA and SCL rise time		1000	20 + 0.1C	(2)	300
						b		ns
tf(SDA) tf(SCL)		SDA and SCL fall time		300	20 + 0.1C	(2)	300
						b
th(ST)		START condition hold time	4		0.6
tsu(SR)		Repeated START condition	4.7		0.6
		setup time
								µs
tsu(SP)		STOP condition setup time	4		0.6
tw(SP:SR)		Bus free time between STOP	4.7		1.3
		and START condition

1.SCL (SCL_A/G pin), SDA (SDA_A/G pin).

2.Cb = total capacitance of one bus line, in pF

Figure 4. I2C slave timing diagram(d)

				5(3($7('
	67$57				67$57
				VX 65	67$57
6'$				WZ 63 65
WI 6'$	WU 6'$		WVX 6'$	WK 6'$
				WVX 63	6723
6&/
WK 67	WZ 6&//	WZ 6&/+	WU 6&/	WI 6&/	!-V

d. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.

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Module specifications	LSM330

2.5Absolute maximum ratings

Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

	Table 8.	Absolute maximum ratings(1)
	Symbol	Ratings	Maximum value	Unit
	Vdd	Supply voltage	-0.3 to 4.8	V
	Vdd_IO	I/O pins supply voltage	-0.3 to 4.8	V
	Vin	Input voltage on any control pin (SCL_A/G, SDA_A/G,	-0.3 to Vdd_IO +0.3	V
		SDO_A, SDO_G, CS_A, CS_G, DEN_G)
	APOW	Acceleration (any axis, powered, Vdd = 3 V)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	AUNP	Acceleration (any axis, unpowered)	3000 g for 0.5 ms
			10000 g for 0.1 ms
	TOP	Operating temperature range	-40 to +85	°C
	TSTG	Storage temperature range	-40 to +125	°C
	ESD	Electrostatic discharge protection	2 (HBM)	kV

1. Supply voltage on any pin should never exceed 4.8 V.

This is a mechanical shock sensitive device, improper handling can cause permanent damage to the part.

This is an ESD sensitive device, improper handling can cause permanent damage to the part.

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LSM330	Terminology

3 Terminology

3.1Sensitivity

Linear acceleration sensitivity can be determined e.g. by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors.

Angular Rate Sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to the device. This value changes very little overtemperature and also very little overtime.

3.2Zero-g and zero rate level

Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X axis and Y axes, whereas the Z axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset.

Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors.

Angular rate zero-rate level describes the actual output value if there is no angular rate present. zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little overtemperature and overtime.

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Functionality	LSM330

4 Functionality

The LSM330 is a system-in-package featuring a 3D digital accelerometer with two embedded state machines and a 3D digital gyroscope, together with two FIFO memory block available to manage linear acceleration and angular rate data.

The device includes specific sensing elements and two IC interfaces capable to measuring both the acceleration and angular rate applied to the module and to provide a signal to external applications through an SPI/I2C serial interface.

The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics.

4.1Power modes

The linear acceleration sensor and the angular rate sensor can be either activated or separately set in Power-down/ sleep mode for applications optimized for power saving.

The acceleration sensor operating modes can be selected between normal or power-down trough the CTRL_REG5_A (20h); the angular rate sensor operating mode can be selected among normal power-down or sleep mode, through CTRL_REG1_G (20h).

4.2Linear acceleration sensor digital main blocks

4.2.1State machine

The LSM330 embeds two state machines able to run a user defined program.

The program is composed by a set of instructions that define the transition to successive states. Conditional branches are possible.

From each state (n) it is possible to have transition to next state (n+1) or to reset state. Transition to Reset Point happens when “RESET condition” is true; Transition to next step happens when “NEXT condition” is true.

Interrupt is triggered when Output/Stop/Continue state is reached.

Each State machine allows to implement in a flexible way gesture recognition, Free Fall, Wake-up, 4D/6D orientation, pulse counter and step recognition, click/double click, shake/double shake, face up/face down, turn/double turn:

–Code and parameters are loaded by host into dedicated memory areas for the state program

–State program with timing based on ODR or decimated time

–Possibiliy of conditional branches

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LSM330	Functionality

Table 9. LSM330 accelerometer state machines: sequence of state to execute an algorithm

START
State 1
reset
next
reset
State 2
next
reset
State 3
next
State n reset
OUTPUT/STOP/CONTINUE	INT set

AM14725v1

4.2.2FIFO

LSM330 embeds 32 slots of data FIFO for each of the three acceleration output

channels: X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. In order to use FIFO it is necessary to enable FIFO_EN bit in CTRL_REG7_A (25h) register.

FIFO buffer can work accordingly in five different modes: Bypass mode, FIFO mode, Stream mode, Stream-to-FIFO mode and Bypass-to-Stream mode. Each mode is selected by FMODE [2:0] bits in the FIFO_CTRL_REG_A (2Eh) register. Programmable watermark level, FIFO empty or FIFO overrun events can be enabled to generate dedicated interrupts on the INT1_A/INT2_A pin (configured through INT2_EN and INT1_EN bits in the

CTRL_REG4_A (23h) register).

When FIFO is empty, EMPTY bit in FIFO_SRC_REG_A (2Fh) is equal to '1' and no samples are available.

If the application requires a lower number of samples a programmable watermark level can be set. In FIFO_SRC_REG_A (2Fh) WTM bit is high if a new data arrives and FSS [4:0] bit in FIFO_SRC_REG_A (2Fh) is greater than or equal to WTMP [4:0] bit in

FIFO_CTRL_REG_A (2Eh) register. In FIFO_SRC_REG_A (2Fh) WTM bit goes to '0' if reading X, Y, Z data slot from FIFO and FSS [4:0] bit in FIFO_SRC_REG_A (2Fh) is minor than or equal to WTMP [4:0] bit in FIFO_CTRL_REG_A (2Eh) register.

When FIFO is completely filled, OVRN_FIFO bit in FIFO_SRC_REG_A (2Fh) is equal to '1' and FIFO slot is overwritten.

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4.2.3Bypass mode

In Bypass mode, the FIFO is not operational and it remains empty. For each channel only the first address is used. The remaining FIFO slots are empty.

Bypass mode must be used in order to reset the FIFO buffer when a different mode is operating (i.e. FIFO mode).

4.2.4FIFO mode

In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels until it is full (32 samples set stored). When the FIFO is full it stops collecting data from the input channels and the FIFO content remains unchanged.

An overrun interrupt can be enabled, P1_OVERRUN = '1' in CTRL_REG7_A (25h) register, in order to be raised when the FIFO stops collecting data. When overrun interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input channels.

At the end of the reading procedure it is necessary to transit from Bypass mode to reset FIFO content. . After this reset command it is possible to restart FIFO mode writing FMODE [2:0] the value '001' in FIFO_CTRL_REG_A (2Eh) register.

FIFO buffer can memorize 32 X, Y and Z data but the depth of the FIFO can be reduced by a programmable watermark. In order to enable FIFO watermark, WTM_EN bit in CTRL_REG7_A (25h) is high and the FIFO depth is set in WTMP [4:0] bits in FIFO_CTRL_REG_A (2Eh) register. The watermark interrupt can be enable in INT1_A pad if P1_WTM bit in CTRL_REG7_A (25h) register is enable.

4.2.5Stream mode

In Stream mode FIFO continues filling data from X, Y, and Z accelerometer channels, when the buffer is full (32 samples set stored) the FIFO buffer index restarts from the beginning and older data is replaced by the current. The oldest values continue to be overwritten until a read operation makes free FIFO slots available.

An overrun interrupt can be enabled, P1_OVERRUN = '1' in CTRL_REG7_A (25h) register, in order to read the whole FIFO content at once. If in the application it is mandatory not to lose data and it is not possible to read at least one sample for each axis within one ODR period, a watermark interrupt can be enabled in order to read partially the FIFO and let free memory slots for data incoming.

Setting the WTMP [4:0] bit in FIFO_CTRL_REG_A (2Eh) register to N value, the number of X, Y and Z data samples that should be read at watermark interrupt rising is up to (N+1).

In the latter case reading all FIFO content before an overrun interrupt has occurred, the first data read is equal to the last already read in previous burst, so the number of new data available in FIFO depends on previous reading (see FIFO_SRC_REG_A (2Fh)) .

At the end of the reading procedure it is necessary to transit from Bypass mode to reset FIFO content.

4.2.6Stream-to-FIFO mode

In Stream-to-FIFO mode FIFO behavior changes according to interrupt generated by the configuration of the two state machine by INT_SM1and INT_SM2 bits in STAT (18h) register.

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When INT_SM1, INT_SM2 bits in STAT (18h) register are equal to '1' FIFO operates in FIFO mode, when INT_SM1, INT_SM2 bit in STAT (18h) register are equal to '0' FIFO operates in Stream mode.

4.2.7Bypass-to-stream mode

In Bypass-to-stream mode, the FIFO starts operating in Bypass mode and once a trigger event occurs (STAT (18h) the FIFO starts operating in Stream mode.

4.2.8Retrieve data from FIFO

FIFO data is read through OUT_X_L_A (28h) and OUT_X_H_A (29h), OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh). When the FIFO is in Stream, Trigger or FIFO mode, a read operation to the OUT_X_L_A (28h) and OUT_X_H_A (29h), OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) or OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh) registers provides the data stored in the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_L_A (28h) and OUT_X_H_A (29h), OUT_Y_L_A (2Ah) and OUT_Y_H_A (2Bh) and OUT_Z_L_A (2Ch) and OUT_Z_H_A (2Dh) registers and both single read and read_burst operations can be used.

4.3Angular rate sensor digital main blocks

Figure 5. Angular rate sensor digital block diagram

					Out_Sel
					00
					01	DataReg
			0			FIFO
					10
				LPF2		32x16x3
					11
			1			I2C
ADC	LPF1	HPF
			HPen		INT_Sel	SPI
					10
					11	Interrupt
					01	generator
					00
						SCR REG
						CONF REG
						INT1
						AM07230v1

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