ST LNBK20D2 User Manual

LNB SUPPLY AND CONTROL VOLTAGE

REGULATOR (PARALLEL INTERFACE)

■ COMPLETE INTERFACE FOR TWO LNBs

REMOTE SUPPLY AND CONTROL

■ GUARANTEED 400mA OUTPUT CURRENT

■ LNB SELECTION AND STAND-BY

FUNCTION

■ BUILT-IN TONE OSCILLATOR FACTORY

TRIMMED AT 22KHz

■ FAST OSCILLATORSTART-UP FACILITATES

DiSEqC

■ TWO SUPPLY INPUTS FOR LOWEST

DISSIPATION

■ BYPASS FUNCTION FOR SLAVE

OPERATION

■ LNB SHORT CIRCUIT PROTECTION AND

DIAGNOSTIC

■ AUXILIARY MODULATIO N INPUT EXTENDS

FLEXIBILITY

■ CABLE LENGTH COMPENSATION

■ INTERNAL OVER TEMPERATURE

PROTECTION

■ BACKWARD CURRENT PROTECTION

■ COST-EFFECTIVE VERSION OF LNBP

SERIES

DESCRIPTION

Intended for analog and digital satellite receivers,
the LNBK20D2 is a monolithic linear voltage
regulator, assembled in SO-20, specifically
designed to provide the powering voltages and the
interfacing signals to the LNB downconverter
situated in the antenna via the coaxial c able. It has
the same functionality of the LNBP1X and
LNBP20 s eries, at a reduced output current
capability. Since most satellite receivers have two
antenna ports, the output voltage of the regulator
is av ailable at one of two logic-selectable output
pins (LNBA, LNBB). When the IC is powered and
put in Stand-by (EN pin LOW), both regulator
outputs are disabled to allow the antenna
downconverters to be supplied/controlled by
others satellite receivers s haring the s ame coaxial
lines. In this occurrence the device will limit at 3
mA (max) the backward current that could flow
from LNBA and LNBB output p ins t o GND.
For slave operation in single dish, dual receiver
systems, the bypass function is implemented by
an electronic switch between t he Master Input pin



ENCODING

LNBK20D2

SO-20

(MI) and the LNBA pin, thu s leaving all LNB
powering and control functions to the Master
Receiver. This electronic switch is c losed when
the device is powered and EN pin is LOW.
The r egulator outputs c an be logic controlled to be
13 or 18 V (typ.) by mean of the VSEL pin for
remote controlling of LNBs. Additionally, it is
possible to incr ement by 1V (typ.) the select ed
voltage value to compensate t he excess voltage
drop along th e coax ial cable (LLC pin HIGH).
In orde r to reduce the power dissipation of the
device when the l owes t output voltage is selected,
the regulator has two Supply Input pins V
V

. They must be powered res pectively at 16V

CC2

(min) and 23V (min), and an internal switch
automatically will select the suitable supply pin
according to the selected output voltage. If
adequate heatsink is provided and higher power
losses are acceptable, both su pply pins can be
powered by the sam e 23V source without
affecting any other circuit performance.
The ENT (T one Enable) pin activates the internal
oscillator so that the DC output is modulated by a
±0.3 V, 22KHz (typ.) square wave. This interna l
oscillator is factory trimmed within a tolerance of
±2KHz, thus no further adjustments neither
external components are required.
A burst coding of the 22KHz tone can be
accomplished thanks to the fast response of the
ENT i nput and the prompt oscillator start-up. This
helps designers who want to implement the
DiSEqC



protocols (*).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is

CC1

and

1/14July 2003

LNBK20D2

available (EXTM). An appropriate DC blo cki ng
capacitor must be used to couple the m odulating
signal source to the EXTM pin. When external
modulation is not use d, the relevant pin can be left
open.
Two pins are dedicated to the overcurrent
protection/monitoring: CEXT and OLF. The
overcurrent protection circuit works dynamically:
as soon as an overload i s detected in either LNB
output, the output is shut-down for a time Toff
determined by the capacitor connec ted between
CEXT and GND. Simultaneously the OLF pin, t hat
is an open collector diagnostic output flag, from
HIGH IMPEDANCE state goes LOW.
After t he time has elapsed, the output is resumed
for a time t

(*): External components are needed to comply to level 2.x and above (bidirectiona) DiSEqCbus hardware requirements. DiSEqCis a
trademark or EUTELSAT.

=1/15t

on

(typ.) and OLF goes in HIGH

off

IMPEDANCE. If the overload is still present, the
protection circuit will cycle again through t
ton until the overload is removed. Typical t

and

off

on+toff

value is 1200ms when a 4.7µF external capacitor
is used.
This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still
ensuring excellent power-on start up even with
highly capacitive loads on LNB outputs.
The device is packaged in Multiwatt15 for
thru-holes mou nting and in PowerSO-20 for
surface mounting. When a limited functionality in a
smaller package matches design needs, a range
of cost-effective PowerSO-10 solutions is also
offered. All version s have built-in thermal
protection agains t overheating damage.

PIN CONFIGURA TION (top view)

2/14

LNBK20D2

TABLE A: PIN CONFIGURATIONS

PIN N° SYMBOL NAME FUNCTION

1 LLC Line Length Compens.

(1V typ)

2 OLF Over Load Flag Logic output (open collector). Normally in HIGH

3 MI Master Input In stand-by mode, the voltage on MI is routed to LNBA pin.

4 LNBB Output Port See truth tables for voltage and port selection

5, 6, 15,

GND Ground Circuit Ground. It is internally connected to the die frame

16

7, 13 N.C. Not Connected

8V

9V

CC1

CC2

Supply Input 1 15V to 27V supply. It is automatically selected when

Supply Input 2 22V to 27V supply. It is automatically selected when

10 LNBA Output Port See truth table voltage and port selection. In stand-by mode

11 V

SEL

Output Voltage Selection:

13 or 18V (typ)
12 EN Port Enable Logic control input: see truth table
14 OSEL Port Selection Logic control input: see truth table
18 ENT 22KHz Tone Enable Logic control input: see truth table
19 CEXT External Capacitor Timing Capacitor used by the Dynamic Overload protection.

20 EXTM External Modulator External Modulation Input. Needs DC decoupling to the AC

NOTE: the limited pin availability of the PowerSO-10 package leads to drop some f unctions.

Logic control input: see truth table

IMPEDANCE, goes LOW when current or thermal overload
occurs

Can be left open if bypass function is not needed

=13or14V

V

OUT

=18or19V

V

OUT

this port is powered by the MI pin via the internal Bypass
Switch

Logic control input: see truth table

Typical application is 4.7µF for a 1200ms cycle

source. if not used, can be left open.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter² Value Unit

V
I
V

I

SW

P

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.

DC Input Voltage (V

I

Output Current (LNBA, LNBB)

O

Logic Input Voltage (ENT, EN OSEL, VSEL, LLC)

I

CC1,VCC2

, MI)

Bypass Switch Current
Power Dissipation at T

D

Storage Temperature Range

stg

Operating Junction Temperature Range

op

case

< 85°C

28 V

Internally Limited mA

-0.5 to 7 V
900 mA

3W

-40 to +150 °C

-40 to +125 °C

THERMAL DATA

Symbol Parameter Value Unit

R

thj-case

Thermal Resistance Junction-case

15 °C/W

3/14

LNBK20D2

LOGIC CONTROLS TRUTH TABL E

CONTROL I/O PIN NAME L H

OUT OLF I

OUT>IOMAX

IN ENT 22KHz tone OFF 22KHz tone ON
IN EN See Table Below See Table Below
IN OSEL See Table Below See Table Below
IN VSEL See Table Below See Table Below
IN LLC See Table Below See Table Below

or Tj>150°C I

OUT<IOMAX

EN OSEL VSEL LLCO

LXXXV

V

LNBA

- 0.4V (typ.) Disabled

MI

H L L L 13V (typ.) Disabled
H L H L 18V (typ.) Disabled
H L L H 14V (typ.) Disabled
H L H H 19V (typ.) Disabled
H H L L Disabled 13V (typ.)
H H H L Disabled 18V (typ.)
H H L H Disabled 14V (typ.)
HHHH Disabled 19V (typ.)

NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ)

BLOCK DIAGRAM

V

LNBB

4/14

LNBK20D2

ELECTRICAL CHARACTERISTICS FOR LNBK SERIES (TJ= 0 to 85°C, CI=0.22µF, CO=0.1µF,

EN=H,ENT=L,LLC=L,V

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

IN1VCC1

V

IN2VCC2

V

O1

V

O2

∆V

O

∆V

O

SVR Supply Voltage Rejection V
I

MAX

t

OFF

t

ON

f

TONE

A

TONE

D

TONE

t

r,tf

G

EXTM

V

EXTM

Z

EXTM

V

SW

V

OL

I

OZ

V

IL

V

IH

I

IH

I

CC

I

OBK

T

SHDN

Supply Voltage IO= 400 mA ENT=H, VSEL=L, LLC=L 15 27 V

Supply Voltage IO= 400 mA ENT=H, VSEL=L, LLC=L 22 27 V

Output Voltage IO= 400 mA VSEL=L, LLC=L 17.3 18 18.7 V

Output Voltage IO= 400 mA VSEL=L, LLC=L 12.5 13 13.5 V

Line Regulation V

Load Regulation V

Output Current Limiting 500 650 800 mA
Dynamic Overload

protection OFF Time
Dynamic Overload

protection ON Time
Tone Frequency ENT=H 20 22 24 KHz

Tone Amplitude ENT=H 0.55 0.72 0.9 Vpp
Tone Duty Cycle ENT=H 40 50 60 %
Tone Rise and Fall Time ENT=H 5 10 15 µs
External Modulation Gain ∆V
External Modulation Input

Voltage
External Modulation

Impedance
Bypass Switch Voltage

Drop (MI to LNBA)
Overload Flag Pin Logic

LOW
Overload Flag Pin OFF

State Leakage Current
Control Input Pin Logic

LOW
Control Input Pin Logic

HIGH
Control Pins Input Current VIH=5V 20 µA

Supply Current Output Disabled (EN=L) 0.3 1 mA

Output Backward Current EN=L V

Temperature Shutdown
Threshold

=16V, V

IN1

=23V I

IN2

= 400 mA ENT=H, VSEL=L, LLC=H 16 27 V

I

O

= 400 mA VSEL=L, LLC=H 23 27 V

I

O

I

= 400 mA ENT=H, VSEL=L, LLC=H 19 V

O

= 400 mA ENT=H, VSEL=L, LLC=H 14 V

I

O

=15 to 18V V

IN1

=22 to 25V V

V

IN2
IN1=VIN2

=0to3A

I

O

IN1=VIN2

Output Shorted C

Output Shorted C

/∆V

OUT

=50mA, unless otherwise specified.)

OUT

=13V 5 50 mV

OUT

=18V 5 50 mV

OUT

=22V V

=13 or 18V

OUT

65 150 mV

=23± 0.5Vacfac= 120 Hz, 45 dB

=4.7µF 1100 ms

EXT

=4.7µFt

EXT

, f = 10Hz to 40KHz 5

EXTM

/15 ms

OFF

AC Coupling 400 mVpp

f = 10Hz to 40KHz 400 Ω

EN=L, ISW=300mA, V

CC2-VMI

=4V 0.35 0.6 V

IOL=8mA 0.28 0.5 V

VOH=6V 10 µA

0.8 V

2.5 V

ENT=H, I

V

IN1=VIN2

=500mA 3.1 6 mA

OUT

LNBA=VLNBB

= 18V

0.23mA

= 22V or floating

150 °C

5/14