ST LNBH26S User Manual

LNBH26S

Dual LNBS supply and control IC with step-up and I²C interface

Features

■Complete interface between LNB and I²C bus

■Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A)

■Selectable output current limit by external resistor

■Compliant with main satellite receiver output voltage specification (8 programmable levels)

■Accurate built-in 22 kHz tone generator suits widely accepted standards

■22 kHz tone waveform integrity guaranteed also at no load condition

■Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allowing low power losses

■Overload and overtemperature internal protection with I²C diagnostic bits

■LNB short-circuit dynamic protection

■+/- 4 kV ESD tolerant on output power pins

Applications

■STB satellite receivers

■TV satellite receivers

■PC card satellite receivers

Datasheet − preliminary data

QFN24 (4x4 mm)

Description

Intended for analog and digital DUAL satellite receivers/Sat-TV, Sat-PC cards, the LNBH26S is a monolithic voltage regulator and interface IC, assembled in QFN24 (4x4) specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dishes or to the multi-switch box. In this application field, it offers a complete solution for dual tuner satellite receivers with an extremely low component count and low power dissipation together with simple design and I²C standard interfacing.

Table 1.	Device summary
	Order code	Package	Packaging
	LNBH26SPQR	QFN24 (4x4)	Tape and reel
March 2012		Doc ID 022995 Rev 1	1/29

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to	www.st.com
change without notice.

Contents	LNBH26S

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Application information (valid for each section A/B) . . . . . . . . . . . . . .		. 4
	2.1	DISEQC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4
	2.2	Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . .	4
	2.3	Data encoding by external DiSEqC envelope control
		through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	2.4	Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
	2.5	Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.6	Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.7	Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
	2.8	Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . .	7
	2.9	PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
	2.10	OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . .	7
	2.11	OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
3	Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
4	Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		11
5	Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
6	I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	6.1	Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	6.2	START and STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	6.3	Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	6.4	Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	6.5	Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
7	I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	7.1	Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	7.2	Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	7.3	Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17

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LNBH26S			Contents
	7.4	Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . 19
8	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 21
	8.1	Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 22
9	Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 24
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 28

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Block diagram	LNBH26S

1 Block diagram

Figure 1. Block diagram

		DSQIN-A ADDR SCL SDA			DSQIN-B
LX-A							LX-B
	PWM CTRL		I²C Digital core			PWM CTRL
Isense							Isense
				DAC
PGND				Drop control			PGND
				Tone ctrl
VUP-A				Diagnostics			VUP-B
				Protections
	ctrl	Linear		Current	Linear	ctrl
VOUT-A				Limit			VOUT-B
	Gate					Gate
		Regulator		selection	Regulator
				Voltage
				reference
		ISEL	GND	BYP VCC			AM10482v1

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LNBH26S	Application information (valid for each section A/B)

2 Application information (valid for each section A/B)

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (VUP) that let the integrated LDO post-regulator (generating the 13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP - VOUT = 1 V typ.). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typically). The step-up converter soft-start function reduces the inrush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V.

2.1DISEQC data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC standards, and can be activated in 3 different ways:

1)by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.

2)by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1.

3)through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled high and the EXTM bit set to “0”.

2.2Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the LNBH26S integrated tone generator.

The output tone waveforms are internally controlled by the LNBH26S tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26S activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired. Refer to Figure 2.

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Application information (valid for each section A/B)	LNBH26S

Figure 2. Tone enable and disable timing (using external waveform)

DSQIN

~ 60 µs ~ 1 µs

Tone

Output

AM10426v1

2.3Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this way, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high the internal control circuit activates the 22 kHz tone output.

The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22

kHz TTL signal on DSQIN has expired (refer to Figure 3).

Figure 3. Tone enable and disable timing (using envelope signal)

DSQIN

~ 6 µs	15 µs ~ 60 µs
Tone
Output
	AM10427v1

2.4Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

IMAX (typ.)	=	16578
		RSEL1.206

with ISET=0,

where RSEL is the resistor connected between ISEL and GND expressed in kΩ and IMAX

(typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to 750 mA for each channel. However, it is recommended to not exceed for a long period a total amount of

current of 1 A from both sections (IOUT_A + IOUT_B < 1 A) in order to avoid the overtemperature protection from triggering and to thoroughly validate the PCB layout

thermal management in real application environment conditions.

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LNBH26S	Application information (valid for each section A/B)

2.5Output voltage selection

Each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register (see Section 7.3: Data registers and Table 13: Output voltage selection table (Data1 register, write mode) for exact programmable values). Register writing is accessible via the I²C bus.

2.6Diagnostic and protection functions

The LNBH26S has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to LOW. One diagnostic bit is dedicated to the overtemperature (OTF), and two bits (one per section) are dedicated to overcurrent (OLF-A, OLF-B). One bit is dedicated to the input voltage power not good function (PNG). Once the OTF bit (or OLF- A, OLF-B or PNG) has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done.

2.7Surge protection and TVS diodes

Each LNBH26S device section is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect each section of STB output circuits where the LNBH26S and other devices are electrically connected to the antenna cable.

Figure 4. Surge protection circuit

For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST is recommended. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).

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Application information (valid for each section A/B)	LNBH26S

2.8Power-on I²C interface reset and undervoltage lockout

The I²C interface built into the LNBH26S is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor.

2.9PNG: input voltage minimum detection

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1”. Refer to the electrical characteristics table for threshold details.

2.10OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. It is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically through the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for TON time 90 ms and after that, the output is set in shutdown for a TOFF time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1”. After this time has elapsed, the involved output is resumed for a time TON. At the end of TON, if the overload is still detected, the protection circuit cycles again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to low after register reading is done. Typical TON + TOFF time is 990 ms and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, while still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is done.

After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register.

If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB section output (VOUT pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation.

If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and OLF bit is reset to “0” after a register reading operation.

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2.11OTF: thermal protection and diagnostic

The LNBH26S is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both linear regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register.

If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (VOUT pins) are disabled. To re-enable the output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation.

If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.

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