ST LNBH26L User Manual

LNBH26L

Dual LNBS supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNB and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93% @

0.5 A)

■ Selectable output current limit by external

resistor

■ Compliant with main satellite receiver output

voltage specification (8 programmable levels)

■ Accurate built-in 22 kHz tone generator suits

widely accepted standards

■ 22 kHz tone waveform integrity guaranteed

also at no load condition

■ Low-drop post regulator and high efficiency

step-up PWM with integrated power N-MOS allowing low power losses

■ Overload and overtemperature internal

protection with I²C diagnostic bits

■ LNB short-circuit dynamic protection

■ +/- 4 kV ESD tolerant on output power pins

Applications

■ STB satellite receivers

■ TV satellite receivers

■ PC card satellite receivers

Description

Intended for analog and digital DUAL satellite receivers/Sat-TV, Sat-PC cards, the LNBH26L is a monolithic voltage regulator and interface IC, assembled in QFN24 (4x4) specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dishes or to the multi-switch box. In this application field, it offers a complete solution for dual tuner satellite receivers with an extremely low component count and low power dissipation together with simple design and I²C standard interfacing.

QFN24 (4x4 mm)

Table 1. Device summary

Order code Package Packaging

LNBH26LPQR QFN24 (4x4) Tape and reel

March 2012 Doc ID 022876 Rev 1 1/28

www.st.com

Contents LNBH26L

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Application information (valid for each section A/B) . . . . . . . . . . . . . . . 4

2.1 DISEQC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4

2.3 Data encoding by external DiSEqC envelope control

through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 7

2.9 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7

2.11 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.2 START and STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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LNBH26L Contents

7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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Block diagram LNBH26L

1 Block diagram

Figure 1. Block diagram

DSQIN-B

DSQIN-A

ADDR

SDASCL

LX-A

PGND

VUP-A

OUT-A

Isense

PWM CTRL

Gate ctrl

Linear

Regulator

ISEL

I²C Digital core

DAC Drop control Tone ctrl Diagnostics Protections

Current

Limit

selection

Voltage

reference

GND

BYP

VCC

Linear

Regulator

PWM CTRL

Gate ctrl

LX-B

Isense

PGND

VUP-B

VOUT-B

AM10482v 1

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LNBH26L Application information (valid for each section A/B)

2 Application information (valid for each section A/B)

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (V / 18 V LNB output voltages plus the 22 kHz DiSEqC tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at V

- V

= 1 V typ.). The IC is also provided with an undervoltage lockout circuit that

OUT

disables the whole circuit when the supplied V typically). The step-up converter soft-start function reduces the inrush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V.

2.1 DISEQC data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC standards, and can be activated in 3 different ways:

1) by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL

compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1.

2) by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this

case the I²C tone control bits must be set: EXTM=0 and TEN=1.

) that let the integrated LDO post-regulator (generating the 13 V

drops below a fixed threshold (4.7 V

3) through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this

case the DSQIN TTL pin must be pulled high and the EXTM bit set to “0”.

2.2 Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the V LNBH26L integrated tone generator.

The output tone waveforms are internally controlled by the LNBH26L tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26L activates the 22 kHz tone on the V

output with about 1 µs delay from TTL

OUT

signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired. Refer to

Figure 2

Figure 2. Tone enable and disable timing (using external waveform)

DSQIN

Tone

~ 1 µs

Output

~ 60 µs

OUT

pin, by using the

AM10426v1

Doc ID 022876 Rev 1 5/28

Application information (valid for each section A/B) LNBH26L

2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this way, the internal 22 kHz signal is superimposed to the V generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high the internal control circuit activates the 22 kHz tone output.

DC voltage to

OUT

The 22 kHz tone on the V

pin is activated with about 6 µs delay from the DSQIN TTL

OUT

signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to

Figure 3. Tone enable and disable timing (using envelope signal)

DSQIN

Tone Output

~ 6 µs

2.4 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

16578

MAX

.)typ(I

RSEL

206.1

Figure 3

15 µs ~ 60 µs

AM10427v1

with ISET=0,

where RSEL is the resistor connected between ISEL and GND expressed in kΩ and I (typ.) is the typical current limit threshold expressed in mA. I each channel. However, it is recommended to not exceed for a long period a total amount of current of 1 A from both sections (I

OUT_A

+ I

OUT_B

overtemperature protection from triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions.

2.5 Output voltage selection

Each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register (see

Section 7.3: Data registers

for exact programmable values). Register writing is accessible via the

I²C bus.

6/28 Doc ID 022876 Rev 1

and

Table 13: Output voltage selection table (Data1

can be set up to 750 mA for

MAX

< 1 A) in order to avoid the

MAX

LNBH26L Application information (valid for each section A/B)

2.6 Diagnostic and protection functions

The LNBH26L has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to LOW. One diagnostic bit is dedicated to the overtemperature (OTF), and two bits (one per section) are dedicated to overcurrent (OLF-A, OLF-B). One bit is dedicated to the input voltage power not good function (PNG). Once the OTF bit (or OLFA, OLF-B or PNG) has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done.

2.7 Surge protection and TVS diodes

Each LNBH26L device section is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect each section of STB output circuits where the LNBH26L and other devices are electrically connected to the antenna cable.

Figure 4. Surge protection circuit

For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST is recommended. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details).

2.8 Power-on I²C interface reset and undervoltage lockout

The I²C interface built into the LNBH26L is automatically reset at power-on. As long as the V

stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does

not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the V interface becomes operative and the DATA registers can be configured by the main microprocessor.

rises above 4.8 V typ., the I²C

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Application information (valid for each section A/B) LNBH26L

2.9 PNG: input voltage minimum detection

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1”. Refer to the electrical characteristics table for threshold details.

2.10 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. It is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically through the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T output is set in shutdown for a T

time of typically 900 ms. Simultaneously, the

OFF

corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1”. After this time has elapsed, the involved output is resumed for a time T overload is still detected, the protection circuit cycles again through T end of a full T

in which no overload is detected, normal operation is resumed and the OLF

diagnostic bit is reset to low after register reading is done. Typical T and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, while still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is done. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register. If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB section output (V

pin) is disabled. To re-enable the output stage, the VSEL bits must be

OUT

set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation. If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and OLF bit is reset to “0” after a register reading operation.

time 90 ms and after that, the

. At the end of TON, if the

and TON. At the

OFF

+ T

OFF

time is 990 ms

2.11 OTF: thermal protection and diagnostic

The LNBH26L is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both linear regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register.

If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (V To re-enable the output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation.

If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.

8/28 Doc ID 022876 Rev 1

pins) are disabled.

OUT

LNBH26L Pin configuration

3 Pin configuration

Figure 5. Pin connections (top view)

192021222324

GNDDSQIN-B DSQIN-A

GND

LX- A

PGND

LX- B

ADDR GND

SCL

7 8 9 121110

SDA

ISEL

VUP-A

VOUT-A

VOUT-B

GND

GNDVUP-B

GND

VCC

BYP

GND

AM10483v1

Table 2. Pin description

Pin n° Symbol Name Pin function

3 LX-A N-Mos drain Channel A, integrated N-channel Power MOSFET drain.

4 P-GND Power ground

5 LX-B N-Mos drain Channel B, integrated N-channel Power MOSFET drain.

6 ADDR Address setting

7 SCL Serial clock Clock from I²C bus.

8 SDA Serial data Bi-directional data from/to I²C bus.

Current selection for

9 ISEL

both channel A and

1, 2, 12, 13,

15, 18, 19, 23

GND Analog ground Analog circuits ground. To be connected directly to the Epad.

DC-DC converter power ground. To be connected directly to the Epad.

Two I²C bus addresses available by setting the Address pin level voltage. See the Address pin characteristics table.

The resistor “RSEL” connected between ISEL and GND defines the linear regulator current limit threshold. Refer to “output current limit selection”

Section 2

. The RSEL resistor defines the

same current limit both for channels A and B.

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