ST LNBH25 User Manual

LNB supply and control IC with step-up and I²C interface

Features

■ Complete interface between LNB and I²C bus

■ Built-in DC-DC converter for single 12 V supply

operation and high efficiency (typ. 93 % @

0.5 A)

■ Selectable output current limit by external

resistor

■ Compliant with main satellite receivers output

voltage specification (15 programmable levels)

■ Accurate built-in 22 kHz tone generator suits

widely accepted standards

■ 22 kHz tone waveform integrity guaranteed

also at no load condition

■ Low-drop post regulator and high efficiency

step-up PWM with integrated power N-MOS allowing low power losses

■ LPM function (low power mode) to reduce

dissipation

■ Overload and overtemperature internal

protections with I²C diagnostic bits

■ LNB short-circuit dynamic protection

■ +/- 4 kV ESD tolerant on output power pins

Applications

■ STB satellite receivers

■ TV satellite receivers

■ PC card satellite receivers

LNBH25

QFN24 (4 x 4 mm)

Description

Intended for analog and digital satellite receivers/Sat-TV and Sat-PC cards, the LNBH25 is a monolithic voltage regulator and interface IC, assembled in QFN24 4x4 specifically designed to provide the 13/18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and I²C standard interfacing.

Table 1. Device summary

Order code Package Packaging

LNBH25PQR QFN24 (4 x 4) Tape and reel

February 2012 Doc ID 022433 Rev 4 1/34

www.st.com

Contents LNBH25

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4

2.3 Data encoding by external DiSEqC envelope control

through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.4 LPM (low power mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 DiSEqC 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.6 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.9 Surge protections and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.10 FLT: fault flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.11 VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.12 TMON: 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.13 TDET: 22 kHz tone detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.14 IMON: minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.15 PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 8

2.16 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 8

2.17 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.18 ISW: inductor switching current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.19 COMP: boost capacitor ESR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.20 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 9

2.21 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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LNBH25 Contents

6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.4 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Doc ID 022433 Rev 4 3/34

Block diagram LNBH25

1 Block diagram

Figure 1. Block diagram

ADDR

SDASCL

DSQIN

DETIN

DSQOUT

FLT

BPSW

Tone

detector

Voltage

reference

I2C Digital core

PWM CTRL

Isense

DAC Drop control Tone ctrl Diagnostics Protections

Current

Limit

selection

VCCGND BYP

ISEL

Linear

Regulator

Gate ctrl

PGND

VUP

VOUT

AM10400v1

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LNBH25 Application information

2 Application information

This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (V /18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at V

up-VOUT

tone output is disabled by setting the LPM bit to “1” (see IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied V function reduces the inrush current during start-up. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. switch from 0 to 18 V.

= 1 V typ.). The LDO power dissipation can be further reduced when the 22 kHz

drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start

2.1 DiSEqC data encoding (DSQIN pin)

The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards, and can be activated in 3 different ways:

1. by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL

compatible). In this case the I²C Tone control bits must be set: EXTM = TEN = 1.

2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this

case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1.

3. through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this

case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.

) that let the integrated LDO post-regulator (generating the 13 V

2.4: LPM (low power mode)

). The

Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC data transmission, the LPM bit must be set to “0” (see

2.4: LPM (low power mode)

2.2 Data encoding by external 22 kHz tone TTL signal

In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”.

The DSQIN is a logic input pin which activates the 22 kHz tone to the V LNBH25 integrated tone generator.

The output tone waveforms are internally controlled by the LNBH25 tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH25 activates the 22 kHz tone on the V activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired (refer to

Figure 2

output with about 1 µs delay from TTL signal

OUT

pin, by using the

Doc ID 022433 Rev 4 5/34

Application information LNBH25

Figure 2. Tone enable and disable timing (using external waveform)

DSQIN

Tone

~ 1 µs

Output

~ 60 µs

AM10426v1

2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin

If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C Tone control bits must be set: EXTM = 0 and TEN = 1. In this way, the internal 22 kHz signal is superimposed to the V generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH, the internal control circuit activates the 22 kHz tone output.

The 22 kHz tone on the V

pin is activated with about 6 µs delay from the DSQIN TTL

OUT

signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to

Figure 3

Figure 3. Tone enable and disable timing (using envelope signal)

DSQIN

Tone

~ 6 µs

Output

15 µs ~ 60 µs

DC voltage to

OUT

2.4 LPM (low power mode)

In order to reduce total power loss, the LNBH25 is provided with the LPM I²C bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested (no 22 kHz tone output is present); at this condition the drop voltage across the integrated LDO regulator (V

UP-VOUT

) is reduced to 0.6 V typ. and, consequently, the power loss inside the LNBH25 linear regulator is reduced too. For example: at 500 mA load, LPM=1 allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage across the LDO is kept to 1 V typ. Keep LPM=0 at all times in case the LPM function is not used.

2.5 DiSEqC 2.0 implementation

The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing. The input pin (DETIN) must be AC coupled to the DiSEqC BUS, and extracted PWK data is available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus hardware

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AM10427v1

LNBH25 Application information

requirements an output RL filter is needed. In order to avoid 22 kHz waveform distortion during tone transmission, LNBH25 is provided with the BPSW pin to be connected to an external transistor, which allows to bypass the output RL filter in DiSEqC 2.x applications while in transmission mode. Before starting tone transmission by means of the DSQIN pin, make sure that the TEN bit is preventively set to “1” and after ending tone transmission, make sure that the TEN bit is set to “0”.

2.6 Output current limit selection

The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation:

Equation 1

13915

MAX

with ISET=0

Equation 2

.)typ(I

RSEL

111.1

6808

MAX

.)typ(I

RSEL

068.1

with ISET=1

(Refer also to the ISET bit description in

Ta bl e 9

where RSEL is the resistor connected between ISEL and GND expressed in kΩ and I

(typ.) is the typical current limit threshold expressed in mA. I

MAX

2.7 Output voltage selection

The linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal DATA 1 register (see

registers

and

Ta bl e 1 4

for exact programmable values). Register writing is accessible via the

I²C bus.

2.8 Diagnostic and protection functions

LNBH25 has 8 diagnostic internal functions provided via the I²C bus, by reading 8 bits on two STATUS registers (in read mode). All the diagnostic bits are, in normal operation (that is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum load current (IMON), to external voltage source presence on the V input voltage Power Not Good function (PNG) and to the 22 kHz tone presence on the DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until relevant cause is removed and a new register reading operation is done.

can be set up to 1 A.

MAX

pin (PDO), to the

OUT

7.3: Data

Doc ID 022433 Rev 4 7/34

Application information LNBH25

2.9 Surge protections and TVS diodes

The LNBH25 device is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect the STB output circuits where the LNBH25 and other devices are electrically connected to the antenna cable.

Figure 4. Surge protection circuit

For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST. The selection of LNBTVS diodes should be made based on the maximum peak power dissipation that the diode is capable of supporting (see Ppp (W) parameter in the LNBTVS datasheet for further details).

2.10 FLT: fault flag

In order to get an immediate feedback on diagnostic status, LNBH25 is equipped with a dedicated fault flag pin (FLT). In the case of overload (OLF bit=1) or overheating (OTF bit=1) or if Power No Good (PNG bit=1) condition is detected, the FLT pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. Be aware that diagnostic bits OLF, OTF and PNG, once activated, are kept latched to “1” until the cause origin is removed and a new register reading operation is performed by the microprocessor. The FLT pin must be connected to a positive voltage (5 V max.) by means of a pull-up resistor.

2.11 VMON: output voltage diagnostic

When device output voltage is activated (V long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to “1”. See

Ta b le 1 7

for more details.

pin), its value is internally monitored and, as

OUT

2.12 TMON: 22 kHz tone diagnostic

The 22 kHz tone can be internally detected and monitored if the DETIN pin is connected to the LNB output bus (see typical application circuit in capacitor. The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz tone amplitude and/or the tone frequency is out of the guaranteed limits (see set to “1”.

Figure 7

) through a decoupling

Ta b le 1 9

), the TMON I²C bit is

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LNBH25 Application information

2.13 TDET: 22 kHz tone detection

When a 22 kHz tone presence is detected on the DETIN pin, the TDET I²C bit is set to “1”.

2.14 IMON: minimum output current diagnostic

In order to detect the output load absence (no LNB connected on the bus or cable not connected to the IRD) the LNBH25 is provided with a minimum output current flag by the IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than 12 mA (typ.). It is recommended to use IMON function only with the 22 kHz tone transmission deactivated, otherwise the IMON bit could be set to “0” even if the output current is below the minimum current threshold. To activate IMON diagnostic function, set to “1” the EN_IMON I²C bit in the DATA 4 register. Be aware that as soon as the IMON function is activated by means of EN_IMON=1, the V independently on the VSEL bit setting. This operation is applied in order to be sure that the LNBH25 output has the higher voltage present in the LNB bus. Do not use this function in an application environment where 21 V voltage level is not supported by other peripherals connected to the LNB bus.

is immediately increased to 21 V (typ.)

OUT

2.15 PDO: overcurrent detection on output pull-down stage

When an overcurrent occurs on the pull-down output stage due to an external voltage source greater than LNBH25 nominal V ms typ.), the PDO I²C bit is set to “1”. This may happen due to an external voltage source present on the LNB output (V

For current threshold and deglitch time details, see

OUT

pin).

and for a time longer than I

OUT

Ta bl e 1 3

SINK_TIME-OUT

2.16 Power-on I²C interface reset and undervoltage lockout

The I²C interface built into LNBH25 is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the V becomes operative and the DATA registers can be configured by the main microprocessor.

rises above 4.8 V typ. the I²C interface

2.17 PNG: input voltage minimum detection

When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to

Ta bl e 1 3

for threshold details.

2.18 ISW: inductor switching current limit

(10

In order to allow low saturation current inductors to be used, the maximum DC-DC inductor switching current limit threshold can be set by means of one I²C bit (ISW). Two values are available: 2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).

Doc ID 022433 Rev 4 9/34

Application information LNBH25

2.19 COMP: boost capacitor ESR

DC-DC converter compensation loop can be optimized in order to work well with high or low ESR capacitors (on the V

pin). For this purpose, one I²C bit in the DATA 4 register

(COMP) can be set to “1” or “0”. It is recommended to reset this bit to “0” unless using high ESR capacitors.

2.20 OLF: overcurrent and short-circuit protection and diagnostic

In order to reduce the total power dissipation during an overload or a short-circuit condition, the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C DATA 3 register. When the PCL (pulsed current limiting) bit is set Io LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T programmed in the DATA 3 register) and after that, the output is set in shutdown for T time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is set to “1” and the FLT pin is set to low level. After this time has elapsed, the output is resumed for a time T

. At the end of TON, if the overload is still detected, the protection

circuit cycles again through T detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical T TIMER=1) and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on startup in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA 4 register. If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (V enable output stage, the VSEL bits must be set again by the microprocessor, and the OLF bit is reset to “0” after a register reading operation. If OLR=0, output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation.

time (90 ms or 180 ms typ., according to the TIMER bit

and TON. At the end of a full TON in which no overload is

OFF

time is 990 ms (if TIMER=0) or 1080 ms (if

OFF

pin) is disabled. To re-

OUT

OFF

2.21 OTF: thermal protection and diagnostic

The LNBH25 is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1” and the FLT pin is set to low level. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA 4 register. If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (V enable output stage, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation. If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation.

10/34 Doc ID 022433 Rev 4

pin) is disabled. To re-

OUT

LNBH25 Pin configuration

3 Pin configuration

Figure 5. Pin connections (top view)

192021222324

DSQIN/

DSQOUTNC

DSQIN

EXTM

VUP

VOUT

DETIN

FLT

LX- A

PGND

ADDR NC

SDA ISEL NCNC

SCL

SDA ISEL NCNC

SCL

7 8 9 121110

Table 2. Pin description

Pin n° Symbol Name Pin function

Open drain output for IC fault conditions. It is set low in case of

2FLT FLT

3 LX N-MOS drain Integrated N-channel Power MOSFET drain.

overload (OLF bit) or overheating status (OTF bit) or power not good (PNG) is detected. To be connected to pull-up resistor (5 V max.).

BPSW

VCC

VBYP

GND

AM09909v 1

4 P-GND Power ground

6 ADDR Address setting

DC-DC converter power ground. To be connected directly to the Epad.

Two I²C bus addresses available by setting the address pin level voltage. See

Ta bl e 16

7 SCL Serial clock Clock from I²C BUS.

8 SDA Serial data Bi-directional data from/to I²C BUS.

The resistor “RSEL” connected between ISEL and GND defines the

9 ISEL Current selection

linear regulator current limit threshold. Refer to Application Information section. Also see the ISET bit description in

Section 2.6

in the

Tab l e 9.

15 GND Analog ground Analog circuits ground. To be connected directly to the Epad.

Needed for internal pre-regulator filtering. The BYP pin is intended

16 BYP Bypass capacitor

only to connect an external ceramic capacitor. Any connection of this pin to external current or voltage sources may cause permanent damage to the device.

17 V

Supply input 8 to 16 V IC DC-DC power supply.

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