ST LM124W, LM224W, LM324W Operation Manual

LM224W

LM124W

LM224W - LM324W

LOW POWER QUAD OPERATIONAL AMPLIFIERS

WIDE GAIN BANDWIDTH : 1.3MHz

LARGE VOLTAGE GAIN : 100dB

VERY LOW SUPPLY CURRENT/AMPLI : 375 A

LOW INPUT BIAS CURRENT : 20nA

LOW INPUT OFFSET VOLTAGE : 3mV max.

LOW INPUT OFFSET CURRENT : 2nA

WIDE POWER SUPPLY RANGE : SINGLE SUPPLY : +3V TO +30V DUAL SUPPLIES : ±1.5V TO ±15V

INPUT COMMON-MODE VOLTAGE RANGE INCLUDES GROUND

ESD INTERNAL PROTECTION : 2kV

DESCRIPTION

These circuits consist of four independent, high gain, internally frequency compensated operational amplifiers. They operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage.

All the pins are protected against electrostatic discharges up to 2000V (as a consequence, the input voltages must not exceed the magnitude of VCC+ or VCC-.)

PIN CONNECTIONS (top view)

N

DIP14

((Plastic Package)

D

SO14

(Plastic Micropackage)

P

TSSOP14

(Thin Shrink Small Outline Package)

ORDER CODE

Part

Temperature

 

Package

 

 

 

 

 

Number

Range

N

D

 

P

 

 

 

 

 

 

 

 

 

LM124W

-55°C, +125°C

 

 

 

 

 

 

 

LM224W

-40°C, +105°C

 

 

 

 

 

 

 

LM324W

0°C, +70°C

 

 

 

 

 

 

 

Example : LM224WN

N = Dual in Line Package (DIP)

D = Small Outline Package (SO) - also available in Tape & Reel (DT)

P = Thin Shrink Small Outline Package (TSSOP) - only available in Tape &Reel (PT)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

September 2003

1/13

ST LM124W, LM224W, LM324W Operation Manual

LM124W - LM224W - LM324W

SCHEMATIC DIAGRAM (1/4 LM124W)

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

 

LM124W

LM224W

 

LM324W

Unit

 

 

 

 

 

 

 

 

VCC

Supply voltage

 

 

±16 or 32

 

V

Vi

Input Voltage

 

-0.3 to Vcc + 0.3

 

V

Vid

Differential Input Voltage 1)

 

-0.3 to Vcc

-0.3 to Vcc

 

-0.3 to Vcc

V

 

+ 0.3

+ 0.3

 

+ 0.3

 

 

 

 

 

 

 

 

 

 

 

 

 

Ptot

Power Dissipation

N Suffix

500

500

 

500

mW

 

D Suffix

 

400

 

400

mW

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Short-circuit Duration 2)

 

 

Infinite

 

 

Iin

Input Current 3)

 

50

50

 

50

mA

Toper

Opearting Free-air Temperature Range

-55 to +125

-40 to +105

 

0 to +70

°C

Tstg

Storage Temperature Range

 

-65 to +150

-65 to +150

-65 to +150

°C

1.Either or both input voltages must not exceed the magnitude of VCC+ or VCC-.

2.Short-circuits from the output to VCC can cause excessive heating if VCC > 15V. The maximum output current is approximately 40mA independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short-circuit on all amplifiers.

3.This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward biased and thereby acting as input diodes clamps. In addition to this diode action, there is also NPN parasitic action on

the IC chip. this transistor action can cause the output voltages of the Op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time duration than an input is driven negative.

This is not destructive and normal output will set up again for input voltage higher than -0.3V.

2/13

LM124W - LM224W - LM324W

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

 

V

+ = +5V, V

-= Ground, V

o

= 1.4V, T

 

= +25°C (unless otherwise specified)

 

 

 

 

CC

CC

 

 

 

amb

 

 

 

 

 

 

Symbol

 

 

 

 

 

Parameter

 

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

 

Vio

Input Offset Voltage - note 1)

 

 

 

 

 

 

 

mV

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

2

3

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

 

 

5

 

 

 

Input Offset Current

 

 

 

 

 

 

 

 

 

 

nA

 

Iio

 

Tamb = +25°C

 

 

 

 

 

 

 

 

2

20

 

 

 

 

Tmin ≤ Tamb

Tmax

 

 

 

 

 

 

40

 

 

Iib

Input Bias Current - note 2)

 

 

 

 

 

 

 

nA

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

20

100

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

 

 

200

 

 

 

Large Signal Voltage Gain

 

 

 

 

 

 

 

V/mV

 

 

 

VCC+ = +15V, RL = 2kΩ,

Vo = 1.4V to 11.4V

 

 

 

 

Avd

 

50

100

 

 

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

25

 

 

 

 

 

Supply Voltage Rejection Ratio (Rs

10kΩ

)

 

 

 

dB

 

SVR

 

V

+ = 5V to 30V

 

 

 

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

65

110

 

 

 

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

65

 

 

 

 

 

Supply Current, all Amp, no load

 

 

 

 

 

 

mA

 

 

 

Tamb = +25°C

 

 

 

 

 

 

VCC = +5V

 

 

 

 

 

 

 

 

 

 

 

 

 

0.7

1.2

 

 

ICC

 

Tmin ≤ Tamb

 

 

 

 

 

 

VCC = +30V

 

1.5

3

 

 

 

 

Tmax

 

 

 

VCC = +5V

 

0.8

1.2

 

 

 

 

 

 

 

 

 

 

 

 

VCC = +30V

 

1.5

3

 

 

 

Input Common Mode Voltage Range

 

 

 

 

 

 

V

 

 

 

VCC = +30V - note 3)

 

 

 

 

 

 

 

 

Vicm

 

 

 

 

 

0

 

VCC

 

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-1.5

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

0

 

VCC -2

 

 

 

 

 

 

 

 

 

 

 

 

 

Common Mode Rejection Ratio (Rs

10kΩ

)

 

 

 

dB

 

CMR

 

Tamb = +25°C

 

 

 

 

 

 

 

70

80

 

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

60

 

 

 

 

Isource

Output Current Source (Vid = +1V)

 

 

 

 

 

 

mA

 

 

VCC = +15V, Vo = +2V

 

 

 

 

20

40

70

 

 

 

 

 

 

 

 

 

 

 

Output Sink Current (Vid = -1V)

 

 

 

 

 

 

 

 

 

Isink

 

VCC = +15V, Vo = +2V

 

 

 

 

10

20

 

mA

 

 

 

VCC = +15V, Vo = +0.2V

 

 

 

 

12

50

 

µ A

 

 

High Level Output Voltage

 

 

 

 

 

 

 

V

 

 

 

VCC = +30V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL = 2kΩ

 

 

 

 

 

 

 

Tamb = +25°C

 

 

 

 

 

 

26

27

 

 

 

 

 

Tmin ≤ Tamb

Tmax

 

 

 

RL = 10kΩ

26

 

 

 

 

VOH

 

Tamb = +25°C

 

 

 

 

 

 

27

28

 

 

 

 

 

Tmin ≤ Tamb

Tmax

 

 

 

 

27

 

 

 

 

 

 

VCC = +5V, RL = 2kΩ

 

 

 

 

3.5

 

 

 

 

 

 

Tamb = +25°C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

Tmin ≤ Tamb ≤ Tmax

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low Level Output Voltage (RL = 10kΩ

)

 

 

 

 

 

mV

 

VOL

 

Tamb = +25°C

 

 

 

 

 

 

 

 

5

20

 

 

 

 

Tmin ≤ Tamb

Tmax

 

 

 

 

 

 

20

 

3/13

LM124W - LM224W - LM324W

Symbol

Parameter

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

SR

Slew Rate

 

 

 

V/µ s

VCC = 15V, Vi = 0.5 to 3V, RL = 2kΩ , CL = 100pF, unity Gain

 

0.4

 

 

 

 

 

 

GBP

Gain Bandwidth Product

 

 

 

MHz

VCC = 30V, f =100kHz,Vin = 10mV, RL = 2kΩ , CL = 100pF

 

1.3

 

 

 

 

 

 

THD

Total Harmonic Distortion

 

 

 

%

f = 1kHz, Av = 20dB, RL = 2kΩ, Vo = 2Vpp, CL = 100pF, VCC = 30V

 

0.015

 

 

 

 

 

 

en

Equivalent Input Noise Voltage

 

 

 

nV

f = 1kHz, Rs = 100Ω, VCC = 30V

 

40

 

-----------

 

 

 

Hz

 

 

 

 

 

 

DVio

Input Offset Voltage Drift

 

7

30

µ V/°C

DIIio

Input Offset Current Drift

 

10

200

pA/°C

Vo1/Vo2

Channel Separation - note 4)

 

120

 

dB

1kHz ≤ f ≤ 20kHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

1.The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so no loading change exists on the input lines.

2.Vo = 1.4V, Rs = 0Ω , 5V < VCC+ < 30V, 0 < Vic < VCC+ - 1.5V

3.The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VCC+ - 1.5V, but either or both inputs can go to +32V without damage.

4.Due to the proximity of external components insure that coupling is not originating via stray capacitance between these external parts. This typically can be detected as this type of capacitance increases at higher frequences.

4/13

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