ST L9347 User Manual

L9347

Intelligent quad (2x5A/2x2.5A) low-side switch

Features

■Quad low-side switch

■2 x 5A designed as conventional switch

■2 x 2.5A designed as switched currentregulator

■Low ON resistance 2 x 0.2Ω, 2 x 0.35Ω (typ.)

■Power SO-36 package with integrated cooling area

■Integrated free wheeling and clamping Z diodes

■Output slope control

■Short circuit protection

■Selective overtemperature shutdown

■Open load detection

■Ground and supply loss detection

■External clock control

■Recirculation control

■Regulator drift detection

■Regulator error control

■Regulator resolution 5mA

■Status monitoring

■Status push-pull stages

■Electrostatic discharge (ESD) protection

PowerSO-36

Bare Die

Description

The L9347 is an integrated quad low-side power switch to drive inductive loads like valves used in ABS systems. Two of the four channels are current regulators with current range from 250mA to 2.25A and an accuracy of 10%.

All channels are protected against fail functions. They are monitored by a status output.

Table 1.	Device summary
	Part number	Package	Packing
	L9347LF	PowerSO-36	Tray
	L9347LF-TR	PowerSO-36	Tape and reel
	L9347DIE1	Bare die	Bare die

May 2007

Rev 2

1/29

www.st.com

Contents	L9347

Contents

1	Block diagram and pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
3	Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
	3.1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.2	Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.3	Output stages (not regulated) Channel 1 and 2 . . . . . . . . . . . . . . . . . . . .	13
	3.4	Current regulator stages Channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . .	13
	3.5	Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.6	Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.7	Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.8	Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.9	Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
4	Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		20
	4.1	Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.2	Regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
5	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		28

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L9347	List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Detected errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 9. Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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List of figures	L9347

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14 Figure 5. Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. Overload switch OFF delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Under current condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Open load condition in the case of pulsed input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Pulsed open load conditions (regulated and non-regulated channels) . . . . . . . . . . . . . . . . 23 Figure 12. Normal condition, inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 17. Test mode 4 (VEN low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 27

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L9347	Block diagram and pin connections

1 Block diagram and pin connections

Figure 1. Block diagram

VS	VCC	VDD
	Internal Supply
EN
Overtemperature		Overtemperature
Channel 4		Channel 1
CLK
		Open Load
IN1		Overload
	LOGIC		Q1
ST1			IPD
		GND-det.
		Open Load
			D4
IN4	LOGIC	Overload	Q4
	&
	DA
ST4		GND-det.	IPD
Overtemperature		Overtemperature
Channel 3		Channel 2
		Open Load
IN2		Overload
	LOGIC		Q2
ST2			IPD
		GND-det.
		Open Load
			D3
IN3	LOGIC	Overload
			Q3
	&
	DA
ST3			IPD
		GND-det.
drift-det.
TEST
99AT0059			GND
			5/29

Block diagram and pin connections

L9347

Figure 2.

Pin connections

GND

1

36

CLK

PGND3

2

35

ST3

PGND3

3

34

IN1

Q3

4

33

IN3

Q3

5

32

ST1

D3

6

31

PGND1

D3

7

30

PGND1

Q1

8

29

VS

Q1

9

28

PGND2

Q2

10

27

PGND2

Q2

11

26

TEST

D4

12

25

EN

D4

13

24

ST2

Q4

14

23

IN4

Q4

15

22

IN2

PGND4

16

21

ST4

PGND4

17

20

VDD

99AT0060

N.C.

18

19

VCC

Table 2.

Pin description

N°

Pin

Function

1

GND

Logic Ground

2, 3

PGND 3

Power Ground Channel 3

4, 5

Q 3

Power Output Channel 3

6, 7

D 3

Free-Wheeling Diode Channel 3

8, 9

Q 1

Power Output Channel 1

10, 11

Q 2

Power Output Channel 2

12, 13

D 4

Free-Wheeling Diode Channel 4

14, 15

Q 4

Power Output Channel 4

16, 17

PGND 4

Power Ground Channel 4

18

NC

Not Connected

19

VCC

5V Supply

20

VDD

5V Supply

21

ST 4

Status Output Channel 4

22

IN 2

Control Input Channel 2

23

IN 4

Control Input Channel 4

24

ST 2

Status Output Channel 2

25

EN

Enable Input for all four Channels

26

TEST

Enable Input for Drift detection

27, 28

PGND 2

Power Ground Channel 2

29

VS

Supply Voltage

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L9347				Block diagram and pin connections
	Table 2.	Pin description (continued)
	N°		Pin	Function
	30, 31		PGND 1	Power Ground Channel 1
	32		ST 1	Status Output Channel 1
	33		IN 3	Control Input Channel 3
	34		IN 1	Control Input Channel 1
	35		ST 3	Status Output Channel 3
	36		CLK	Clock Input

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Electrical specifications							L9347
2	Electrical specifications
Table 3.	Electrical characteristcs:
	(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol	Parameter	Test condition		Min.	Typ.	Max.	Unit
Power supply
ISON	Supply current	VS ≤ 18V				5	mA
		(outputs ON)
ISOFF	Quiescent current	VS ≤ 18V				5	mA
		(outputs OFF)
Icc	Supply current VCC (analog supply)	VCC =5V				5	mA
Idd	Supply current VDD (digital supply)	VDD =5V fCLK=0Hz				5	uA
Idd	Supply current VDD (digital supply)	VDD =5V fCLK=250kHz				5	mA
General diagnostic functions
VQU	Open load voltage	VS ≥ 6.5V		0.3	0.33	0.36	x VQ
		(outputs OFF)
VthGND	Signal-GND-loss threshold	VCC= 5V		0.1		1	V
VthPGL	Power-GND-loss threshold	VCC= 5V		1.5	2.5	3.5	V
fCLK,min	Clock frequency error			10		100	kHz
DCCLKe_low	Clock duty cycle error detection low	fCLK= 250 kHz			33,3	45	%
DCCLKe_high	Clock duty cycle error detection high	fCLK= 250 kHz		55	66,6		%
VSloss	Supply detection	VCC = VDD = 5V		2		4.5	V
Additional diagnostic functions channel 1 and channel 2 (non regulated channels)
IQU1,2	Open-load current channel 1, 2	VS ≥ 6.5V		50		140	mA
IQO1,2	Over-load current channel 1, 2	VS ≥ 6.5V		5	7.5	9	A
Additional diagnostic functions channel 3 and channel 4 (regulated channels)
DCOUT	Output duty cycle range	filtered with 10ms		10		90	%
IQO3,4	Overload current	VS ≥ 6.5V		2.5	5	8	A
	channel 3,4
Vrerr	Recirculation error shutdown	Iout > 50mA		45	50	60	V
	threshold (open D3/D4)
PWMdOUT	Output PWM ratio during drift	VIN3 = VIN4 = PWMIN		-14.3		+14.3	%
	comparison	VTEST = H
Digital inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
VIL	Input low voltage			-0.3		1	V
VIH	Input high voltage			2		6	V
VIHy	Input voltage hysteresis (1)			20		500	mV

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L9347

Electrical specifications

Table 3.

Electrical characteristcs: (continued)

(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

II

Input pull down current

VIN = 5V, VS ≥ 6.5V

8

20

40

μA

Digital outputs (ST1 to ST4)

V

STL

Status output voltage in low state (2)

I

≤ 40μA

0

0.4

V

ST

VSTH

Status output voltage in high state (2)

IST ≥ -40μA

2.5

3.45

V

IST ≥ -120μA

2

3.45

V

RDIAGL

ROUT + RDSON in low state

0.3

0.64

1.5

kΩ

RDIAGH

ROUT + RDSON in high state

1.5

3.2

7.0

kΩ

Power outputs (Q1 to Q4)

Static drain-source ON-resistance

IQ = 1A; VS ≥ 9.5V

RDSON1,2

Q1 and Q2

Tj = 25°C

W

(non-reg. channels)

Tj = 125°C(3)

0.2

0.5

W

Tj = 150°C(4)

0.5

W

Static drain-source ON-resistance

IQ = 1A; VS ≥ 9.5V

RDSON3,4

Q3 and Q4

Tj = 25°C

Ω

(reg. channels)

0.35

0.75

T

j

= 125°C (3)

Ω

T = 150°C (4)

0.75

Ω

j

V

F_250mA

Forward voltage of free wheeling path

I

= -250mA

0.5

1.5

V

D3, D4 @250mA

D3/4

V

F_2.25A

Forward voltage of free wheeling path

I

= -2.25A

2.0

4.5

V

D3, D4 @2.25A

D3/4

Rsens

Sense resistor = (VF_2.25A-

1

Ω

VF_250mA)/2A

VZ

Z-diode clamping voltage

IQ ≥ 100mA

45

60

V

IPD

Output pull down current

VEN = H, VIN = L

10

150

μA

IQlk

Output leakage current

VEN = L; VQ = 20V

5

μA

Timing

tON

Output ON delay time

IQ = 1A

0

5

20

μs

tOFF

Output OFF delay time channel

IQ = 1A

0

10

30

μs

tOFFREG

Output OFF delay time regulator

(5)

528

μs

tr

Output rise time

IQ = 1A

0.5

1.5

8

μs

tf

Output fall time

IQ = 1A

0.5

1.5

8

μs

tsf

Short error detection filter time

fCLK = 250kHz DC = 50%(5)

4

8

μs

tlf

Long error detection filter time

fCLK = 250kHz DC = 50%(5)

16

32

μs

tSCP

Short circuit switch-OFF delay time

(5)

4

30

μs

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