ST L9347 User Manual
Intelligent quad (2x5A/2x2.5A) low-side switch
Features
■ Quad low-side switch
■ 2 x 5A designed as conventional switch
■ 2 x 2.5A designed as switched current-
regulator
■ Low ON resistance 2 x 0.2Ω, 2 x 0.35Ω (typ.)
■ Power SO-36 package with integrated
cooling area
■ Integrated free wheeling and clamping Z
diodes
■ Output slope control
■ Short circuit protection
■ Selective overtemperature shutdown
■ Open load detection
■ Ground and supply loss detection
■ External clock control
■ Recirculation control
■ Regulator drift detection
■ Regulator error control
■ Regulator resolution 5mA
■ Status monitoring
■ Status push-pull stages
■ Electrostatic discharge (ESD) protection
Table 1. Device summary
L9347
PowerSO-36
Description
The L9347 is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are
current regulators with current range from 250mA
to 2.25A and an accuracy of 10%.
All channels are protected against fail functions.
They are monitored by a status output.
Bare Die
Part number Package Packing
L9347LF PowerSO-36 Tray
L9347LF-TR PowerSO-36 Tape and reel
L9347DIE1 Bare die Bare die
May 2007 Rev 2 1/29
www.st.com
1
Contents L9347
Contents
1 Block diagram and pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Input circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Output stages (not regulated) Channel 1 and 2 . . . . . . . . . . . . . . . . . . . . 13
3.4 Current regulator stages Channel 3 and 4 . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Protective circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 Drift detection (regulated channels only) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Other test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Non regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Regulated channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
L9347 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Detected errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Special test mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures L9347
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Input PWM to output current range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Current accuracy according to the input and clock frequency ratio . . . . . . . . . . . . . . . . . . 14
Figure 5. Output slope, resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Overload switch OFF delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Normal condition, resistive load, pulsed input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Under current condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Open load condition in the case of pulsed input signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Pulsed open load conditions (regulated and non-regulated channels). . . . . . . . . . . . . . . . 23
Figure 12. Normal condition, inductive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Current overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Recirculation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Current regulation error (e.g. as a result of voltage reduction) . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16. Over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. Test mode 4 (VEN low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18. PowerSO-36 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 27
4/29
L9347 Block diagram and pin connections
99AT0059
1 Block diagram and pin connections
Figure 1. Block diagram
VS VCC VDD
Internal Supply
EN
CLK
IN1
ST1
IN4
ST4
IN2
Overtemperature
Channel 4
Overtemperature
Channel 3
LOGIC
LOGIC
&
DA
LOGIC
Overtemperature
Channel 1
Open Load
Overload
GND-det.
Open Load
Overload
GND-det.
Overtemperature
Channel 2
Open Load
Overload
Q1
IPD
D4
Q4
IPD
Q2
ST2
IN3
ST3
TEST
drift-det.
IPD
D3
Q3
IPD
LOGIC
&
DA
GND-det.
Open Load
Overload
GND-det.
GND
5/29
Block diagram and pin connections L9347
99AT0060
Figure 2. Pin connections
CLK
PGND3
PGND3
PGND4
PGND4
Table 2. Pin description
GND 1
Q3
Q3
D3
D3
Q1
Q1
Q2
Q2
D4
D4
Q4
Q4
N.C.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
ST3
IN1
IN3
ST1
PGND1
PGND1
VS
PGND2
PGND2
TEST
EN
ST2
IN4
IN2
ST4
VDD
VCC
N° Pin Function
1 GND Logic Ground
2, 3 PGND 3 Power Ground Channel 3
4, 5 Q 3 Power Output Channel 3
6, 7 D 3 Free-Wheeling Diode Channel 3
8, 9 Q 1 Power Output Channel 1
10, 11 Q 2 Power Output Channel 2
12, 13 D 4 Free-Wheeling Diode Channel 4
14, 15 Q 4 Power Output Channel 4
16, 17 PGND 4 Power Ground Channel 4
18 NC Not Connected
19 VCC 5V Supply
20 VDD 5V Supply
21 ST 4 Status Output Channel 4
22 IN 2 Control Input Channel 2
23 IN 4 Control Input Channel 4
24 ST 2 Status Output Channel 2
25 EN Enable Input for all four Channels
26 TEST Enable Input for Drift detection
27, 28 PGND 2 Power Ground Channel 2
29 VS Supply Voltage
6/29
L9347 Block diagram and pin connections
Table 2. Pin description (continued)
N° Pin Function
30, 31 PGND 1 Power Ground Channel 1
32 ST 1 Status Output Channel 1
33 IN 3 Control Input Channel 3
34 IN 1 Control Input Channel 1
35 ST 3 Status Output Channel 3
36 CLK Clock Input
7/29
Electrical specifications L9347
2 Electrical specifications
Table 3.
Electrical characteristcs
(Vs = 4.8 to 18V; T
= -40 to 150°C unless otherwise specified)
j
:
Symbol Parameter Test condition Min. Typ. Max. Unit
Power supply
V
≤ 18V
I
SON
I
SOFF
I
cc
I
dd
I
dd
Supply current
Quiescent current
Supply current VCC (analog supply) VCC =5V 5 mA
Supply current VDD (digital supply) VDD =5V f
Supply current VDD (digital supply) VDD =5V f
S
(outputs ON)
V
≤ 18V
S
(outputs OFF)
CLK
CLK
5mA
5mA
=0Hz 5 uA
=250kHz 5 mA
General diagnostic functions
VS ≥ 6.5V
(outputs OFF)
= 250 kHz 33,3 45 %
CLK
= 250 kHz 55 66,6 %
CLK
0.3 0.33 0.36 x V
DC
DC
V
V
f
CLK,min
VS
V
QU
thGND
thPGL
CLKe_low
CLKe_high
loss
Open load voltage
Signal-GND-loss threshold VCC= 5V 0.1 1 V
Power-GND-loss threshold VCC= 5V 1.5 2.5 3.5 V
Clock frequency error 10 100 kHz
Clock duty cycle error detection low f
Clock duty cycle error detection high f
Supply detection VCC = VDD = 5V 2 4.5 V
Additional diagnostic functions channel 1 and channel 2 (non regulated channels)
Q
I
QU1,2
I
QO1,2
Open-load current channel 1, 2 VS ≥ 6.5V 50 140 mA
Over-load current channel 1, 2 VS ≥ 6.5V 5 7.5 9 A
Additional diagnostic functions channel 3 and channel 4 (regulated channels)
DC
I
QO3,4
V
PWM
OUT
rerr
Output duty cycle range filtered with 10ms 10 90 %
Overload current
channel 3,4
Recirculation error shutdown
threshold (open D3/D4)
Output PWM ratio during drift
dOUT
comparison
VS ≥ 6.5V 2.5 5 8 A
Iout > 50mA 45 50 60 V
= V
V
V
IN3
TEST
IN4
= H
= PWM
IN
-14.3 +14.3 %
Digital inputs (IN1 to IN4, ENA, CLK, TEST). The valid PWM-Ratio for IN3/IN4 is 10% to 90%
V
IL
V
IH
V
IHy
Input low voltage -0.3 1 V
Input high voltage 2 6 V
Input voltage hysteresis
(1)
20 500 mV
8/29
L9347 Electrical specifications
Table 3.
Electrical characteristcs: (continued)
(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
I
I
Digital outputs (ST1 to ST4)
V
STL
V
STH
R
DIAGL
R
DIAGH
Power outputs (Q1 to Q4)
R
DSON1,2
R
DSON3,4
Input pull down current VIN = 5V, VS ≥ 6.5V 8 20 40 μA
Status output voltage in low state
Status output voltage in high state
R
R
OUT
OUT
+ R
+ R
in low state 0.3 0.64 1.5 kΩ
DSON
in high state 1.5 3.2 7.0 kΩ
DSON
Static drain-source ON-resistance
Q1 and Q2
(non-reg. channels)
Static drain-source ON-resistance
Q3 and Q4
(reg. channels)
(2)
IST ≤ 40μA00.4V
IST ≥ -40μA 2.5 3.45 V
(2)
≥ -120μA 2 3.45 V
I
ST
= 1A; VS ≥ 9.5V
I
Q
T
= 25°C
j
= 125°C
T
j
Tj = 150°C
= 1A; VS ≥ 9.5V
I
Q
= 25°C
T
j
= 125°C
T
j
Tj = 150°C
(3)
(4)
(3)
(4)
0.2 0.5
0.5
0.35 0.75
0.75
W
W
W
Ω
Ω
Ω
V
F_250mA
V
F_2.25A
R
sens
V
I
PD
I
Qlk
Timing
t
ON
t
OFF
t
OFFREG
t
t
t
SCP
Forward voltage of free wheeling path
D3, D4 @250mA
Forward voltage of free wheeling path
D3, D4 @2.25A
Sense resistor = (V
V
F_250mA
Z-diode clamping voltage IQ ≥ 100mA 45 60 V
Z
)/2A
F_2.25A-
= -250mA 0.5 1.5 V
I
D3/4
= -2.25A 2.0 4.5 V
I
D3/4
1 Ω
Output pull down current VEN = H, VIN = L 10 150 μA
Output leakage current VEN = L; VQ = 20V 5 μA
Output ON delay time IQ = 1A 0 5 20 μs
Output OFF delay time channel IQ = 1A 0 10 30 μs
Output OFF delay time regulator
t
r
t
f
sf
lf
Output rise time IQ = 1A
Output fall time IQ = 1A
Short error detection filter time f
Long error detection filter time f
Short circuit switch-OFF delay time
(5)
= 250kHz DC = 50%
CLK
= 250kHz DC = 50%
CLK
(5)
528 μs
0.5 1.5 8 μs
0.5 1.5 8 μs
(5)
(5)
48μs
16 32 μs
430μs
9/29
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