The electrical characteristics are valid within the defined Operating Conditions, unless otherwise specified.
The function is guaranteed by design until T
SymbolParameterTest ConditionMin.Typ.Max.Unit
switch-on-threshold.
JSDon
SUPPLY
Quiescent currentVS≤ 14V; VEN≤ 0.3V
I
Q
85 °C
T
amb
V
14V; V
≤
S
150°C
T
a
V
14V;EN = high, Output = off
≤
S
EN
≤
0.3V
<210µA
12
EN = high, Output = on
Inputs, IN1 - IN4;Programming, PRG
V
V
INhigh
R
INlow
Input voltage LOW-141V
Input voltage HIGH245V
I
Input current
IN
Input impedanceVIN< 0V; VIN>V
IN
4. Current direction depends on the programming setting (PRG=high leads into a positive current see also Blockdiagram page 1)
0V ≤ V
IN
≤ 45V
4)
S
-2550µA
1060kΩ
50µA
mA
3.5
mA
4/13
L9333
ELECTRICAL CHARACTERISTCS
(continued)
SymbolParameterTest ConditionMin.Typ.Max.Unit
Enable EN
V
ENlow
V
ENhigh
R
I
Input voltage LOW-141V
Input voltage HIGH245V
Input impedance-14V < VEN< 1.5V5k
Output voltage during clampingEFB≤ 2mJ; 10 mA < IO< 0.3A455260V
Short-circuit currentVS> 6V4007001000mA
internal output capacitiesVO> 4.5V100pF
O
Diagnostic Output DIAG
V
Output voltage LOWIDL= 0.6mA0.8V
Dlow
Ω
Ω
I
Dmax
I
DLeak
Timing Characteristics
t
d,on
t
d,off
t
t
d,DIAG
S
Note : All parameters are measured at 125°C.
Max. output currentinternal current limitation; VD=
Leakage currentVD=VS=14V;Ta<125°C0.11µA
5)
On delay timeVS=14V
Off delaytime34.5µs
Enable settling time20µs
set
ON or OFF Diagnostic delay time10µs
Output voltage slopes2.5916V/µs
out
5. See also Fig.3 TimingCharacteristics
14V
V
C
=14V;Ta<150°C5µA
D=VS
ext
= 0F; L
ext
=0H
only testing condition
10mA ≤ I
≤ 200mA
0
1515mA
23.5µs
5/13
L9333
Figure 1. Timing Characteristics
V
EN
Active
V
PR G
V
0.8 V
V
IN
OUT
V
t
Non-Inverting ModeInverting Mode
t
t
S
S
6)
0.2 V
S
t
set
t
d,off
6. Output voltage slope not controlled for enable low!
6/13
t
d,on
t
t
set
L9333
FUNCTIONAL DESCRIPTION
The L9333 is a quad low side driver for lines, lamps or inductive loads in automotive and industrial applications.
The logic input levels are 3.3V CMOS compatible. This allows the device to be driven directly by a microcon-
troller. For the noise immunity, all input thresholds have a hysteresis of typ. 100mV. Each input (IN, EN and
PRG) is protected towithstand voltages from-14Vto 45V. The device is activated with a’high’ signal on ENable.
ENable ’low’ switches the device into the sleep mode. In this mode the quiescent current is typically less than
2µA. A high signalon PRoGramming input changes the signaltransferpolarity from noninverting to the inverting
mode. This pin can be connected either to V
PRG and EN pin is low. For packaged applications it is still recommended to connect all input pins to ground
respective VS to avoid EMC influence. The forced condition leads to a mode change if the PRG pin was high
before the interruption. Independent of the PRoGramminginput, the OUTput switches off, if the signal INput pin
is not connected. This function is verified using a leakage current of 5µA (sink for PRG=high; source for
PRG=low) during circuit test.
Each output driver has a current limitation of min 0.4A and an independent thermal shut-down. The thermal
shut-down deactivates that output, whichexceeds temperature switch off level. When the junction temperature
decreases 20K below this temperature threshold the output will be activated again. This 20K is the hysteresis
of the thermal shutdown function. The Gates, of the output DMOS transistors are charged and discharged with
a current source. Therefore the output slope is limited. This reduces the electromagnetic radiation. For inductive loads an output voltage clamp of typically 52V is implemented.
The DIAGnostic is an open drain output. The logic status depends on the PRoGramming pin. If the PRG pin is
’low’ the DIAG output becomes low, if the device works correctly.At thermal shut-down of one channel or if the
ground is disconnected the DIAGnostic output becomes high. If the PRG pin is ’high’ this output is switched off
at normal function and switched on at overtemperature. For the fault condition of interrupted ground, the potential of VS and Diagnostic should be equal.
or GND. If these pins are not connected, the forced status of the
Measurement setup:
DUT mounted on a specific application board is driven in a typical application circuit (see below). Two devices
are stimulated by a generator to read and write bus signals. They will be monitored externally to ensure proper
function.
Figure 4. PCB layout
TOPSIDE
BACKSIDE
Measurementmethod:
a)The two bus lines are transferred 2m under a terminated stripline.That’s where they were exposed to the
RF-field. Stripline setup and measurement method is described in DIN 40839-4 or ISO 11452-5.
b)DUT mounted on the same application board is exposed to RF through the tophole of a TEM-cell. Mea-
surement method according SAE J1752.
c)The two bus lines are transferred into a BCI current injection probe. Setup and measurement method is
described in ISO 11452-4.
Failure criteria:
Failure monitoring is done by envelope measurement of the logic signals with a LeCroy oscilloscope with acceptance levels of 20% in amplitude and 2% time.
Limits:
The device is measured within the described setup and limitswithout fail function.
The Electromagnetic Susceptivity is not tested in production.
a) Field strength under stripline of > 250V/m in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
b) Field strength in TEM-cell of > 500V/m in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
c) RF-currents with BCI of > 100mA in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
9/13
L9333
Measured Circuit
The EMS of the device was verified in the below described setup.
Figure 5.
Ω
11
100
∗
optional
4
Ω
20k
Ω
10k
Jumper
Ω
10k
4.7nF 4.7nF
ANECHOIC CHAMBER
10nF
33µF
SM6T39A
SMBYW01-200
1
19
Jumper
DIAG
VSENPRG
4 ∗ 10kΩ
14
16
OUT1
IN1
8
13
OUT2
L9333
IN2
4
17
7
4 ∗ 1nF
optional
OUT3
IN3
4.7nF
OUT4
GND
IN4
4 ∗ 4.7n
5
9
10/13
2m
Stripline
Flat cable
11
1
9
14
13
8
7
16
125Hz
17
2
f
U(t)
4
250Hz
500Hz
2
f
14V
-
+
5
1kHzf2
L9333
DIM.
MIN.TYP.MAX.MIN.TYP.MAX.
A2.352.650.0930.104
A10.10.30.0040.012
B0.330.510.0130.020
C0.230.320.009
D12.6130.4960.512
E7.47.60.2910.299
e1.270.050
H1010.65 0.3940.419
h0.250.750.0100.030
L0.41.270.0160.050
K0°(min.)8°(max.)
mminch
0.013
OUTLINE AND
MECHANICAL DATA
SO20
B
e
D
1120
110
L
hx45°
A
K
A1C
H
E
SO20MEC
11/13
L9333
PAD
L9333
12/13
L9333
Information furnished is believed tobe accurate and reliable. However,STMicroelectronics assumes no responsibility for the consequences
of useof such information nor for any infringementof patents or other rightsof third partieswhich may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products arenot
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2000 STMicroelectronics - All Rights Reserved
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STMicroelectronics GROUP OF COMPANIES
- Sweden- Switzerland - United Kingdom - U.S.A.
http://www.st.com
13/13
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