ST L9333 User Manual

■

WIDE OPERATING SUPPLY VOLTAGE
RANGE FROM 4.5V UP TO 32V FOR
TRANSIENT 45V

■

VERY LOW STANDBY QUIESCENT
CURRENT TYPICALLY < 2µA

■

INPUT TO OUT PUT SIGN A L T RANSF ER
FUNCTION PROGRAMMABLE

■

HIGH SIGNAL RANGE FROM -14V UP TO 45V
FOR ALL INPUTS

■

3.3V CMOS COMPATIBLE INPUTS

■

DEFINED OUTPUT OFF STATE FOR OPEN
INPUTS

■

FOUR OPEN DRAIN DMOS OUTPUTS, WITH
R

= 1.5Ω FOR VS > 6V AT 25°C

DSon

■

OUTPUT CURRENT LIMITATION

■

CONTROLLED OUTPUT SLOPE FOR LOW EMI

■

OVERTEMPERATUR E PR O TECTION FOR
EACH CHANNEL

■

INTEGRATED OUTPUT CLAMPING FOR FAST
INDUCTIVE RECIRCULATION V

> 45V

FB

L9333

QUAD LOW SIDE DRIVER

MULTIPOWER BCD TECHNOLOGY

SO20 (12+4+4) DIE

ORDERING NUMB ERS :

L9333MD
L9333DIE1

■

STATUS MONITORING FOR

- OVERTEMPERATU RE

- DISCONNECTED GROUND OR SUPPLY
VOLTAGE

DESCRIPTION

The L9333 is a monolithic integrated quad low side
driver. It is intended to drive lines, lamps or relais in
automotive or industrial applications.

(SO20 12+4+4)

(DIE)

BLOCK DIAGRAM

March 2001

IN 4

IN 1

PRG

EN

VS

GND

CHANNEL4

VS

R

IN

PRG

R

IN

R

EN

=

&

THERMA L

SHUT­DOWN

4

DIAG-

NOSTIC

LOG IC

REFERENCE

CHANNEL1

Vint
Vlogic

OUT 4

OUT 1

DIA G

1/13

L9333

PIN CONNECTION

(Top view)

IN1
IN2

DIAG

GND
GND

GND
GND

VS

IN3
IN4

1

2

3

4

5

6

7

813

9

10 11

So 12+4+4

20

PRG

19

OUT1

18

OUT2

17

GND

16

GND

15

GND

14

GND

Med. Power

OUT3

12

OUT4
EN

PIN FUNCTION

Pin

N°

1 IN 1 Input 1
2 IN 2 Input 2
3 DIAG Diagnostic

4, 5, 6, 7,

14, 15,

16, 17

8 VS Supply Voltage

9 IN 3 Input 3
10 IN 4 Input 4
11 EN Enable
12 OUT4 OUTPUT4
13 OUT 3 OUTPUT 3
18 OUT 2 OUTPUT 2
19 OUT 1 OUTPUT 1

Pin Name Description

GND Ground

20 PRG Programming

2/13

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

L9333

V

dV

S

, VEN,

V

IN

V

PRG

V

OUT

V

DIAG

Note 1) : In f lyback phase th e output voltage can reach 60V .

Supply voltage DC

S

Supply voltage Pulse (T = 400ms)

-0.3 to 32

-0.3 to 45

/dt Supply voltage transient -10 to +10 V/µs

Input, Enable, Programming

-14 to 45 V

Pin voltage
Output voltage

-0.3 to 45

1)

Diagnostic output voltage -0.3 to 45 V

ESD - PROTECTION

Parameter

Supply pins and signal pins ± 2 KV
Output pins ± 4 KV

Note: Human-Body-Model according to MIL 883C. The device widthstand ST1 class level.

Value

against GND

THERMAL DATA

Symbol Parameter Min Typ Max Unit

V
V

V

Unit

T

T

JSDhys

JSD

Temperature shutdown threshold 175 220 °C
Temperature shutdown hysteresis 20 K

SO 12+4+4

R

th (j-p)

R

th (j-a)

Note 2) : With 6cm2 on board heat sink area.

Thermal resistance junction to pins 15 °C/W

Thermal resistance junction to ambient

2)

LIFE TIME

Symbol Parameter Condition Value Unit

t

B

t

b

useful life time V

≤ 14V

S

EN = low

operating life time 4.5V ≤ VS ≤ 32V

EN = high

20 years

5000 hours

50 °C/W

3/13

L9333

OPERATING RANGE:

Within the operating range the IC oper ates as descr ibed i n the circui t desc r iption, includ ing the diagnos tic table.

Symbol Parameter Condition Min Max Unit

V

S

VIN, VEN,

V

PRG

V

OUT

Supply voltage 4.5 32 V
Input voltage -14 45 V

Output voltage Voltage will be limited by internal Z-

-0.3 60 V

Diode clamping

V

DIAG

T

J

Diagnostic output voltage -0.3 45 V
Junction temperature -40 150 °C

ELECTRICAL CHARACTERISTCS

The electrical characteristics are valid within the defined Operating Conditions, unless otherwise specified.
The function is guaranteed by design until T

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

Quiescent current VS ≤ 14V; VEN ≤ 0.3V

I

Q

switch-on-threshold.

JSDon

T

85 °C

amb

VS ≤ 14V; VEN ≤ 0.3V
Ta 150°C

VS ≤ 14V; EN = high, Output = off
EN = high, Output = on

< 2 10 µA

50 µA

12

3.5

mA
mA

Inputs, IN1 - IN4; Programming, PRG

V

INlow

V

INhigh

R

Note 3) : Current direction depends on the programming settin g (PRG=high leads into a positi ve current see also Blockdi agram page 1)

Input voltage LOW -14 1 V
Input voltage HIGH 2 45 V

I

Input current

IN

Input impedance VIN < 0V; VIN > V

IN

0V ≤ V

IN

≤ 45V

3)

S

-25 50 µA

10 60 kΩ

Enable EN

V

ENlow

V

ENhigh

R

I

Input voltage LOW -14 1 V
Input voltage HIGH 2 45 V
Input impedance -14V < VEN < 1.5V 5 kΩ

EN

Input current 1.5V < VEN < 45V 5 80 µA

EN

4/13

L9333

ELECTRICAL CHARACTERISTCS

(continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Outputs OUT1- OUT4

R

DSon

I

OLeak

Output ON-resistor VS > 6V, IO = 0.3A 1.7 3.8 Ω
Leakage current VO = VS = 14V; Ta < 125°C 1 5 µA

VO = VS = 14V; Ta < 150°C 25 µA

V

OClamp

I

OSC

C

Output voltage during clamping E

≤ 2mJ; 10 mA < I

FB

< 0.3A 45 52 6 0 V

O

Short-circuit current VS > 6V 400 700 1000 mA
internal output capacities VO > 4.5V 100 pF

O

Diagnostic Output DIAG

V

Dlow

I

Dmax

Output voltage LOW IDL = 0.6mA 0.8 V
Max. output current internal current limitation; VD =

1515mA

14V

I

DLeak

Leakage current VD = VS = 14 V; Ta < 125 °C 0.1 1 µA

VD = VS = 14 V; Ta < 150 °C 5 µA

Timing Characteristics

4)

t

d,on

t

d,off

t

t

d,DIAG

S

Note : All para m eters are meas ured at 125°C.
Note 4) : See als o F i g.3 Timing Characteristics

On delay time VS = 14V
Off delay time 3 4.5 µs
Enable settling time 20 µs

set

ON or OFF Diagnostic delay time 10 µs
Output voltage slopes 2.5 9 16 V/µs

out

C

= 0F; L

ext

ext

= 0H

only testing condition

≤ I

≤ 200mA

0

10mA

23.5µs

5/13

L9333

Figure 1. Tim in g C haracteristic s

V

EN

Active

V

PRG

V

OUT

0.8 V

t

Non-Inverting Mode Inverting Mode

t

V

IN

t

V

S
S

5)

0.2 V

S

t

set

Note 5) : Output voltage slope not controlled for enable low!

t

d,off

t

d,on

6/13

t

t

set

L9333

FUNCTIONAL DESCRIPTION

The L9333 is a quad low si de dr iver for l ines, l amps or i nductive loads in automoti ve and i ndustr ial a pplicati ons.
The logic input levels are 3.3V CMOS compatible. This allows the device to be driven directly by a microcon-

troller. For the noise immunity, all input thresholds have a hysteresis of typ. 100mV. Each input (IN, EN and
PRG) is protected to withstand vol tages from -14V to 45V. The device is activated with a ' high' sign al on ENable.
ENable 'low' switches the device into the sleep mode. In this mode the quiescent current is typically less than
2µA. A high signal on PRoGramming input c hanges the signal transfer polarity from noninv erting to the inv erting
mode. This pin can be connected either to V
PRG and EN pin is low. For packaged applications it is still recommended to connect all input pins to ground
respective VS to avoid EMC influence. The forced condition leads to a mode change if the PRG pin was high
before the interrupti on. Independent of the PRoGramming input, the OUTput switches off, i f the s ignal INput pin
is not connected. This function is verified using a leakage current of 5µA (sink for PRG=high; source for
PRG=low) during circuit test.

Each output driver has a current limitation of min 0.4A and an independent thermal shut-down. The thermal
shut-down deactivates that output, which exceeds temperature switch off lev el. When the juncti on temperatur e
decreases 20K below this temperature threshold the output will be activated again. This 20K is the hysteresis
of the thermal shutdown function. The Gates, of the output DMOS transistors are charged and discharged with
a current source. Therefore the output slope is limited. This reduces the electromagnetic radiation. For induc­tive loads an output voltage clamp of typically 52V is implemented.

The DIAGnostic is an open drain output. The logic status depends on the PRoGramming pin. If the PRG pin is
'low' the DIAG output becomes low, if the device works correctly. At thermal shut-down of one channel or if the
ground is disconnected the DIAGnostic output becomes high. If the PRG pin is 'high' this output is switched off
at normal function and switched on at overtemper ature. For the fault conditi on of inter rupted ground, the poten­tial of VS and Diagnostic should be equal.

or GND. If these pins are not connected, the forced status of the

S

DIAGNO STIC TABL E

Pins EN PRG IN OUT DIAG

Normal function H L L L (on) L (on)

H L H H (off) L (on)
H H L H (off) H (off)
H H H L (on) H (off)

L X X H (off) H (off)

Overtemperature,
disconnected ground or
supply voltage

Overtemperature H H X

X = not relevant
* selective for each channel at overtemperature

HLX

H (off)

H(off)

*

*

H (off)

L(on)

7/13

L9333

Figure 2. Application for Inverting Transfer Polarity

BOARD VOLTAGE 1 4 V

VCC = 5V or 3.3V

33µF

VCC

INT

PRG

VS

DIAG

EN

IN 1
IN 2
IN 3
IN 4

L9333

OUT 1
OUT 2
OUT 3
OUT 4

GND

MICROCONTROLLER

GND

D 0
D 1
D 2
D 3

AdressdecoderA 0:8

8

Figure 3. Application for non Inverting Transfer Polarity

BOARD VOLTAGE 14 V

33µF

2 W 12 mH

50 kHz

M

10µH

250 mA

240

50pF

VCC = 5V

Ω

VCC

IN

GND

VS

PRG

DIAG

EN

L9333

OUT 1

IN 1

OUT 2

IN 2

OUT 3

IN 3

OUT 4

IN 4

GND

Note We re commend to use th e device for dri ving inductive loads with flyback energy EFB ≤ 2mJ.

2 W 12 mH

8/13

10µH

M

250 mA

240

50pF

VCC = 5V

Ω

VCC

IN

GND

L9333

EMC SPECIFICA TION
EMS (electromagnetic susceptibility)

Measurement setup:
DUT mounted on a specific application board is driven in a typical application circuit (see below). Two devices

are stimulated by a generator to read and write bus signals. They will be monitored externally to ensure proper
function.

Measurement method:

a) The two bus lines are transferred 2m under a terminated stripline. That's where they were exposed to the

RF-field. Stripline setup and measurement method is described in DIN 40839-4 or ISO 11452-5.

b) DUT mounted on the same application board is exposed to RF through the tophole of a TEM-cell. Mea-

surement method according SAE J1752.

c) The tw o bus lines are transferred into a BCI current injection probe. Setup and measurement method is

described in ISO 11452-4.

Failure criteria:

Failure monitoring is done by envelope measurement of the logic signals with a LeCroy oscilloscope with ac­ceptance levels of 20% in amplitude and 2% time.

Limits:

The device is measured within the described setup and limits without fail function.
The Electromagnetic Susceptivity is not tested in production.

a) Field strength under stripline of > 250V/m in the frequency range 1 - 400MHz modulation:AM 1kHz 80%.
b) Field strength in TEM-cell of > 500V/m in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.
c) RF-currents with BCI of > 100mA in the frequency range 1 - 400MHz modulation: AM 1kHz 80%.

Measured Circuit

The EMS of the device was verified in the below described setup.

9/13

L9333

Figure 4.

11

Jumper

ANECHOIC CHAMBER

SMBYW01-20 0

1

Ω

100

∗

optional

4

Ω

20k

Ω

10k

Ω

10k

4.7nF 4.7nF

10nF

33µF

SM6T39A

Jumper

14

19

DIAG

VS EN PRG

Ω

10k

∗

4

16

8

13

OUT1

7

1nF

∗

4

optional

OUT2

OUT3

4.7nF

OUT4

GND

L9333

IN1

IN2

IN3

IN4

4.7n

∗

4

4

5

17

9

10/13

2m

Stripline

Flat cable

11

1
9

14

13
8
7

16

125Hz

17

2

250Hz

f

U(t)

4

2

f

2

500Hz

f

14V

-

+

5

1kHz

L9333

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0 .093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0 .013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

K 0˚ (min.)8˚ (max.)

mm inch

OUTLINE AND

MECHANICAL DATA

SO20 (12+4+4)

B

e

D

1120

110

PAD

L

h x 45˚

A

K

A1

C

H

E

SO20MEC

11/13

L9333

L9333

12/13

L9333

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise unde r any patent or patent right s of STMic roelectronics. Specifications ment i oned in this p ublication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized for use as crit i cal component s in l i fe support devi ces or systems wi t hout express written approva l of STMicroelectronics.

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 2001 STMi croelectroni cs - All Rights Reserved

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13/13