ST L6997S User Manual

L6997S

STEP DOWN CONTROLLER

FOR LOW VOLTAGE OPERATIONS

1 Features

■ FROM 3V TO 5.5V V

■ MINIMUM OUTPUT VOLTAGE AS LOW AS

0.6V

■ 1V TO 35V INPUT VOLTAGE RANGE

■ CONSTANT ON TIME TOPOLOGY

■ VERY FAST LOAD TRANSIENTS

■ 0.6V, ±1% VREF

■ SELECTABLE SINKING MODE

■ LOSSLESS CURRENT LIMIT, AVAILABLE

ALSO IN SINKING MODE

■ REMOTE SENSING

■ OVP,UVP LATCHED PROTECTIONS

■ 600µA TYP QUIESCENT CURRENT

■ POWER GOOD AND OVP SIGNALS

■ PULSE SKIPPING AT LIGTH LOADS

■ 94% EFFICIENCY FROM 3.3V TO 2.5V

RANGE

2 Applications

■ NETWORKING

■ DC/DC MODULES

■ DISTRIBUTED POWER

■ MOBILE APPLICATIONS

■ CHIP SET, CPU, DSP AND MEMORIES

SUPPLY

Figure 2. Minimum Component Count Application

Rin1Rin2

VDR

OSC

BOOT

HGATE

PHASE

LGATE

PGND

GND

GNDSENSE

Rilim

VCC

PGOOD OVP

L6997S

ILIM

Figure 1. Package

TSSOP20

Table 1. Order Codes

Part Number Package

L6997S TSSOP20

L6997STR Tape & Reel

3 Description

The device is a high efficient solution for networking dc/dc modules and mobile applications compatible with 3.3V bus and 5V bus.

It's able to regulate an output voltage as low a s 0.6V. The constant on time topology assures fast load tran-

sient response. The embedded voltage feed-forward provides nearly constant switching frequency operation in spite of a wide input voltage range.

An integrator can be introduced in the control loop to reduce the static output voltage error.

The remote sensing improves the static and dynamic regulation, recovering the wires voltage drop.

Pulse skipping technique reduces power consumption at light loads. Drivers current capability allows output currents in excess of 20A.

3.3V

Cin

Dboot

Cboot

Ro1

Ro2

0.6V

Cout

June 2004

Css

SHDN

VSENSE

INT VFB Vref

Cvref

REV. 1

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L6997S

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

PHASE

BOOT, HGATE

and PHASE

PINS

OTHER PINS ±2000 V

tot

stg

Table 3. Thermal Data

Symbol Parameter Value Unit

th j-amb

VCC to GND -0.3 to 6 V V

to GND -0.3 to 6 V

HGATE and BOOT, to PHASE -0.3 to 6 V HGATE and BOOT, to PGND -0.3 to 42 V PHASE -0.3-to 36 V LGATE to PGND -0.3 to V ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF,

INT, GND

SENSE

to GND

-0.3 to V

Maximum Withstandin g Voltage Range

+0.3 V

±750 V Test Condition:CDF-AEC-Q100-002 “Human Body Model” Accepatance Criteria: “Normal Performance”

Power dissipation at T

= 25°C 1 W

amb

Storage temperature range -40 to 150 °C

Thermal Resistance Junction to Ambient 125 °C/W Junction operating temperature range -40 to 125 °C

Figure 3. Pin Connection (Top View)

NOSKIP

GNDSENSE

INT

VSENSE

VCC GND

VREF

VFB

OSC

20 2 3 4 5 6 7 8 9 10SS

TSSOP20

BOOT1 HGATE PHASE VDR LGATE PGND PGOOD OVP SHDN ILIM

Table 4. Pin Function

N° Name Description

1 NOSKIP Connect to V 2 GNDSENSE Remote ground sensing pin 3 INT Integrator output. Short this pin to VFB pin and connect it via a capacitor to V

integrator in the control loop. If the integrator is not used, short this pin to VREF.

4 VSENSE This pin must be connected to the remote output voltage to detect overvoltage and

undervoltage conditions and to provide integrator feedback input.

to force continuous conduction mode and sink mode.

to insert the

OUT

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L6997S

Table 4. Pin Function (continued)

N° Name Description

5VCCIC Supply Voltage. 6 GND Signal ground 7 VREF 0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and

8 VFB PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or

9 OSC Connect this pin to the input voltage through a voltage divider in order to provide the feed-

10 SS Soft Start pin. A 5µA constant current charges an external capacitor. Itsvalue sets the soft-

11 ILIM An external resistor connected between this pin and GND sets the current limit threshold don’t

12 SHDN Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left

13 OVP Open drain output. During the over voltage condition it is pulled up by an external resistor. 14 PGOOD Open drain output. It is pulled down when the output voltage is not within the specified

15 PGND Low Side driver ground. 16 LGATE Low Side driver output. 17 V

18 PHASE Return path of the High Side dr iver. 19 HGATE High side driver output. 20 BOOT Bootstrap capacitor pin. High Side driver is supplied through this pin.

ground. This pin is capable to source or sink up to 250uA

to VSENSE to disable the integrator function.

forward function don’t leave floating.

start time do n’t leave floating.

leave floating..

floating.

thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating.

Low Side driver supply.

Table 5. Electrical Characteristics

= VDR = 3.3V; T

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY SECTION

Vin Input voltage range Vout=Vref Fsw=110Khz Iout=1A 1 35 V

Turn-onvoltage 2.86 2.97 V

Turn-off voltage 2.75 2.9 V Hysteresis 90 mV

IqV

Drivers Quiescent Current VFB > VREF 7 20 µA

IqVcc Device Quiescent current VFB > VREF 400 600 µA

SHUTDOWN SECTION

SHDN Device On 1.2 V

Device Off 0.6 V

SHVDR

SHVCC

Drivers shutdown current SHDN to GND 5 µA Devices shutdown current SHDN to GND 1 15 µA

SOFT START SECTION

∆V

Soft Start current VSS = 0.4V 4 6 µA

Active Soft start and voltage 300 400 500 mV

= 0°C to 85°C unless otherwise specified)

amb

35.5V

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L6997S

Table 5. Electrical Characteristics (continued)

= VDR = 3.3V; T

Symbol Parameter Test Condition Min. Typ. Max. Unit

CURRENT LIMIT AND ZERO CURRENT COMPARATOR

Input bias current R

LIM

Zero Crossing Comparator offset Phase-gnd

Current limit factor 1.6 1.8 2 µA

ILIM

ON TIME

Ton On time duration V

OFF TIME

OFFMIN

Minimum off time 600 ns K

OSC/TOFFMIN

VOLTAGE REFERENCE

VREF Voltage Accuracy 0µA < I

PWM COMPARATOR

Input voltage offset -2 +2 mV

Input Bias Current 20 nA

INTEGRATOR

Over Voltage Clamp V Under Voltage Clamp V Integrator Input Offset Voltage

SENSE-VREF

VSENSE

Input Bias Current 20 nA

GATE DRIVERS

High side rise time V High side fall time 50 100 ns Low side rise time V Low side fall time 50 90 ns

UVP/OVP PROTECTIONS

GOOD

OVP Over voltage threshold with respect to V UVP Under voltage threshold 67 70 73 %

Upper threshold (V

SENSE-VREF

Lower threshold (V

SENSE-VREF

PGOOD

= 0°C to 85°C unless otherwise specified)

amb

= 2KΩ to 200KΩ 4.655.4µA

ILIM

REF=VSENSE

OSC=125mV 720 800 880 ns OSC=250mV 370 420 470 ns OSC=500mV 200 230 260 ns OSC=1000mV 90 115 140 ns

OSC=250mV 0.20 0.40

< 100µA 0.594 0.6 0.606 V

REF

= V

SENSE SENSE

= GND 0.45 0.55 0.65 V

=3.3V; C=7nF

HGATE - PHASE from 1 to 3V

=3.3V; C=14nF

LGATE from 1 to 3V

REF

rising 110 112 116 %

SENSE

)

falling 858891%

SENSE

)

=2mA 0.2 0.4 V

Sink

-2 2 mV

0.62 0.75 0.88 V

-4 -4 mV

50 90 ns

118 121 124 %

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Figure 4. Functional & Block Diagram

Vcc

L6997S

OUT

GNDVCCOVPPGOODSHDN

overvoltage comparator

VSENSE

1.12 VREF

-+undervoltage comparator

VSENSE

0.6 VREF

pgood comparators

LS and HS anti-cross-conduction comparators

VSENSE

1.075 VREF

comp

V(LGATE)<0.5V

VSENSE

BOOT

VCC

0.925 VREF

HGATE

HS driver

level shifter

V(PHASE)<0.2V

comp

Toff min

PHASE

delay

VDR

Ton min

one-shot

PGND

LGATE

LS driver

Ton

one-shot

Ton

OSC

VSENSE

one-shot

OSC

VSENSE

Ton= Kosc V(VSENSE)/V(OSC)

no-skipno-skip

mode

comparator

negative current limit

PHASE

++-

PHASE

ILIM

0.05

zero-cross comparator

LS control

Ton= Kosc V(VSENSE)/V(OSC)

NOSKIP

IC enable

control

soft-start

5 uA

power management

ILIM

comparator

positive current limit

PHASE

+-+

+VREF

0.05

HS control

VREF

pwm comparator

VREF

INT

VSENSE

SENSEGND

OSC

1.236V

bandgap

VREF

1.416 Reference chain

0.6V

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L6997S

4 DEVICE DESCRIPTION

4.1 Constant On Time PWM topology Figure 5. Loop block schematic diagram

Vin

One-shot generator

OSC

Vsense

Vref

FFSR

HGATE

LGATE

Vout

PWM comparator

The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time duration forced by the one-shot generator. The On Time is directly proportional to VSENSE pin voltage and inverse to OSC pin voltage as in Eq1:

SENSE

where K

= 180ns and τ is the internal propagation delay time (typ. 40ns). The system imposes in steady

OSC

state a minimum On Time corresponding to V responding Ton will not decrease. Connecting the OSC pin to a voltage partition from V steady-state switching frequency F

OUT

-------------- -

== =

-----------

--------------------- -

OSC

independent of VIN. It results:

OSC

-------------- -

OUT

τ+=

= 1V. In fact if the V

OSC

---------------

OSC

→ fSWK

OSC

(1)

voltage increases above 1V th e cor-

OSC

OSCαOUT

to GND, it allows a

(2)

where

OSC

OUT

-------------- -

OUT

The above equations allow setting the frequency divider ratio α that such equations hold only if V

<1V. Further the Eq2 shows how the system has a switching frequen-

OSC

cy ideally independe nt fr om the i npu t vo lta ge. T h e del ay in tro duc es a ligh t dep end enc e fr om V

--------------------==

R2R1+

--------------------==

R3R4+

(3)

(4)

once output voltage has been set; note

OSC

. A mini-

mum Off-Time constraint of about 500ns is introduced in order to assure the boot capacitor charge and to

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L6997S

limit the switchin g frequency after a loa d transient as well as to mask PWM comp arator output again st noise and spikes.

The system has not an in ternal clock, becau se this is a hys teretic controller, so the turn on pulse wi ll start if thre e conditions are met contemporarily: the FB pi n voltage i s lower than the r eference volt age, the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity.

4.2 Closing the loop

The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage (0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4.

The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of DC error. Further the system regulates the output voltage valley value not the average, as shown in Figure 6. So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To compensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal integrator amplifier with t he extern al capacitor C an AC path for output ripple.

introduces a DC pole in the control loop. C

INT1

also provides

INT1

Figure 6. Valley regulation

Vout

DC Error Offset

<Vout>

Vref

Time

The integrator amplifier generates a c urrent, proportional to the DC error s, that increases the output capaci tance voltage in order to compensate the total st atic error. A v oltage clamp within the devi ce forces anINT pin v oltage range (V

-50mV, V

REF

+150mV). This is useful to avoid or smooth output voltage overshoot during a load

REF

transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peakto-peak amplitude is less than 150mV in steady state.

In case the ripple amplitude is larger than 150mV, a capacitor C

can be connected between INT pin and

INT2

ground to reduce ripple amplitude at INT pin, otherwise the int egrator will operate out of its linear range. Choose C

according to the following equation:

INT1

⋅

INTαOUT

INT1

where g

=50 µs is the integrator transconductance,

INT

the close loop bandwidth. This equation holds if C

-------------------------------=

2 π F

⋅⋅

(5)

is the output divider ratio given from Eq4 and FU is

OUT

is connected between INT pin and ground. C

INT2

is given

by:

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L6997S

Where

--------------- -

∆

is the output ripple and ∆V

OUT

INT2 INT1

∆

------------------=

∆V

OUT

INT

Figure 7. Integrator loop block diagram

Vin

Cint2

One-shot generator

OSC

From Vsense Vref

INT

Integrator amplifier

PWM comparator

(6)

is the required ripple at the INT pin (100mV typ).

PCB TRACES

FFSR

HGATE

LGATE

Vref

Vsense

Gndsense

Vout

LOAD

Cint1

Respect to a traditional P WM con t roller, that has an internal oscil lator s etti ng the switching frequency, i n a hys teretic system the frequency can change with some parameters. Fo r example, while in a standard fixed s witc hing frequency topology, the increase of the losses (increasing the output current, for example) generates a variation in the On Time and Off Time, in a fixed On Time topology , the increase of the losses generates only a variation on the Off Time, changing the switching frequency. In the device is implemented the voltage feedforward circuit that allows constant swi tchi ng fr equency during s teady -sate oper atio n and withi nthe inp ut rang e variation. Any way there are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depends on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.

During a positive load transient, (the output current increases), the conve rter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off).

4.3 Transition from PWM to PFM/PSK

To achieve high efficie ncy at light loa d conditi ons, PFM mode i s provided. The PFM mode differs fr om the PWM mode essentially for the off phase; the on phase is the same. In PFM after a On cycle the system turns-on the low side MOSFET until the inductor current goes down zero, when the zero-crossing comparator turns off the low side MOSFET. In PWM mode, after On cycle, the system keeps t he low side MOSFET on unti l the next turnon cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in an hysteretic controller enabling the zero current comparator by enabling, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down to reference value. The device wor ks in discontinuous mod e

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L6997S

at light load and in continuous mode at high load. The transition from PFM to PWM occu rs when load curr ent is around half the inductor current ripple. This threshold value depends on V the inductor value is, the smaller the threshold is. On the other hand, the bigger the i nductor value is, the sl ower the transient response is. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mai nly due to the ver y low loa d. If the PFM i s not c ompati ble wi th the appl ic ation it can be disabled connecting to V

the NOSKIP pin.

4.4 Softstart

After the device is turned on the SS pin voltage begin s to increase and the system star ts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range for the V internal current source (5

voltage (where the output current limit increase linearly) is from 0.6V to 1V. In this range an

A Typ) charges the capacitor on the SS pi n; the reference curr ent (for the current li mit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5 voltage is close to 1V the maximum current lim it is active. Output protecti ons OVP & UVP are disab led until the SS pin voltage reaches 1V (see figure 8).

Once the SS pin voltage reaches the 1V value, the voltage on SS pin doesn't impact the system operatio n anymore. If the SHDN pin is turned on before the supplies, the power section must be turned on before the logic section. While if the supplies are applied with the SHND pin off, the start up sequence doesn't meter.

Figure 8. Soft -Start Diagram

Vss

, L, and V

. Note that the higher

OUT

A (Typ.). When SS

4.1V

0.6V

Ilim current

Soft-start active range

Time

Maximum current limit

Time

Because the system implements the s oft s tart by contr ol lin g the inductor current, the soft star t capac itor s houl d be selected based on of the output capacitance, the current limit and the soft start active range (

∆

VSS).

In order to select the softstart capacitor i t must be imposed that the output voltage reaches the final value before the soft start voltage reaches the under voltage value (1V). After this UVP and OVP are enable.

The time necessary to charge the SS capacitor up to 1V is given by:

TSSCSS()

--------

Iss

CSS⋅=

(7)

In order to calculate the output voltage chargin time it should be considered that the inductor current function can be supposed linear function of the time.

t,CSS()

ilim/RdsonKILIMISS

-------------------------------------------------------------------------- -=

⋅∆()

SSCSS

t⋅⋅⋅()

(8)

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