ST L6997S User Manual

L6997S

STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONS

1 Features

■FROM 3V TO 5.5V VCC RANGE

■MINIMUM OUTPUT VOLTAGE AS LOW AS 0.6V

■1V TO 35V INPUT VOLTAGE RANGE

■CONSTANT ON TIME TOPOLOGY

■VERY FAST LOAD TRANSIENTS

■0.6V, ±1% VREF

■SELECTABLE SINKING MODE

■LOSSLESS CURRENT LIMIT, AVAILABLE ALSO IN SINKING MODE

■REMOTE SENSING

■OVP,UVP LATCHED PROTECTIONS

■600 A TYP QUIESCENT CURRENT

■POWER GOOD AND OVP SIGNALS

■PULSE SKIPPING AT LIGTH LOADS

■94% EFFICIENCY FROM 3.3V TO 2.5V

2 Applications

■NETWORKING

■DC/DC MODULES

■DISTRIBUTED POWER

■MOBILE APPLICATIONS

■CHIP SET, CPU, DSP AND MEMORIES SUPPLY

Figure 2. Minimum Component Count Application

Figure 1. Package

TSSOP20
Table 1. Order Codes
Part Number		Package
L6997S		TSSOP20
L6997STR		Tape & Reel

3 Description

The device is a high efficient solution for networking dc/dc modules and mobile applications compatible with 3.3V bus and 5V bus.

It's able to regulate an output voltage as low as 0.6V. The constant on time topology assures fast load transient response. The embedded voltage feed-forward provides nearly constant switching frequency operation in spite of a wide input voltage range.

An integrator can be introduced in the control loop to reduce the static output voltage error.

The remote sensing improves the static and dynamic regulation, recovering the wires voltage drop.

Pulse skipping technique reduces power consumption at light loads. Drivers current capability allows output currents in excess of 20A.

				3.3V
		Rin2	Rin1
				Cin
VCC	VDR	OSC		Dboot
		BOOT
		HGATE	HS	Cboot
				L
				0.6V
		PHASE
PGOOD				Ro1
		LGATE
OVP			LS	DS
L6997S				Cout
				Ro2
ILIM		PGND
		GND
Rilim		GNDSENSE
SS		VSENSE
Css		INT
		VFB
SHDN		Vref
			Cvref

REV. 1

June 2004

1/30

L6997S

Table 2. Absolute Maximum Ratings

Symbol	Parameter		Value	Unit
VCC	VCC to GND		-0.3 to 6	V
VDR	VDR to GND		-0.3 to 6	V
	HGATE and BOOT, to PHASE		-0.3 to 6	V
	HGATE and BOOT, to PGND		-0.3 to 42	V
VPHASE	PHASE		-0.3-to 36	V
	LGATE to PGND		-0.3 to VDR+0.3	V
	ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF,		-0.3 to VCC+0.3	V
	INT, GNDSENSE to GND
BOOT, HGATE	Maximum Withstanding Voltage Range		±750	V
and PHASE	Test Condition:CDF-AEC-Q100-002 “Human Body Model”
PINS	Accepatance Criteria: “Normal Performance”
OTHER PINS			±2000	V
Ptot	Power dissipation at Tamb = 25°C		1	W
Tstg	Storage temperature range		-40 to 150	°C

Table 3. Thermal Data

Symbol	Parameter	Value	Unit
Rth j-amb	Thermal Resistance Junction to Ambient	125	°C/W
Tj	Junction operating temperature range	-40 to 125	°C

Figure 3. Pin Connection (Top View)

NOSKIP	1	20	BOOT
GNDSENSE	2	19	HGATE
INT	3	18	PHASE
VSENSE	4	17	VDR
VCC	5	16	LGATE
GND	6	15	PGND
VREF	7	14	PGOOD
VFB	8	13	OVP
OSC	9	12	SHDN
SS	10	11	ILIM
		TSSOP20

Table 4. Pin Function

N°	Name	Description
1	NOSKIP	Connect to VCC to force continuous conduction mode and sink mode.
2	GNDSENSE	Remote ground sensing pin
3	INT	Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the
		integrator in the control loop. If the integrator is not used, short this pin to VREF.
4	VSENSE	This pin must be connected to the remote output voltage to detect overvoltage and
		undervoltage conditions and to provide integrator feedback input.

2/30

		L6997S
Table 4. Pin Function (continued)
N°	Name	Description
5	VCC	IC Supply Voltage.
6	GND	Signal ground
7	VREF	0.6V voltage reference. Connect a ceramic capacitor (max. 10nF) between this pin and
		ground. This pin is capable to source or sink up to 250uA
8	VFB	PWM comparator feedback input. Short this pin to INT pin to enable the integrator function, or
		to VSENSE to disable the integrator function.
9	OSC	Connect this pin to the input voltage through a voltage divider in order to provide the feed-
		forward function don’t leave floating.
10	SS	Soft Start pin. A 5 A constant current charges an external capacitor. Itsvalue sets the soft-
		start time don’t leave floating.
11	ILIM	An external resistor connected between this pin and GND sets the current limit threshold don’t
		leave floating..
12	SHDN	Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left
		floating.
13	OVP	Open drain output. During the over voltage condition it is pulled up by an external resistor.
14	PGOOD	Open drain output. It is pulled down when the output voltage is not within the specified
		thresholds. Otherwise is pulled up by external resistor. If not used it can be left floating.
15	PGND	Low Side driver ground.
16	LGATE	Low Side driver output.
17	VDR	Low Side driver supply.
18	PHASE	Return path of the High Side driver.
19	HGATE	High side driver output.
20	BOOT	Bootstrap capacitor pin. High Side driver is supplied through this pin.

Table 5. Electrical Characteristics

(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)

Symbol		Parameter	Test Condition	Min.	Typ.	Max.	Unit
SUPPLY SECTION
Vin		Input voltage range	Vout=Vref Fsw=110Khz Iout=1A	1		35	V
VCC,				3		5.5	V
VDR
VCC		Turn-onvoltage		2.86		2.97	V
		Turn-off voltage		2.75		2.9	V
		Hysteresis			90		mV
IqVDR		Drivers Quiescent Current	VFB > VREF		7	20	A
IqVcc		Device Quiescent current	VFB > VREF		400	600	A
SHUTDOWN SECTION
SHDN		Device On		1.2			V
		Device Off				0.6	V
ISHVDR		Drivers shutdown current	SHDN to GND			5	A
ISHVCC		Devices shutdown current	SHDN to GND		1	15	A
SOFT START SECTION
ISS		Soft Start current	VSS = 0.4V	4		6	A
∆ VSS		Active Soft start and voltage		300	400	500	mV

3/30

L6997S

Table 5. Electrical Characteristics (continued)

(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)

Symbol		Parameter		Test Condition	Min.	Typ.	Max.	Unit
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
ILIM		Input bias current		RILIM = 2KΩ to 200KΩ	4.6	5	5.4	µA
		Zero Crossing Comparator offset			-2		2	mV
		Phase-gnd
KILIM		Current limit factor			1.6	1.8	2	µA
ON TIME
Ton		On time duration		VREF=VSENSE OSC=125mV	720	800	880	ns
				VREF=VSENSE OSC=250mV	370	420	470	ns
				VREF=VSENSE OSC=500mV	200	230	260	ns
				VREF=VSENSE OSC=1000mV	90	115	140	ns
OFF TIME
TOFFMIN		Minimum off time					600	ns
		KOSC/TOFFMIN		OSC=250mV	0.20		0.40
VOLTAGE REFERENCE
VREF		Voltage Accuracy		0µA < IREF < 100µA	0.594	0.6	0.606	V
PWM COMPARATOR
		Input voltage offset			-2		+2	mV
IFB		Input Bias Current				20		nA
INTEGRATOR
		Over Voltage Clamp		VSENSE = VCC	0.62	0.75	0.88	V
		Under Voltage Clamp		VSENSE = GND	0.45	0.55	0.65	V
		Integrator Input Offset Voltage			-4		-4	mV
		VSENSE-VREF
IVSENSE		Input Bias Current				20		nA
GATE DRIVERS
		High side rise time		VDR=3.3V; C=7nF		50	90	ns
		High side fall time		HGATE - PHASE from 1 to 3V		50	100	ns
		Low side rise time		VDR=3.3V; C=14nF		50	90	ns
				LGATE from 1 to 3V
		Low side fall time				50	90	ns
PGOOD UVP/OVP PROTECTIONS
OVP		Over voltage threshold		with respect to VREF	118	121	124	%
UVP		Under voltage threshold			67	70	73	%
		Upper threshold		VSENSE rising	110	112	116	%
		(VSENSE-VREF)
		Lower threshold		VSENSE falling	85	88	91	%
		(VSENSE-VREF)
VPGOOD				ISink=2mA		0.2	0.4	V

4/30

Vcc

.4 Figure

SHDN

PGOOD

OVP

overvoltage comparator

VCC

GND

Functional

+

VSENSE

-

1.12 VREF

undervoltage comparator

&

-

VSENSE

+

0.6 VREF

Block

SS

IC enable

S

R

soft-start

pgood comparators

+

1.075 VREF

5 uA

control

-

VSENSE

LS and HS anti-cross-conduction comparators

Diagram

+

VSENSE

V(LGATE)<0.5V

ILIM

comp

VCC

BOOT

power management

-

0.925 VREF

V IN

R

Q

level shifter

HS driver

HGATE

V(PHASE)<0.2V

Toff min

VOUT

positive current limit

S

comp

PHASE

comparator

delay

PHASE

-

+

Ton min

VDR

-

one-shot

0.05

+

LGATE

LS driver

R

Q

Ton

VREF

+

one-shot

PGND

VSENSE

OSC

S

FB

-

pwm comparator

Ton= Kosc V(VSENSE)/V(OSC)

+

Ton

INT

-

S

Q

HS control

Gm

one-shot

-

VREF

+

VSENSE

V IN

VREF

R

OSC

VSENSE

SENSEGND

Ton= Kosc V(VSENSE)/V(OSC)

OSC

no-skip

no-skip

mode

mode

+

PHASE

negative current limit

bandgap

PHASE

+

comparator

1.236V

-

+

-

VREF

-

0.05

ILIM

1.416

0.6V

zero-cross comparator

Reference chain

NOSKIP

LS control

5/30

L6997S

L6997S

4 DEVICE DESCRIPTION

4.1 Constant On Time PWM topology

Figure 5. Loop block schematic diagram

Vin
R1		One-shot generator
	OSC
			FFSR
R2	Vsense		R	Q	HS
					Vout
					HGATE
		Vref	S	Q
					LS
		+			DS
					LGATE
		-
			PWM comparator
		FB
	R4		R3

The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time duration forced by the one-shot generator. The On Time is directly proportional to VSENSE pin voltage and inverse to OSC pin voltage as in Eq1:

T		=	K		VSENSE		+ τ	(1)
	ON			OSC	---------------------
					V	OSC

where KOSC = 180ns and τ is the internal propagation delay time (typ. 40ns). The system imposes in steady state a minimum On Time corresponding to VOSC = 1V. In fact if the VOSC voltage increases above 1V the corresponding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a steady-state switching frequency FSW independent of VIN. It results:

VOUT		1	=	α	OSC	1	→	α OSC = fSW KOSC α OUT (2)
fSW = ---	V-----IN------	----------		-------------- --------------
		TON		α	OUT KOSC
where
α	OSC	=	VOSC		=	R2		(3)
			----V----IN------			-------------
					R2 + R1
α	OUT	=	VFB		=	R4		(4)
			V-----OUT---------			-------------
					R3 + R4

The above equations allow setting the frequency divider ratio α OSC once output voltage has been set; note that such equations hold only if VOSC<1V. Further the Eq2 shows how the system has a switching frequency ideally independent from the input voltage. The delay introduces a light dependence from VIN. A minimum Off-Time constraint of about 500ns is introduced in order to assure the boot capacitor charge and to

6/30

L6997S

limit the switching frequency after a load transient as well as to mask PWM comparator output against noise and spikes.

The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity.

4.2 Closing the loop

The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage (0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4.

The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of DC error. Further the system regulates the output voltage valley value not the average, as shown in Figure 6. So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To compensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal integrator amplifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides an AC path for output ripple.

Figure 6. Valley regulation

Vout

DC Error Offset

<Vout>

Vref

Time

The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance voltage in order to compensate the total static error. A voltage clamp within the device forces anINT pin voltage range (VREF-50mV, VREF+150mV). This is useful to avoid or smooth output voltage overshoot during a load transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak- to-peak amplitude is less than 150mV in steady state.

In case the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and ground to reduce ripple amplitude at INT pin, otherwise the integrator will operate out of its linear range. Choose CINT1 according to the following equation:

CINT1	gINT		α OUT		(5)
	= ----------	---	π-----	---F----u------
	2

where gINT=50 µs is the integrator transconductance, α OUT is the output divider ratio given from Eq4 and FU is

the close loop bandwidth. This equation holds if CINT2 is connected between INT pin and ground. CINT2 is given by:

7/30

L6997S

CINT2	=	∆ VOUT	(6)
C-----INT---------1-		-∆-----V----INT--------

Where ∆ VOUT is the output ripple and ∆ VINT is the required ripple at the INT pin (100mV typ).

Figure 7. Integrator loop block diagram

Vin
R1	One-shot generator				PCB TRACES
OSC
		FFSR
R2		R	Q	HS	Vout
	From Vsense			HGATE
	Vref	S	Q
				LS	LOAD
					DS
		+
FB				LGATE
		-
		PWM comparator
		Vref
		-		Vsense
INT		+
Cint2		-
		+		Gndsense
	Integrator amplifier
	Cint1

Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters. For example, while in a standard fixed switching frequency topology, the increase of the losses (increasing the output current, for example) generates a variation in the On Time and Off Time, in a fixed On Time topology , the increase of the losses generates only a variation on the Off Time, changing the switching frequency. In the device is implemented the voltage feedforward circuit that allows constant switching frequency during steady-sate operation and withinthe input range variation. Any way there are many factors affecting switching frequency accuracy in steady-state operation. Some of these are internal as dead times, which depends on high side MOSFET driver. Others related to the external components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.

During a positive load transient, (the output current increases), the converter switches at its maximum frequency (the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output current decreases), the device stops to switch (high side MOSFET remains off).

4.3 Transition from PWM to PFM/PSK

To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM mode essentially for the off phase; the on phase is the same. In PFM after a On cycle the system turns-on the low side MOSFET until the inductor current goes down zero, when the zero-crossing comparator turns off the low side MOSFET. In PWM mode, after On cycle, the system keeps the low side MOSFET on until the next turnon cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The PFM mode is naturally implemented in an hysteretic controller enabling the zero current comparator by enabling, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down to reference value. The device works in discontinuous mode

8/30

L6997S

at light load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the inductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the transient response is. The PFM waveforms may appear more noisy and asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM is not compatible with the application it can be disabled connecting to VCC the NOSKIP pin.

4.4 Softstart

After the device is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range for the VSS voltage (where the output current limit increase linearly) is from 0.6V to 1V. In this range an internal current source (5 A Typ) charges the capacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5 A (Typ.). When SS voltage is close to 1V the maximum current limit is active. Output protections OVP & UVP are disabled until the SS pin voltage reaches 1V (see figure 8).

Once the SS pin voltage reaches the 1V value, the voltage on SS pin doesn't impact the system operation anymore. If the SHDN pin is turned on before the supplies, the power section must be turned on before the logic section. While if the supplies are applied with the SHND pin off, the start up sequence doesn't meter.

Figure 8. Soft -Start Diagram

	Vss
4.1V
1V
0.6V		Soft-start active range
Ilim	current	Time
5
A
		Maximum current limit
		Time

Because the system implements the soft start by controlling the inductor current, the soft start capacitor should be selected based on of the output capacitance, the current limit and the soft start active range (∆ VSS).

In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before the soft start voltage reaches the under voltage value (1V). After this UVP and OVP are enable.

The time necessary to charge the SS capacitor up to 1V is given by:

T		(C		) =	1V	C		(7)
	SS		SS		-------		SS
					Iss

In order to calculate the output voltage chargin time it should be considered that the inductor current function can be supposed linear function of the time.

IL	(t,CSS) =	(Rilim/Rdson KILIM ISS		t)
		--------------------(---∆---V-----SS--------	---C----SS--------)--------------	------ (8)

9/30