Datasheet L6935 Datasheet (ST)

High performance 3 A ULDO linear regulator

Features

■ Up to 5 V input voltage range

■ 60 mΩ max R

■

35 µA shut-down current

■ 3 A maximum output current

■ Split bias and power supplies

■ Adjustable output voltage: 0.5 V to 3.0 V

■ Excellent load and line regulation: 1 %

accuracy (over temperature)

■ MLCC supported

■ Programmable soft-start

■ Short-circuit protection

■ 3.5 A overcurrent protection

■ Thermal shut-down

■ VFQFPN20 4 x 4 x 1.0 mm package

DS(on)

L6935

VFQFPN20

(4.0 x 4.0 x 1.0 mm)

Description

L6935 is an ultra low drop output linear regulator
operating up to 5 V input and is able to support
output current up to 3 A. Designed with an
internal low-R
be used for on-board DC-DC conversions saving
in real estate, list of components and power
dissipation.

Bias input and power input are split to allow linear
conversion from buses lower than 1.2 V
minimizing power losses.

N-channel MOSFET, it can

DS(on)

Applications

■ Motherboard

■ Mobile PC

■ Hand-held instruments

■ PCMCIA cards

■ Processors I/O

■ Chipset and RAM supply

voltage from 0.5 V to 3.0 V with a voltage
regulation accuracy of 1 %. soft-start is available
to program the output voltage rise-time according
to the external capacitor connected.

Enable and Power Good functions make L6935
suitable for complex systems and programmable
start-up sequencing.

The current limit at 3 A protects the system during
a short circuit. The current is sensed in the power
DMOS in order to limit the power dissipation.
Thermal shut down limits the internal temperature
at 150 °C with a hysteresis of 20 °C.

Table 1. Device summary

L6935 provides the application with an adjustable

Order codes Package Packing

L6935

VFQFPN20

Tu b e

L6935TR Tape and reel

May 2008 Rev 1 1/20

www.st.com

20

Contents L6935

Contents

1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3

1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 VIN vs VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4.1 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 VIN, VBIAS and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8 VFQFPN20 mechanical data and package dimensions . . . . . . . . . . . . 18

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2/20

Typical application circuit and block diagram L6935

1 Typical application circuit and block diagram

1.1 Application circuit

Figure 1. Typical application circuit - VIN = VBIAS

V

EN

IN

VIN

C

IN

EN

VBIAS

L6935

VOUT

ADJ

V

OUT

= 0.5V to 3.0V

R

1

C

OUT

SS GND PGOOD

C

SS

L6935 Reference Schematic

Figure 2. Typical application circuit - VIN

V

BIAS

VIN = 0.75V to V

EN

BIAS

VIN

EN

C

IN

SS GND PGOOD

C

SS

PAD

≠ VBIAS

VBIAS

L6935

PAD

VOUT

ADJ

R

2

PGOOD

V

OUT

> 0.5V (*)

R

1

R

2

C

OUT

PGOOD

L6935 Reference Schematic
(*) Vin may decrease until the minimum drop is reached. Conversely, Vout can rise untile the minimum drop is reached.

3/20

Typical application circuit and block diagram L6935

1.2 Block diagram

Figure 3. Block diagram

VIN

VBIAS

SS

GND

CHARGE

PUMP

VREF

0.9 VREF

+

-

ERROR
AMPLIFIER

+

-

REFERENCE

0.500V

ENABLEEN

THERMAL

SENSOR

CURRENT

DRIVER

LIMIT

VOUT

ADJ

PGOOD

4/20

Pins description and connection diagrams L6935

2 Pins description and connection diagrams

Figure 4. Pins connection (top view)

2.1 Pin descriptions

Table 2. Pins descriptions

Pin # Name Function

1 N.C. Not internally connected.

2 GND Ground connection. Connect to PCB ground plane.

3, 4 N.C. Not internally connected.

N.C.
N.C.
N.C.
N.C.
N.C.

VIN

VIN

VIN

10987

11

12

13

L6935

14

15

16 17 18 19

VOUT

VOUT

EN

VOUT

VBIAS

6

20

SS

ADJ

5

4

3

2

1

PGOOD
N.C.
N.C.
GND
N.C.

Power Good output flag: the pin is open drain and it is forced low if the

5 PGOOD

6 VBIAS

7EN

8 to 10 VIN

11 to15 N.C. Not internally connected.

16 to 18 VOUT

5/20

output voltage is lower than 90 % of the programmed voltage. If not used, it
can be left floating.

Input bias supply. This pin supplies the internal logic to drive the power
N-channel MOSFET that realize the voltage conversion. Connect directly to

or to a different supply ranging from VIN to 5 V.

V

IN

The voltage connected to this pin MUST always be higher or equal that V

Enables the device if a voltage higher than 1 V is applied.
When pulled low, the device is in low-power consumption: everything inside

the controller is kept OFF.
See Section 6.2 for details about EN signal and power sequencing.

Power supply voltage. This pin is connected to the drain of the internal
N-channel MOSFET.
Filter to GND with capacitor larger than the one used for V

Regulated output voltage. This pin is connected to the source of the
internal N-mos. MLCC capacitor are supported. Filter to GND with
capacitor smaller than the one used for V

.

IN

.

OUT

.

IN

Pins description and connection diagrams L6935

Table 2. Pins descriptions (continued)

Pin # Name Function

Feedback for the IC regulation.

19 ADJ

20 SS

PA D G ND

Connecting this pin through a voltage divider to V

, it is possible to

OUT

program the output voltage between 0.5 V and 3.0 V.

Soft-start pin. The soft-start time is programmed connecting an external
capacitor C

from this pin to GND.

SS

In steady state regulation, the voltage at this pin is 3.3 V.

Ground connection. Connect to PCB GND Plane with enough VIAs to
improve thermal conductivity.

6/20

Electrical specifications L6935

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VIN to GND 5.5 V

VBIAS, EN, PGOOD to GND 6 V

SS, VOUT to GND -0.3 to 3.3 V

ADJ to GND -0.3 to 1 V

Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002 “human body model”

acceptance criteria: “normal performance”

3.2 Thermal data

±1000 V

Table 4. Thermal data

Symbol Parameter Value Unit

R

thJA

T

MAX

T

STG

T

J

1. Measured with the component mounted on demonstration board in free air (22 x 28.5 mm - 2 layer 70 µm

copper).

Thermal resistance junction to ambient

Maximum junction temperature 150 °C

Storage temperature range -50 to 150 °C

Junction temperature range -25 to 150 °C

(1)

55 °C/W

7/20

Electrical specifications L6935

3.3 Electrical characteristics

Table 5. Electrical characteristics

(V

= 5 V, V

IN

Symbol Parameter Test conditions Min Typ Max Unit

Recommended operating conditions

= 5 V; TA = 25 °C unless otherwise specified).

BIAS

V

= V

VIN Operating supply voltage

VBIAS UVLO V

IN

V

< 5 V

BIAS

rising 1.275 V

BIAS

Quiescent current Iout = 0 A 2.3 3 mA

I

IN

Shut-down current

= V

V

IN

= V

V

IN

Voltage regulation

VOUT Output voltage Io = 0.1 A; V

ADJ

Line regulation

Vin = 3.30 V +/- 10 %; Io = 10 mA
Vin = 4.50 V +/- 10 %; Io = 10 mA

Load regulation Vin = 3.3 V; Io = 100 mA to 3 A 7 mV

F = 100...120 Hz; Io = 10 mA
Vin = 3 V; ∆Vin = 2 Vpp; Vout = 1 V

R

DS(on)

Ripple rejection

(1)

Drain-to-source resistance Io = 3 A 30 60 mΩ

Enable, SS and protections

I

OCP

PGOOD

Current limiting Vo = 1.8 V 3.15 3.50 3.85 A

Power Good threshold V

falling, wrt Ref. 77 85 %

ADJ

Hysteresis 10 %

Voltage low I = -1 mA 0.4 V

BIAS

= 3.3 V

BIAS

= 5.0 V

BIAS

= 3.3 V; ADJ = OUT 0.496 0.500 0.504 V

IN

45 dB

V

5.0

BIAS

25
40

2.5

2.5

V

µA

mV

EN Enable threshold EN rising 1.05 V

SS Soft start current Vss = 0 V 1.0 µA

OT Thermal shut-down

Hysteresis

1. Parameter guaranteed by design, not tested in production

(1)

Temperature rising

(1)

150 °C

20 °C

8/20

Typical performances L6935

]

]

]

]

4 Typical performances

Figure 5. Output voltage and OC threshold vs junction temperature

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

Output Voltage [%]

-0.4

-0.6

-0.8

-1.0

-40 -20 0 20 40 60 80 100 120 140
Temperat u r e [ ° C]

Figure 6. Quiescent and shutdown current vs junction temperature

4.0

3.8

3.6

3.4

OC Threshold [A

3.2

3.0

-40 -20 0 20 40 60 80 100 120 140
Temperature [°C]

4.0

3.8

3.6

3.4

Quiescent Current [mA

3.2

3.0

-40-200 20406080100120140
Temperature [°C]

Figure 7. Line regulation

0.2%

VBIAS = VIN, VOUT = 0.5V

0.1%

0.0%

Line Regulation [%

-0.1%

-0.2%

1.01.52.02.53.03.54.04.55.0
V

[V]

IN

40
35

5 VIN

30
25
20
15

Shutdown Current [uA

Line Regulation [%

3 VIN

10

5
0

-40 -20 0 20 40 60 80 100 120 140

0.2%

0.1%

0.0%

-0.1%

-0.2%

2.0 2.5 3.0 3.5 4.0 4.5 5.0

Temperature [°C]

VBIAS = 1.4V, VOUT = 2V

V

[V]

IN

9/20

Typical performances L6935

]

]

Figure 8. Load regulation

Load Regulation [%

0.3%

0.2%

0.1%

0.0%

-0.1%

-0.2%

-0.3%

VBIAS = 1.4V, VIN = 2. 6V, VOUT = 2V

0.0 0.5 1.0 1.5 2.0 2.5

Output Current [A]

0.3%

0.2%

0.1%

0.0%

-0.1%

Load Regulation [%

-0.2%

-0.3%

0.0 0.5 1.0 1.5 2.0 2.5

VBIAS = VIN = 1.4V, VOUT = 0.5V

Output Current [A]

10/20

Device description L6935

5 Device description

5.1 Soft-start

L6935 implements a soft-start feature to smoothly charge the output filter avoiding high in­rush currents to be required to the input power supply.

The soft-start process begins as soon as V
A constant current I
capacitor (C

) to this pin a voltage ramp is implemented; the voltage ramp internally

SS

= 1.0 µA is sourced through the SS pin: connecting an external

SS

reaches UVLO and ENABLE is asserted.

BIAS

clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the
voltage on C

reaches the V

SS

value the internal clamp is released.

REF

In this way, the soft-start process lasts for:

where C

V

REF

------------- -

T

SS

is the external capacitor [F] and TSS is the soft-start time [sec.].

SS

⋅ 510

C

SS

I

SS

5

CSSF[]⋅⋅==

If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped
to GND for a fixed time of about 50 µs. in order to discharge the residual charge present on
C

: in this way, the device will be ready for a new SS process as ENABLE is asserted

SS

again.

Figure 9 describes a typical soft-start process.

Figure 9. Soft start process diagram (left) and measured (right)

Vbias

>1.1V

ENABLE

ADJ

Vout

~50µsec

Programmed Tss

>0.7V

0.5V

Programmed Vout

11/20

Device description L6935

5.2 Power Good

L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft
start procedure, and is left free when V

An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise
generated by the application. Figure 10 shows the PGOOD commutations.

Figure 10. Power good window

reaches 90 % of the programmed value.

OUT

5.3 VIN vs V

BIAS

L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than
the power input (VIN). The aim of this feature is to provide low-drop regulation still having
the supply voltage to correctly drive the internal power mosfet so optimizing the conversion.
VIN drives only the drain of the power DMOS and it can be kept as low as possible
(V

> V

IN

higher than V

OUT

+ V

IN

DROPmin

.

), while V

5.4 Protections

L6935 is equipped with a set of protections in order to protect both the load and the device
from electrical overstress. Each protection does not latch the device, that returns to work
properly as the perturbation disappear.

5.4.1 Over-current protection

An over current protection is provided: if the current that flows through the power DMOS is
greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep
constant the delivered current (I
PGOOD to be set low.

Figure 11 show the way the OCP intervention: as the threshold value is reached by I

device forces a lower output current (~3.5 A).

drives the control section. V

BIAS

). Anyhow the output may drop also causing the

OUT

must be typically

BIAS

OUT

, the

12/20

Device description L6935

Figure 11. Over-current protection

5.4.2 Thermal protection

The device constantly monitors its internal temperature. As the silicon reaches a 150 °C, the
control circuit turns off the power DMOS, and stays off until a safe temperature of
150° - 20° = 130 °C. Figure 12 shows how the over-temperature protection intervention.

Figure 12. Over-temperature protection

13/20

Application information L6935

6 Application information

L6935 is the best choice in smart linear regulator applications, due to its own small size,
high power delivered and high regulation accuracy. Furthermore thermal shut-down and
OCP guarantee the highest reliability for each application.

V

can be separated by V

IN

V

< V

IN

V

get lower, according to the relationship P

IN

, resulting in a better performance. In fact, the power dissipated decreases as

BIAS

6.1 Components selection

6.1.1 Input capacitor

The choice of the input capacitor value depends on the several factor such as load transient
requirements, input source (battery or DC/DC converter) and its distance from the input
capacitor. Generally speaking, a capacitor with the lowest ESR possible should be chosen:
a value within the range [10 µF; 100 µF] can be sufficient in many cases.

6.1.2 Output capacitor

: in this way the device can regulate the output voltage even if

BIAS

= (VIN - V

DISS

OUT

) x I

OUT

.

The choice of the output capacitor value basically depends on the load transient
requirement. Output capacitor must be sized according to the dynamic requests of the load.
A too small capacitor may exhibit huge voltage drop after a load transient is applied: a value
greater than 10 µF should be used.

In order to guarantee a good reliability, at least X5R type should be used as I/O capacitors.

Different kinds of input/output capacitors can be used: Table 6. shows a few tested
examples.

Table 6. Input/output capacitor selection guide

Manufacturer Type I/O cap. value Rated voltage

Murata - GRM31CR61ExxxK

Panasonic - ECJ3YB1AxxxM MLCC, SMD1206, X5R 10...100 µF 10 - 25 V

Panasonic - EEFFD0HxxxR

Sanyo - 8TPE100MPC2

TDK - C3216X5R0JxxxMT MLCC, SMD1210, X5R 10...100 µF 6.3 V

1. xxx in the part numbers stands for 106 (10 µF), 226 (22 µF)... 105 (100 µF)

(1)

MLCC, SMD1206, X5R 10...100 µF 6.3 - 25 V

SPCap - SMD7343

28 mΩ ESR

POSCAP, SMD6032

25 mΩ ESR

10...100 µF4 - 8 V

10...100 µF 6.3 - 25 V

14/20

Application information L6935

6.2 VIN, VBIAS and sequencing

Different configurations for VIN and VBIAS are possibleand the power sequencing must
consider the different timings in which the power suppliesbecomes available. In order to
properly drive the device internal logic, it is reccomendedto control the sequence between
EN signal and the VIN / VBIAS application: the device need to result being disabled when
VBIAS crosses the UVLO threshols. Furthermore, in case of VIN <> VBIAS, the EN signal
needs to be driven by the last-coming between the two supplies.

It is reccomended to drive the EN pin with a resistor divider connected as reported into

Figure 13 and Figure 14.

Figure 13. Recommended circuit for VBIAS = VIN

VIN

VIN

R

CIN COUT

EN

(OpenDrain Toggle **)

** Drive EN with external Open-Drain Signal.

EH

EN

R

EL

VBIAS

L6935

SS GND ADJ

CSS

PAD

Figure 14. Reccomended circuit for VBIAS

VBIAS

VIN (< VBIAS)

C

IN

(OpenDrain Toggle **)

EN

*

EH

R

VIN

EN

R

EL

VBIAS

L6935

SS GND ADJ

C

SS

VOUT

PGOOD

≠ VIN

PGOOD

PAD

VOUT

VOUT = 0.5V to 3.0V

R

1

R

2

R

1

R

2

R

PG

PGOOD

VOUT = 0.5V to 3.0V

R

PG

C

OUT

PGOOD

* EN Divider (REH) needs to be connected to the Last-Coming rail between VCC and VIN.

** Drive EN with external Open-Drain Signal.

15/20

Demonstration board description L6935

7 Demonstration board description

Figure 15 and Figure 16 show the schematic and the layout of the demonstration board

designed for L6935. V
mounted. C3 defines the Soft-Start timer, according to the relationship described in the

Section 5.1.

and V

IN

may be different and, in this case, R4 must not be

BIAS

The value of the output divider R
V

value, according to the following equation:

OUT

/ R2 have to be designed in order to program the desired

1

V

OUT

0.5= 1

Figure 15. Demonstration board schematic

V

BIAS

R

V

EN

4

IN

C

4

C

2

R

C

1

5

8, 9, 10

7

C

3

VIN

EN

SS GND

20

2

6

VBIAS

L6935

PAD

16,17,18

R

1

⎛⎞

------ -+

⋅

⎝⎠

R

2

VOUT

PGOOD

5

19

ADJ

R

3

PGOOD

ADJ

V

OUT

R

C

6

1

C

5

R

2

GND

Figure 16. Demonstration board layout

16/20

Demonstration board description L6935

Different values for R1 are available in order to program the value of V

V

= 0.50 VDC @ R1 = 0 Ω

OUT

V

= 0.75 VDC @ R1 = 5 kΩ

OUT

V

= 1.00 VDC @ R1 = 10 kΩ

OUT

V

= 1.25 VDC @ R1 = 15 kΩ

OUT

V

= 1.50 VDC @ R1 = 20 kΩ

OUT

V

= 3.00 VDC @ R1 = 50 kΩ

OUT

Table 7. L6935 demonstration board bill of material

Reference Description

C1, C2, c3 Chip capacitor 100 nF - 6.3 V - X5R

C4 Murata chip capacitor (GRM31CR60J226K) 1206, X5R, 6.3-25V, 22 µF

C5 Murata chip capacitor (GRM31CR61E106K) 1206, X5R, 6.3-25V, 10 µF

C6 Not mounted

R1 Chip resistor 15

R2 Chip resistor 10

R3, R5 Chip resistor 10

kΩ +/-0.1% - 1/16 W
kΩ +/-0.1% - 1/16 W
kΩ +/-5% - 1/16 W

(R2 = 10 kΩ)

OUT

R4 Chip resistor 0

Ω

17/20

VFQFPN20 mechanical data and package dimensions L6935

8 VFQFPN20 mechanical data and package dimensions

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Figure 17. VFQFPN20 mechanical data and package dimensions

DIMENSIONS

REF.

A 0.80 0.90 1.00 31.496 35.433 39.370

A1 0.02 0.05

A2 0.65

A3 0.25

b 0.18 0.23 0.30

D 4.0 0

D2 2.70 2.8 0 2.90

E

E2

e0.50

L 0.3 0.4 0.5

ddd

mm mils

MIN. TYP. MAX. MIN. TYP. MAX.

0.787 1.969

25.591 39.370

1.00

9.843

7.087 9.055 11.811

151.57 157.48 163.39

4.153.85

106.30 110.24 114.17

4.00

2.70 2.80 2.90

0.45

151.57 157.48 163.39

4.153.85

106.30 110.24 114.17

17.717 19.685 21.654

0.55

11.811 15.748 19.685

3.150

0.08

PACKAGE AND

PACKING INFORMATION

Very Fine Quad Flat

Package No lead

Weight: not available

VFQFPN20 (4x4x1.00mm)

18/20

Revision history L6935

9 Revision history

Table 8. Document revision history

Date Revision Changes

20-May-2008 1 Initial release

19/20

L6935

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