High performance 2A ULDO linear regulator
Features
■ 2V to 14V input voltage range
■ 200mΩ r
■ 200µA quiescent current at any load
■ Excellent load and line regulation
■ Adjustable from 1.2V to 5V
■ 1% voltage regulation accuracy
■ Short circuit protection
■ Thermal shut down
■ HSOP8 package
Applications
■ Motherboards
■ Mobile PC
■ Hand-held instruments
■ PCMCIA Cards
■ Processors I/O
■ Chipset and RAM supply
Figure 1. Typical operating circuit
Vin=2V to 14V
Vin=2V to 14V
DS(on)
max
C1
C1
Vin Vout
Vin Vout
2
2
EN
EN
1
1
GND
GND
L6932H1.2
L6932H1.2
7
7
6
6
L6932H1.2
HSO-8
Description
The L6932 Ultra Low Drop Output linear regulator
operates from 2V to 14V and is able to support
output current up to 2A. Designed with an internal
50mΩ N-channel Mosfet, it can be used for
onboard DC-DC conversions saving in real
estate, list of components, low noise generation
and power dissipation.
L6932H1.2 is available as adjustable version from
1.2V to 5V with a voltage regulation accuracy of
1%.
The upper current limit is fixed at 2.5A to control
the current in short circuit condition within ±8%.
The current is sensed in the power mos in order
to limit the power dissipation.
The device is also provided with a thermal shut
down that limits the internal temperature at 150°C
with a histeresys of 20°C. L6932H1.2 provides the
Enable and the Power good functions
4
4
R3
R3
PGOOD
PGOOD
5
5
FB
FB
3
3
8
8
NC2NC1
NC2NC1
R1
R1
R2
R2
Vout=1.2V to 5 V
Vout=1.2V to 5 V
.
C2
C2
Table 1. Device summary
Part number Package Packaging
L6932H1.2 HSO-8 Tube
L6932H1.2TR HSO-8 Tape and reel
May 2007 Rev 2 1/13
www.st.com
13
Contents L6932H1.2
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Application informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Demoboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.3 Component part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.3 Loop Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
L6932H1.2 Pin settings
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
NC2
EN
EN
1
1
8
8
NC2
1.2 Pin description
Table 2. Pin description
Name Pin N° Description
1 EN Enables the device when connected to Vin and disables it when forced to GND.
2 VIN
3FB
4VOUT
5 PGOOD
Supply voltage. This pin is connected to the drain of the internal N-mos.
Connect this pin to a capacitor larger than 10µF.
Connecting this pin to a voltage divider it is possible to program the output
voltage between 1.2V and 5V.
Regulated output voltage. This pin is connected to the source of the internal Nmos. Connect this pin to a capacitor of 10µF.
Power good output. The pin is open drain and detects the output voltage. It is
forced low if the output voltage is lower than 90% of the programmed voltage.
Vin
Vin
FB
FB
Vout
Vout
NC1
2
2
3
3
4
4
7
7
6
6
5
5
NC1
GND
GND
PGOOD
PGOOD
6 GND Ground pin
7, 8
NC1-
NC2
Internally not connected.
3/13
Maximum ratings L6932H1.2
2 Maximum ratings
2.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
IN
2.2 Thermal data
Table 4. Thermal data
Symbol Parameter Value Unit
R
thJA
T
MAX
T
STG
1. Package mounted on board
VIN and PGOOD 14.5 V
EN, OUT and ADJ -0.3 to (Vin +0.3) V
Maximum thermal resistance junction-ambient
Maximum junction temperature 150 °C
Storage temperature range -65 to 150 °C
34
(1)
°C/W
3 Block diagram
Figure 3. Internal block diagram
4/13
L6932H1.2 Electrical characteristics
4 Electrical characteristics
Table 5. Electrical characteristcs (TJ = 25°C, VIN = 5V unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Operating Supply
V
IN
Voltage
= 0.1A; VIN = 3.3V
V
r
DS(on)
I
OCC
Output voltage
O
Line Regulation
Load Regulation
Drain Source ON
resistance
Current limiting 2.3 2.5 2.7 A
I
O
V
= 2.5V ±10%; IO = 10mA
IN
V
= 3.3V ±10%; IO = 10mA
IN
V
= 5V ±10%; IO = 10mA
IN
= 3.3V; 0.1A < IO < 2A
V
IN
Iq Quiescent current 0.2 0.4 mA
Ish Shutdown current
Ripple Rejection
2V < V
IN
f = 120Hz, I
= 2Vpp
∆V
IN
(1)
< 14V
= 1A VIN = 5V,
O
Ven EN Input Threshold 0.5 0.65 0.8 V
Pgood threshold Vo rise 90 %Vo
Pgood Hysteresis 10 %Vo
214V
1.188 1.2 1.212 V
5mV
5mV
5mV
15 mV
200 mΩ
25 µA
60 75 dB
Pgood saturation Ipgood = 1mA 0.2 0.4 V
1. Specification referred to T from -25°C to 125°C.
5/13
Typical electrical performance L6932H1.2
5 Typical electrical performance
Figure 4. Output voltage vs
junction temperature
Figure 6. Shutdown current vs
junction temperature
Figure 5. Quiescent current vs
junction temperature
6/13
L6932H1.2 Application information
6 Application information
6.1 Application circuit
Figure 7. Demoboard application circuit
Vout=1.2V to 5V
Vout=1.2V to 5V
Vin=2V to 14V
Vin=2V to 14V
Vin=2V to 14V
Vin Vout
Vin Vout
Vin Vout
2
2
2
EN
EN
EN
C1
C1
C1
L6932H1.2
L6932H1.2
L6932H1.2
1
1
1
6
6
6
GND
GND
GND
V
OUT
7
7
7
1.2
------- -
R
4
4
4
R3
R3
R3
PGOOD
PGOOD
PGOOD
5
5
5
FB
FB
FB
3
3
3
8
8
8
NC2NC1
NC2NC1
NC2NC1
+()×=
R
1R2
2
R1
R1
R1
R2
R2
R2
Vout=1.2V to 5V
C2
C2
C2
6.2 Demoboard layout
Figure 8. Demoboard layout
7/13
Components selection L6932H1.2
6.3 Component part list
Table 6. Component par list
Reference Part number Description Manufacturer
C1 GRM32ER6C226KE20B 22Uf, 16V MURATA
C2 GRM32ER6C226KE20B 22Uf, 16V MURATA
R1 N.M.
R2 0Ω
R3 100K
7 Components selection
7.1 Input capacitor
The input capacitor value depends on a lot of factors such as load transient requirements,
input source (battery or DC/DC converter) and its distance from the input cap. Usually a
47µF is enough for any application but a much lower value can be sufficient in many cases.
7.2 Output capacitor
The output capacitor choice depends basically on the load transient requirements.
Tantalum, Special Polymer, POSCAP and aluminum capacitors are good and offer very low
ESR values. Multilayer ceramic caps have the lowest ESR and can be required for
particular applications. Nevertheless in several applications they are ok, the loop stability
issue has to be considered (see loop stability section).
Below a list of some suggested capacitor manufacturers
Table 7. Suggested capacitor
Manufacturer Type Cap Value (µF) Rated Voltage (V)
MURATA CERAMIC 1 to 47 4 to 16
PANASONIC CERAMIC 1 to 47 4 to 16
TAYO YUDEN CERAMIC 1 to 47 4 to 16
TDK CERAMIC 1 to 47 4 to 16
TOKIN CERAMIC 1 to 47 4 to 16
SANYO POSCAP 1 to 47 4 to 16
PANASONIC SP 1 to 47 4 to 16
KEMET TANTALUM 1 to 47 4 to 16
8/13
L6932H1.2 Components selection
7.3 Loop Stability
The stability of the loop is affected by the zero introduced by the output capacitor. The time
constant of the zero is given by:
T ESR C
F
ZERP
×=
OUT
-----------------------------------------------=
2π ESR C
1
××
OUT
This zero helps to increase the phase margin of the loop until the time constant is higher
than some hundreds of nsec, depending also on the output voltage and current.
So, using very low ESR ceramic capacitors could produce oscillations at the output, in
particular when regulating high output voltages (adjustable version).
To solve this issue is sufficient to add a small capacitor (e.g. 1nF to 10nF) in parallel to the
high side resistor of the external divider, as shown in Figure 9.
Figure 9. Compensation network
Vout=1.2 V to 5VVin=2V to 14V
Vin Vout
Vin Vout
2
2
EN
EN
C1
C1
L6932H1.2
L6932H1.2
1
1
6
6
GND
GND
7
7
4
4
R3
R3
PGOOD
PGOOD
5
5
FB
FB
3
3
8
8
NC2NC1
NC2NC1
R1
R1
R2
R2
Vout=1.2 V to 5VVin=2V to 14V
C3
C3
C2
C2
The thermal resistance junction to ambient of the demoboard is approximately 34°C/W.
This mean that, considering an ambient temperature of 60°C and, a maximum junction
temperature of 150°C, the maximum power that the device can handle is 2.7W.
This means that the device is able to deliver a DC output current of 2A only with a very low
dropout.
9/13
Package mechanical data L6932H1.2
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
10/13
L6932H1.2 Package mechanical data
Table 8. HSO-8 Mechanical data
Dim.
mm. inch
Min Typ Max Min Typ Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.04 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 3.1 0.122
E 3.80 4.00 0.150 0.157
E1 2.4 0.094
e 1.27 0.050
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
k 8° (max.)
ddd 0.1 0.04
Figure 10. Package dimensions
11/13
Revision history L6932H1.2
9 Revision history
Table 9. Revision history
Date Revision Changes
23-Jun-2006 1 First release
07-May-2007 2 Final release, mechanical data pad size updated
12/13
L6932H1.2
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