ST L6910G User Manual
L6910G
Fi
ADJUSTABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
1 FEATURES
■ OPERATING SUPPLY VOLTAGE FROM 5V
TO 12V BUSES
■ UP TO 1.3A GATE CURRENT CAPABILITY
■ ADJUSTABLE OUTPUT VOLTAGE
■ N-INVERTING E/A INPUT AVAILABLE
■
0.9V ±1.5% VOLTAGE REFERENCE
■ VOLTAGE MODE PWM CONTROL
■ VERY FAST LOAD TRANSIENT RESPONSE
■ 0% TO 100% DUTY CYCLE
■ POWER GOOD OUTPUT
■ OVERVOLTAGE PROTECTION
■ HICCUP OVERCURRENT PROTECTION
■ 200kHz INTERNAL OSCILLATOR
■ OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50kHz TO 1MHz
■ SOFT START AND INHIBIT
■ PACKAGE: SO-16
2 APPLICATIONS
■ SUPPLY FOR MEMORIES AND TERMI-
NATIONS
■ COMPUTER ADD-ON CARDS
■ LOW VOLTAGE DISTRIBUTED DC-DC
■ MAG-AMP REPLACEMENT
3 DESCRIPTION
The device is a pwm controller for high performance
gure 1. Packages
SO-16 (Narrow)
Table 1. Order Codes
Part Number Package
L6910G SO-16
L6910GTR SO-16 in Tape & Reel
dc-dc conversion from 3.3V, 5V and 12V buses.
The output voltage is adjustable down to 0.9V;
higher voltages can be obtained with an external
voltage divider.
High peak current gate drivers provide for fast switching to the external power section, and the output
current can be in excess of 20A.
The device assures protections against load overcurrent and overvoltage.
An internal crowbar is also provided turning on the
low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in
HICCUP mode.
Figure 2. Block Diagram
R
T
May 2005
PGOOD
VREF
OSC
EAREF
SS
D03IN1509
VCC OCSET
PROTECTION
E/A
+
-
300K
COMP
MONITOR
& REF
OSC
PWM
-
+
BOOT
UGATE
PHASE
LGATE
PGND
GND
VFB
Vin 5V to 12V
V
O
Rev. 1
1/26
L6910G
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
Vcc Vcc to GND, PGND 15 V
V
BOOT-VPHASE
V
HGATE-VPHASE
T
j
T
stg
P
tot
OCSET PIN Maximum Withstanding Voltage Range
OTHER PINS ±2000 V
Table 3. Thermal Data
Symbol Parameter Value Unit
Boot Voltage 15 V
15 V
OCSET, LGATE, PHASE -0.3 to Vcc+0.3 V
SS, FB, PGOOD, VREF, EAREF, RT 7 V
COMP 6.5 V
Junction Temperature Range -40 to 150 °C
Storage temperature range -40 to 150 °C
Maximum power dissipation at Tamb = 25°C1W
±1000 V
Test Condition: CDF-AEC-Q100-002”Human Body Model”
Acceptance Criteria: “Normal Performance”
R
th j-amb
(*) Device soldered on 1 S2P PC board
Thermal Resistance Junction to Ambient 120 °C/W
Figure 3. Pins Connection (Top view)
VREF
OSC
OCSET
SS/INH
COMP
FB
GND
EAREF PGOOD
2
3
4
5
6
7
8
D03IN1510
16
15
14
13
12
11
10
N.C.1
VCC
LGATE
PGND
BOOT
HGATE
PHASE
9
2/26
L6910G
Table 4. Pins Function
Pin Name Description
1 VREF Internal 0.9V ±1.5% reference is available for external regulators or for the internal error amplifier
2 OSC Oscillator switching frequency pin. Connecting an external resistor (R
3 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
4 SS/INH The soft start time is programmed connecting an external capacitor from this pin and GND. The
5 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control
6 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage
7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to 3V) for
9
PGOOD
10 PHASE
11 HGATE High side gate driver output.
12 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
13 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
14 LGATE This pin is the lower mosfet gate driver output
15 VCC Device supply voltage. The operative supply voltage ranges is from 5V to 12V.
16 N.C. This pin is not internally bonded. It may be left floating or connected to GND.
(connecting this pin to EAREF) if external reference is not available.
A minimum 1nF capacitor is required.
If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.
) from this pin to GND, the
T
external frequency is increased according to the equation:
6
⋅
4.94 10
f
OSC,RT
200K H z
-------------------------+=
R
KΩ()
T
Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
7
⋅
4.306 10
f
OSC,RT
200K H z
-----------------------------–=
R
T
KΩ()
If the pin is not connected, the switching frequency is 200KHz.
The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in oscillator
stops to switch.
In Over Voltage condition this pin goes over 3V until that conditon is removed.
The internal 200µA current generator sinks a constant current through the external resistor. The
Over-Current threshold is due to the following equation:
I
I
----------------------------------------------=
P
⋅
OCSETROCSET
R
DSon
internal current generator forces through the capacitor 10µA.
This pin can be used to disable the device forcing a voltage lower than 0.4V
feedback loop.
control feedback loop.
Connected to the output resistor divider, if used, or directly to Vout, it manages also over-voltage
conditions and the PGOOD signal
the PWM regulation or short it to VREF pin to use the internal reference.
If this pin goes under 650mV (typ), the device shuts down.
This pin is an open collector output and it is pulled low if the output voltage is not within the above
specified thresholds. If not used it may be left floating.
This pin is connected to the source of the upper mosfet and provides the return path for the high side
driver. This pin monitors the drop across the upper mosfet for the current limit together with OCSET.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot).
VBOOT limited to VOCSET -10V(typ.) when all other pins are connected to GND.
reduce the noise injection into the device
DO NOT CONNECT V
TO A VOLTAGE GREATER THAN VCC.
IN
3/26
L6910G
Table 5. Electrical Characteristics (Vcc = 12V, TJ =25°C unless otherwise specified)
Symbol Parameter Test Condition Min Typ Max Unit
SUPPLY CURRENT
V
cc
Icc Vcc Supply current OSC = open; SS to GND 4 7 9 mA
POWER-ON
Turn-On Vcc threshold VOCSET = 4V 4.0 4.3 4.6 V
Turn-Off Vcc threshold VOCSET = 4V 3.8 4.1 4.4 V
Rising V
Turn On EAREF threshold VOCSET = 4V 650 750 mV
SOFT START AND INHIBIT
Iss Soft start Current
S.S. current in INH condition
OSCILLATOR
f
OSC
f
OSC,RT
Initial Accuracy OSC = OPEN
Total Accuracy 16 KΩ < RT to GND < 200 KΩ -15 15 %
∆Vosc Ramp amplitude 1.9 V
REFERENCE
V
V
V
Output Voltage Accuracy V
OUT
Reference Voltage C
REF
Reference Voltage C
REF
ERROR AMPLIFIER
I
EAREF
N.I. bias current V
EAREF Input Resistance Vs. GND 300 kΩ
I
V
V
COMP
G
I.I. bias current VFB = 0V to 3V 0.01 0.5 µA
FB
Common Mode Voltage 0.8 3 V
CM
Output Voltage 0.5 4 V
Open Loop Voltage Gain 70 85 dB
V
GBWP Gain-Bandwidth Product 10 MHz
SR Slew-Rate COMP = 10pF 10 V/µs
GATE DRIVERS
I
HGATE
High Side
Source Current
R
HGATE
High Side
Sink Resistance
I
LGATE
R
LGATE
Low Side Source Current Vcc = 12V; V
Low Side Sink Resistance Vcc = 12V 1.5 3 Ω
Output Driver Dead Time PHASE connected to GND 90 210 ns
PROTECTIONS
I
OCSET
OCSET Current Source V
Over Voltage Trip (V
I
OSC
OSC Sourcing Current V
POWER GOOD
Upper Threshold (V
Lower Threshold (V
Hysteresis (V
V
PGOOD
I
PGOOD
PGOOD Voltage Low I
Output Leakage Current V
threshold 1.24 1.4 V
OCSET
SS = 2V
6103514
SS = 0 to 0.4V
FB
/ V
180
OSC = OPEN; T
= VFB; V
OUT
= 1nF; I
REF
= 1nF; TJ = 0 to 125°C-2 +2%
REF
= 3V 10 µA
EAREF
V
- V
BOOT
- V
V
HGATE
V
- V
BOOT
= 4V 170 200 230 µA
OCSET
/ V
FB
/ V
FB
/ V
FB
EAREF
)VFB Rising 117 120 %
EAREF
> OVP Trip 15 30 mA
FB
)VFB Rising 108 110 112 %
EAREF
)VFB Falling 88 90 92 %
EAREF
) Upper and Lower threshold 2 %
= -4mA 0.4 V
PGOOD
= 6V 0.2 1 µA
PGOOD
= 0° to 125°
j
= V
EAREF
REF
PHASE
PHASE
= 12V 2 4 Ω
PHASE
LGATE
REF
= 0 to 100µA 0.886 0.900 0.913 V
= 12V
= 6V
= 6V 0.9 1.1 A
170
0.886 0.900 0.913 V
11.3 A
200 220
60
230
µA
µA
KHz
kHz
4/26
L6910G
4 DEVICE DESCRIPTION
The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N
Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be
precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is
used (simply connecting together EAREF and VREF pins). The device allows also using an external
reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient
response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V
high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to
100%. The device protects against over-current conditions entering in HICCUP mode. The device
monitors the current by using the
r
DS(ON)
of the upper MOSFET(s) that eliminates the need for a cur-
rent sensing resistor. The device is available in SO16 narrow package.
4.1 Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50
OSC pin and GND or V
µ
A (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between
. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-
CC
ied proportionally to the current sunk (forced) from (into) the pin.
In particular connecting R
vs. GND the frequency is increased (current is sunk from the pin), according to the
T
following relationship:
4.94 10
-------------------------+=
R
Connecting R
f
OSC,RT
to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according
T
200KHz
to the following relationships:
f
OSC,RT
200KHz
4.306 10
-----------------------------–=
R
⋅
KΩ()
T
7
/µs
slew rate that permits to realize
6
⋅
K
Ω()
T
V
CC
= 12V
15 10
f
OSC,RT
200KHz
---------------------–=
R
T
Switching frequency variation vs. RT are repeated in Fig. 4.
Note that forcing a 50
µ
A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 4.
10000
1000
100
Resistance [kOhm]
10
10 100 1000
RT to GND
RT to VCC=12V
RT to VCC=5V
Frequency [kHz]
6
⋅
KΩ()
= 5V
V
CC
5/26
L6910G
4.2 Reference
A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid
instability in the internal linear regulator. It is able to deliver up to 100
device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed.
Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting
input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this
pin can range from 0.9V to 3V. It has an internal pull-down (300k
no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is
lower than 650mV (typ).
4.3 Soft Start
At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial
value for this current is of 35
10
µ
A until the final charge value of approximatively 4V.
When the voltage across the soft start capacitor (V
charge the output capacitor. As V
µ
A and speeds-up the charge of the capacitor up to 0.5V. After that it becames
) reaches 0.5V the lower power MOS is turned on to dis-
reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper
SS
SS
MOS begins to switch and the output voltage starts to increase.
No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.
If VCC and OCSET pins are not above their own turn-on thresholds and V
Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any undervoltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor
is rapidly discharged.
µ
A and may be used as reference for the
Ω
resistor) that forces the device shutdown if
is not above 650mV, the Soft-
EAREF
Figure 5. Soft Start (with Reference Present)
Vcc
Vin
Vss
LGATE
Vout
to GND
Vcc Turn-on threshold
Vin Turn-on threshold
1V
Timing Diagram
0.5V
Acquisition: CH1 = PHASE; CH2 = V
CH3 = PGOOD; CH4 = V
ss
out
;
4.4 Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the R
), maintaining fast switching transition.
DSON
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
6/26
L6910G
avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the
high side turn-off.
The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ V
current is 1.3A @ V
= 12V and 500mA @ VCC = 5V.
CC
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
= 12V and 500mA @ VCC = 5V, and the sink peak
CC
CH1 = High Side Gate CH4 = Gate Current
Figure 7. Low Side Driver Peak Current. VCC = 12V (right) VCC = 5V (left)
CH1 = Low Side Gate CH4 = Gate Current
4.5 Monitoring and Protections
The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the
powergood output is forced low.
The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)
greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the
over-voltage is detected.
7/26
L6910G
µ
µ
µ
Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the
R
, with the voltage across the external resistor (R
DSON
upper MOS. Thus the overcurrent threshold (I
Where the typical value of I
R
(also the variation with temperature) and the minimum value of I
dsON
is 200µA. To calculate the R
OCS
) can be calculated with the following relationship:
P
I
P
overcurrent protection this relationship must be satisfied:
I
PIOUTMAX
∆
Where
I is the inductance ripple current and I
OUTMAX
In case of over current detectionthe soft start capacitor is discharged with constant current (10
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 8. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 8. Hiccup Mode Figure 9. Inductor Ripple Current vs. Vout
) connected between the OCSET pin and drain of the
OCS
R
⋅
OCSIOCS
---------------------------------=
R
dsON
value it must be considered the maximum
I∆
=
-----+≥ I
2
OCS
PEAK
. To avoid undesirable trigger of
OCS
is the maximum output current.
µ
A typ.) and when
CH1 = SS; CH4 = Inductor current
9
8
7
6
5
4
3
2
Inductor Ripple [A]
1
0
0.5 1.5 2.5 3.5
Output V oltage [V]
L=1.5
H, Vin=12V
H, Vin=5V
L=3
L=2µH,
Vin=12V
L=3µH,
Vin=12V
L=1.5
Vin=5V
L=2µH,
Vin=5V
H,
4.6 Inductor Design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
∆
IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
V
–
INVOUT
L
------------------------------
f
swIL
Where f
is the switching frequency, VIN is the input voltage and V
SW
the ripple current vs. the output voltage for different values of the inductor, with V
V
OUT
---------------⋅=
∆⋅
V
IN
is the output voltage. Figure 9 shows
OUT
= 5V and VIN = 12V.
IN
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
8/26
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