L6910G
Fi
ADJUSTABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
1 FEATURES
■ OPERATING SUPPLY VOLTAGE FROM 5V
TO 12V BUSES
■ UP TO 1.3A GATE CURRENT CAPABILITY
■ ADJUSTABLE OUTPUT VOLTAGE
■ N-INVERTING E/A INPUT AVAILABLE
■
0.9V ±1.5% VOLTAGE REFERENCE
■ VOLTAGE MODE PWM CONTROL
■ VERY FAST LOAD TRANSIENT RESPONSE
■ 0% TO 100% DUTY CYCLE
■ POWER GOOD OUTPUT
■ OVERVOLTAGE PROTECTION
■ HICCUP OVERCURRENT PROTECTION
■ 200kHz INTERNAL OSCILLATOR
■ OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50kHz TO 1MHz
■ SOFT START AND INHIBIT
■ PACKAGE: SO-16
2 APPLICATIONS
■ SUPPLY FOR MEMORIES AND TERMI-
NATIONS
■ COMPUTER ADD-ON CARDS
■ LOW VOLTAGE DISTRIBUTED DC-DC
■ MAG-AMP REPLACEMENT
3 DESCRIPTION
The device is a pwm controller for high performance
gure 1. Packages
SO-16 (Narrow)
Table 1. Order Codes
Part Number Package
L6910G SO-16
L6910GTR SO-16 in Tape & Reel
dc-dc conversion from 3.3V, 5V and 12V buses.
The output voltage is adjustable down to 0.9V;
higher voltages can be obtained with an external
voltage divider.
High peak current gate drivers provide for fast switching to the external power section, and the output
current can be in excess of 20A.
The device assures protections against load overcurrent and overvoltage.
An internal crowbar is also provided turning on the
low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged and the system works in
HICCUP mode.
Figure 2. Block Diagram
R
T
May 2005
PGOOD
VREF
OSC
EAREF
SS
D03IN1509
VCC OCSET
PROTECTION
E/A
+
-
300K
COMP
MONITOR
& REF
OSC
PWM
-
+
BOOT
UGATE
PHASE
LGATE
PGND
GND
VFB
Vin 5V to 12V
V
O
Rev. 1
1/26
L6910G
Table 2. Absolute Maximum Ratings
Symbol Parameter Value Unit
Vcc Vcc to GND, PGND 15 V
V
BOOT-VPHASE
V
HGATE-VPHASE
T
j
T
stg
P
tot
OCSET PIN Maximum Withstanding Voltage Range
OTHER PINS ±2000 V
Table 3. Thermal Data
Symbol Parameter Value Unit
Boot Voltage 15 V
15 V
OCSET, LGATE, PHASE -0.3 to Vcc+0.3 V
SS, FB, PGOOD, VREF, EAREF, RT 7 V
COMP 6.5 V
Junction Temperature Range -40 to 150 °C
Storage temperature range -40 to 150 °C
Maximum power dissipation at Tamb = 25°C1W
±1000 V
Test Condition: CDF-AEC-Q100-002”Human Body Model”
Acceptance Criteria: “Normal Performance”
R
th j-amb
(*) Device soldered on 1 S2P PC board
Thermal Resistance Junction to Ambient 120 °C/W
Figure 3. Pins Connection (Top view)
VREF
OSC
OCSET
SS/INH
COMP
FB
GND
EAREF PGOOD
2
3
4
5
6
7
8
D03IN1510
16
15
14
13
12
11
10
N.C.1
VCC
LGATE
PGND
BOOT
HGATE
PHASE
9
2/26
L6910G
Table 4. Pins Function
Pin Name Description
1 VREF Internal 0.9V ±1.5% reference is available for external regulators or for the internal error amplifier
2 OSC Oscillator switching frequency pin. Connecting an external resistor (R
3 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection.
4 SS/INH The soft start time is programmed connecting an external capacitor from this pin and GND. The
5 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control
6 FB This pin is connected to the error amplifier inverting input and is used to compensate the voltage
7 GND All the internal references are referred to this pin. Connect it to the PCB signal ground.
8 EAREF Error amplifier non-inverting input. Connect to this pin an external reference (from 0.9V to 3V) for
9
PGOOD
10 PHASE
11 HGATE High side gate driver output.
12 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet.
13 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to
14 LGATE This pin is the lower mosfet gate driver output
15 VCC Device supply voltage. The operative supply voltage ranges is from 5V to 12V.
16 N.C. This pin is not internally bonded. It may be left floating or connected to GND.
(connecting this pin to EAREF) if external reference is not available.
A minimum 1nF capacitor is required.
If the pin is forced to a voltage lower than 70%, the device enters the hiccup mode.
) from this pin to GND, the
T
external frequency is increased according to the equation:
6
⋅
4.94 10
f
OSC,RT
200K H z
-------------------------+=
R
KΩ()
T
Connecting a resistor (RT) from this pin to Vcc (12V), the switching frequency is reduced according to
the equation:
7
⋅
4.306 10
f
OSC,RT
200K H z
-----------------------------–=
R
T
KΩ()
If the pin is not connected, the switching frequency is 200KHz.
The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in oscillator
stops to switch.
In Over Voltage condition this pin goes over 3V until that conditon is removed.
The internal 200µA current generator sinks a constant current through the external resistor. The
Over-Current threshold is due to the following equation:
I
I
----------------------------------------------=
P
⋅
OCSETROCSET
R
DSon
internal current generator forces through the capacitor 10µA.
This pin can be used to disable the device forcing a voltage lower than 0.4V
feedback loop.
control feedback loop.
Connected to the output resistor divider, if used, or directly to Vout, it manages also over-voltage
conditions and the PGOOD signal
the PWM regulation or short it to VREF pin to use the internal reference.
If this pin goes under 650mV (typ), the device shuts down.
This pin is an open collector output and it is pulled low if the output voltage is not within the above
specified thresholds. If not used it may be left floating.
This pin is connected to the source of the upper mosfet and provides the return path for the high side
driver. This pin monitors the drop across the upper mosfet for the current limit together with OCSET.
Connect through a capacitor to the PHASE pin and through a diode to Vcc (cathode vs. boot).
VBOOT limited to VOCSET -10V(typ.) when all other pins are connected to GND.
reduce the noise injection into the device
DO NOT CONNECT V
TO A VOLTAGE GREATER THAN VCC.
IN
3/26
L6910G
Table 5. Electrical Characteristics (Vcc = 12V, TJ =25°C unless otherwise specified)
Symbol Parameter Test Condition Min Typ Max Unit
SUPPLY CURRENT
V
cc
Icc Vcc Supply current OSC = open; SS to GND 4 7 9 mA
POWER-ON
Turn-On Vcc threshold VOCSET = 4V 4.0 4.3 4.6 V
Turn-Off Vcc threshold VOCSET = 4V 3.8 4.1 4.4 V
Rising V
Turn On EAREF threshold VOCSET = 4V 650 750 mV
SOFT START AND INHIBIT
Iss Soft start Current
S.S. current in INH condition
OSCILLATOR
f
OSC
f
OSC,RT
Initial Accuracy OSC = OPEN
Total Accuracy 16 KΩ < RT to GND < 200 KΩ -15 15 %
∆Vosc Ramp amplitude 1.9 V
REFERENCE
V
V
V
Output Voltage Accuracy V
OUT
Reference Voltage C
REF
Reference Voltage C
REF
ERROR AMPLIFIER
I
EAREF
N.I. bias current V
EAREF Input Resistance Vs. GND 300 kΩ
I
V
V
COMP
G
I.I. bias current VFB = 0V to 3V 0.01 0.5 µA
FB
Common Mode Voltage 0.8 3 V
CM
Output Voltage 0.5 4 V
Open Loop Voltage Gain 70 85 dB
V
GBWP Gain-Bandwidth Product 10 MHz
SR Slew-Rate COMP = 10pF 10 V/µs
GATE DRIVERS
I
HGATE
High Side
Source Current
R
HGATE
High Side
Sink Resistance
I
LGATE
R
LGATE
Low Side Source Current Vcc = 12V; V
Low Side Sink Resistance Vcc = 12V 1.5 3 Ω
Output Driver Dead Time PHASE connected to GND 90 210 ns
PROTECTIONS
I
OCSET
OCSET Current Source V
Over Voltage Trip (V
I
OSC
OSC Sourcing Current V
POWER GOOD
Upper Threshold (V
Lower Threshold (V
Hysteresis (V
V
PGOOD
I
PGOOD
PGOOD Voltage Low I
Output Leakage Current V
threshold 1.24 1.4 V
OCSET
SS = 2V
6103514
SS = 0 to 0.4V
FB
/ V
180
OSC = OPEN; T
= VFB; V
OUT
= 1nF; I
REF
= 1nF; TJ = 0 to 125°C-2 +2%
REF
= 3V 10 µA
EAREF
V
- V
BOOT
- V
V
HGATE
V
- V
BOOT
= 4V 170 200 230 µA
OCSET
/ V
FB
/ V
FB
/ V
FB
EAREF
)VFB Rising 117 120 %
EAREF
> OVP Trip 15 30 mA
FB
)VFB Rising 108 110 112 %
EAREF
)VFB Falling 88 90 92 %
EAREF
) Upper and Lower threshold 2 %
= -4mA 0.4 V
PGOOD
= 6V 0.2 1 µA
PGOOD
= 0° to 125°
j
= V
EAREF
REF
PHASE
PHASE
= 12V 2 4 Ω
PHASE
LGATE
REF
= 0 to 100µA 0.886 0.900 0.913 V
= 12V
= 6V
= 6V 0.9 1.1 A
170
0.886 0.900 0.913 V
11.3 A
200 220
60
230
µA
µA
KHz
kHz
4/26
L6910G
4 DEVICE DESCRIPTION
The device is an integrated circuit realized in BCD technology. The controller provides complete control logic and protection for a high performance step-down DC-DC converter. It is designed to drive N
Channel Mosfets in a synchronous-rectified buck topology. The output voltage of the converter can be
precisely regulated down to 900mV with a maximum tolerance of ±1.5% when the internal reference is
used (simply connecting together EAREF and VREF pins). The device allows also using an external
reference (0.9V to 3V) for the regulation. The device provides voltage-mode control with fast transient
response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 10MHz gain-bandwidth product and 10V
high converter bandwidth for fast transient performance. The PWM duty cycle can range from 0% to
100%. The device protects against over-current conditions entering in HICCUP mode. The device
monitors the current by using the
r
DS(ON)
of the upper MOSFET(s) that eliminates the need for a cur-
rent sensing resistor. The device is available in SO16 narrow package.
4.1 Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is typically 50
OSC pin and GND or V
µ
A (Fsw = 200KHz) and may be varied using an external resistor (RT) connected between
. Since the OSC pin is maintained at fixed voltage (typ. 1.235V), the frequency is var-
CC
ied proportionally to the current sunk (forced) from (into) the pin.
In particular connecting R
vs. GND the frequency is increased (current is sunk from the pin), according to the
T
following relationship:
4.94 10
-------------------------+=
R
Connecting R
f
OSC,RT
to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according
T
200KHz
to the following relationships:
f
OSC,RT
200KHz
4.306 10
-----------------------------–=
R
⋅
KΩ()
T
7
/µs
slew rate that permits to realize
6
⋅
K
Ω()
T
V
CC
= 12V
15 10
f
OSC,RT
200KHz
---------------------–=
R
T
Switching frequency variation vs. RT are repeated in Fig. 4.
Note that forcing a 50
µ
A current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 4.
10000
1000
100
Resistance [kOhm]
10
10 100 1000
RT to GND
RT to VCC=12V
RT to VCC=5V
Frequency [kHz]
6
⋅
KΩ()
= 5V
V
CC
5/26
L6910G
4.2 Reference
A precise ±1.5% 0.9V reference is available. This reference must be filtered with 1nF ceramic capacitor to avoid
instability in the internal linear regulator. It is able to deliver up to 100
device regulation and also for other devices. If forced under 70% of its nominal value, the device enters in Hiccup mode until this condition is removed.
Through the EAREF pin the reference for the regulation is taken. This pin directly connects the non-inverting
input of the error amplifier. An external reference (or the internal 0.9V ±1.5%) may be used. The input for this
pin can range from 0.9V to 3V. It has an internal pull-down (300k
no reference is connected (pin floating). However the device is shut down if the voltage on the EAREF pin is
lower than 650mV (typ).
4.3 Soft Start
At start-up a ramp is generated charging the external capacitor CSS with an internal current generator. The initial
value for this current is of 35
10
µ
A until the final charge value of approximatively 4V.
When the voltage across the soft start capacitor (V
charge the output capacitor. As V
µ
A and speeds-up the charge of the capacitor up to 0.5V. After that it becames
) reaches 0.5V the lower power MOS is turned on to dis-
reaches 1.1V (i.e. the oscillator triangular wave inferior limit) also the upper
SS
SS
MOS begins to switch and the output voltage starts to increase.
No switching activity is observable if SS is kept lower than 0.5V and both mosfets are off.
If VCC and OCSET pins are not above their own turn-on thresholds and V
Start will not take place, and the relative pin is internally shorted to GND. During normal operation, if any undervoltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor
is rapidly discharged.
µ
A and may be used as reference for the
Ω
resistor) that forces the device shutdown if
is not above 650mV, the Soft-
EAREF
Figure 5. Soft Start (with Reference Present)
Vcc
Vin
Vss
LGATE
Vout
to GND
Vcc Turn-on threshold
Vin Turn-on threshold
1V
Timing Diagram
0.5V
Acquisition: CH1 = PHASE; CH2 = V
CH3 = PGOOD; CH4 = V
ss
out
;
4.4 Driver Section
The driver capability on the high and low side drivers allows using different types of power MOS (also multiple
MOS to reduce the R
), maintaining fast switching transition.
DSON
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use several kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
6/26
L6910G
avoided if the PHASE pin is over about 500mV. The lower mos is in any case turned-on after 200ns from the
high side turn-off.
The peak current is shown for both the upper (fig. 6) and the lower (fig. 7) driver at 5V and 12V. A 3.3nF capacitive load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ V
current is 1.3A @ V
= 12V and 500mA @ VCC = 5V.
CC
Similarly, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ VbootVphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase = 5V.
Figure 6. High Side Driver Peak Current. Vboot-Vphase = 12V (right) Vboot-Vphase = 5V (left)
= 12V and 500mA @ VCC = 5V, and the sink peak
CC
CH1 = High Side Gate CH4 = Gate Current
Figure 7. Low Side Driver Peak Current. VCC = 12V (right) VCC = 5V (left)
CH1 = Low Side Gate CH4 = Gate Current
4.5 Monitoring and Protections
The output voltage is monitored by means of pin FB. If it is not within ±10% (typ.) of the programmed value, the
powergood output is forced low.
The device provides overvoltage protection, when the voltage sensed on pin FB reaches a value 17% (typ.)
greater than the reference the OSC pin is forced high (3V typ.) and the lower driver is turned on as long as the
over-voltage is detected.
7/26
L6910G
µ
µ
µ
Overcurrent protection is performed by the device comparing the drop across the high side MOS, due to the
R
, with the voltage across the external resistor (R
DSON
upper MOS. Thus the overcurrent threshold (I
Where the typical value of I
R
(also the variation with temperature) and the minimum value of I
dsON
is 200µA. To calculate the R
OCS
) can be calculated with the following relationship:
P
I
P
overcurrent protection this relationship must be satisfied:
I
PIOUTMAX
∆
Where
I is the inductance ripple current and I
OUTMAX
In case of over current detectionthe soft start capacitor is discharged with constant current (10
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occurs, the device turns off both mosfets, and the SS capacitor is discharged again (after reaching the upper threshold of about 4V). The system is now working in HICCUP mode,
as shown in figure 8. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 8. Hiccup Mode Figure 9. Inductor Ripple Current vs. Vout
) connected between the OCSET pin and drain of the
OCS
R
⋅
OCSIOCS
---------------------------------=
R
dsON
value it must be considered the maximum
I∆
=
-----+≥ I
2
OCS
PEAK
. To avoid undesirable trigger of
OCS
is the maximum output current.
µ
A typ.) and when
CH1 = SS; CH4 = Inductor current
9
8
7
6
5
4
3
2
Inductor Ripple [A]
1
0
0.5 1.5 2.5 3.5
Output V oltage [V]
L=1.5
H, Vin=12V
H, Vin=5V
L=3
L=2µH,
Vin=12V
L=3µH,
Vin=12V
L=1.5
Vin=5V
L=2µH,
Vin=5V
H,
4.6 Inductor Design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current
∆
IL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
V
–
INVOUT
L
------------------------------
f
swIL
Where f
is the switching frequency, VIN is the input voltage and V
SW
the ripple current vs. the output voltage for different values of the inductor, with V
V
OUT
---------------⋅=
∆⋅
V
IN
is the output voltage. Figure 9 shows
OUT
= 5V and VIN = 12V.
IN
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
8/26
L6910G
The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
4.7 Output Capacitor
The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output
voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL):
∆
I load transient in case of enough fast compensation network response:
t
application
LI∆⋅
------------------------------ t
V
–
INVOUT
removal
LI∆⋅
---------------==
V
OUT
∆ I
V
OUT
∆ ESR⋅=
OUT
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
2
I
OUT
L
⋅
–⋅()⋅⋅
Where D
∆
OUT
is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
MAX
---------------------------------------------------------------------------------------------=
2C
OUTVINMINDMAXVOUT
V
∆
during load transient and the lower is the output voltage static ripple.
4.8 Input Capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
I
rmsIOUT
D1D–()⋅=
Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are:
P ESR I
2
⋅=
rms
4.9 Compensation Network Design
The control loop is a voltage mode (figure 10). The output voltage is regulated to the input Reference voltage
level (EAREF). The error amplifier output V
a pulse-width modulated (PWM) wave with an amplitude of V
output filter. The modulator transfer function is the small-signal transfer function of V
has a double pole at frequency F
depending on the L-C
LC
output capacitor ESR. The DC Gain of the modulator is simply the input voltage V
oscillator voltage
∆
V
.
OSC
is then compared with the oscillator triangular wave to provide
COMP
at the PHASE node. This wave is filtered by the
IN
resonance and a zero at F
out
IN
OUT/VCOMP
ESR
divided by the peak-to-peak
. This function
depending on the
9/26
L6910G
Figure 10. Compensation Network
V
IN
∆V
OSC
PWM
COMPARATOR
C18
C19
R5
EAREF
V
COMP
-
The compensation network consists in the internal error amplifier and the impedance networks ZIN (R3, R4 and
C20) and Z
(R5, C18 and C19). The compensation network has to provide a closed loop transfer function with
FB
the highest 0dB crossing frequency to have fast response (but always lower than fsw/10) and the highest gain
in DC conditions to minimize the load regulation.
A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include
worst-case component variations when determining phase margin.
To locate poles and zeroes of the compensation networks, the following suggestions may be used:
Modulator singularity frequencies:
ω
LC
1
--------------------------- ω
LC
⋅
OUT
ESR
L
V
OUT
ESR
C
OUT
R3
C20
R4
D03IN1512
1
---------------------------------==
ESR C
⋅
OUT
Compensation network singularity frequency:
ω
----------------------------------------------- ω
P1
R5
ω
------------------------ ω
Z1
R5 C19⋅
1
C18 C19⋅
⋅
-----------------------------
C18 C19+
1
Z2
P2
-------------------------------------------==
R3 R4+()C20⋅
– Put the gain R5/R3 in order to obtain the desired converter bandwidth;
– Place ω
– Place ω
– Place ω
– Place ω
before the output filter resonance ωLC;
Z1
at the output filter resonance ωLC;
Z2
at the output capacitor ESR zero ω
P1
at one half of the switching frequency;
P2
ESR
;
– Check the loop gain considering the error amplifier open loop gain.
1
------------------------==
R4 C20⋅
1
10/26
Figure 11. Asymptotic Bode Plot of Converter's Gain
ω
ω
ω
ω
ω
ω
ω
dB
Error Amplifier
R5/R3
L6910G
Ζ1
LC
Modulator Gain
Compensation Network Gain
Error Amplifier Closed Loop Gain
Ζ2
ESR
P1
P2
5 15A DEMO BOARD DESCRIPTION
The demo board shows the operation of the device in a general purpose application. This evaluation board allows voltage adjustability from 0.9V to 5V through the switches S2-S5 according to the reported table when the
internal 0.9V reference is used (G1 closed). Output current in excess of 20A can be reached dependently on
the kind of mosfet used: up to three SO8 mosfet may be used for both High side and Low side switches. External
reference may be used for the regulation simply leaving open G1 and the switches S2-S5. The device may also
be disabled with the switch S1. The V
the V
input rail. The device is also able to operate with a single supply voltage; in this case the jumper G2 has
IN
to be closed and a 5V to 12V input can be directly connected to the V
copper thickness is of 70
µ
m in order to minimize conduction losses considering the high current that the circuit
is able to deliver.The PGOOD signal is used as a logic level and it's been pulled up to V
other appropriate voltage available on the demo board.
Maximum Absolute Rating) a 5V reference is required.
Figure 12. 15A Demo Board Schematic
F1
VIN
GNDIN
VCC
GNDCC
REFIN
GNDREFIN
+VREF
GNDREF
G2
R6
C17
EAREF
C16
G1
C12
C21
R1
S1
S2
S3
S4
S5
R10
R11
SR12
SR13
input rail supplies the device while the power conversion starts from
CC
input. The four layers demo board's
IN
because there's no
IN
In case of input voltage higher than 7V (PGOOD Pin
Figure 12 shows the demo board's schematic circuit
L1
C1-C3
D2
R8
R9
C22
V
S2
OUT
Open Open OpenOpen
0.9
ON Open Open Open
1.2
1.5
1.8
ON ON Open Open
2.5
Open Open ON Open
3.3
Open Open Open ON
5.0
Open Open ON ON
L2
ONOpen
C4-
11
S3 S4 S5
Open Open
R2
V
OUT
GNDOUT
PWRGD
V
C15
GND
VREF
OSC
R7
D1
BOOT
OCSET
CC
SS
15
7
8
1
4
2
COMP
12
5
C19
R5
C18
D03IN1513
VFB
C14
C13
Q1-3
UGATE
3
11
PHASE
10
14
13
9
6
LGATE
PGND
PGOOD
R3
R4
Q4-6
C20
11/26
L6910G
Table 6. Part List
Reference Description Manufacturer
R1 N.C NEOHM
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1KOhm 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 10Ohm 5% 125mW NEOHM SMD 0805
R7 510Ohm 5% 125mW NEOHM SMD 0805
R8 N.C
R9 0 Ohm SMD 0805
R10 14K 5% 125mW NEOHM SMD 0805
R11 6.98K 5% 125mW NEOHM SMD 0805
R12 2.61K 5% 125mW NEOHM SMD 0805
R13 1.74K 5 5% 125mW NEOHM SMD 0805
C1, C3 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C9, C10 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12, C13,
C15, C21
C14 1nF KEMET SMD0805
C16 100nF KEMET
C17 4.7µF - 16V AUX SMA6032
C18 1.5nF KEMET SMD0805
C19 15nF KEMET SMD0805
C20 47nF KEMET SMD0805
C22 N.C
L1 Short
L2 3µH (T50-52B Core, 7T AWG15) MICROMETALS
Q2,Q3,Q4,Q6 STS11NF30L ST SO8
D1 1N4148 SOT23
D2 STPS2L25U ST SMB
U1 Device L6910G ST SO16Narrow
F1 Short
SWITCH DIP SWITCH 6 POS.
100nF KEMET SMD0805
Table 7. Other Inductor Manufacturer
Manufacturer Series Inductor Value (µH) Saturation Current (A)
WÜRTH ELEKTRONIK 744318 1.8 to 2.7 16 to 20
PANASONIC ETQP6F1R8FA 1.8 20
SUMIDA CDEP134-2R7MC-H 2.7 15
12/26
Figure 13. PCB and Components Layouts
Component Side Internal Signal GND Layer
Figure 14. PCB and Components Layouts
L6910G
Internal Power GND Layer Solder Side
Figure 15. Efficiency vs Output Current
100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
Vin=Vcc=5V
80
80
75
75
1357 911131517
1357 911131517
Vin=Vcc=5V
Fsw=200KHz
Fsw=200KHz
Output Current (A)
Vo=3.3V
Vo=3.3V
Vo=2.5V
Vo=2.5V
Vo=1.8V
Vo=1.8V
Vo=1.5V
Vo=1.5V
Vo=1.2V
Vo=1.2V
Vo=0.9V
Vo=0.9V
13/26
L6910G
Figure 16. Efficiency vs Output Current
100
95
90
85
80
75
Efficiency (%)
70
65
60
55
50
1357911131517
Vin=Vcc=12V
Vin=Vcc=12V
Fsw.=200KHZ
Fsw.=200KHZ
Output Current (A)
Output Current (A)
Vo=5V
Vo=5V
Vo=3.3V
Vo=3.3V
Vo=1.5V
Vo=1.5V
Vo=1.8V
Vo=1.8V
Vo=2.5V
Vo=2.5V
Vo=1.2V
Vo=1.2V
Vo=0.9V
Vo=0.9V
6 COMPONENTS SELECTION
6.1 Inductor Selection
To select the right inductor value, the application conditions must be fixed. For example we can consider:
Vin=12V Vout =3.3V Iout=15A
Considering a ripple of approximately 25% to 30% of Iout, the inductor value will be L=3
An iron powder core (TO50-52B) with 7 windings has been chosen.
µ
H.
6.2 Output Capacitors
2 POSCAP capacitors, model 6TPB330M, have been chosen, with a maximum ERS equal to 40mΩ each.
Therefore, the resultant ESR is of 20m
Ω
. Considering a current ripple of 4A, the output voltage ripple is:
∆
Vout = 4 · 0.02 = 80mV
6.3 Input Capacitors
For I
= 15A and D = 0.5 (worst case for input current ripple), the RMS current of the input capacitor is equal
OUT
to 7.5A.
Two OSCON electrolytic capacitors 6SP680M, with a maximum ESR equal to 13m
tain the ripple. Therefore, the resultant ESR is equal to 13m
P = ESR · I
Ω
/2 = 6.5mΩ. The losses, in worst case, are:
2
rms = 366mW
Ω
, have been chosen to sus-
6.4 Over-Current Protection
The current limit can be set to approximately 20A. Substituting the demo board parameters in the relationship reported in the relative section, (I
that R
OCS
= 510Ω
OSCMIN
=170µA; IP = 20A; R
DSONMAX
= 9mΩ / 2=4.5mΩ) it results
14/26
L6910G
6.5 APPLICATION SUGGESTIONS FOR HIGHER CURRENTS
For higher output currents, up to 20A, the following configuration can be used (with reference to the demo board
schematic):
Q1,Q2,Q3: STS11NF30L
Q4,Q5,Q6: STS17NF3LL
L: 2.5
µ
H Magnetic 77121A7 Core 7T 2x AWG16
In these conditions, the following performance have been achieved:
Table 8.
V
(V) V
IN
5 1.2 20 81 12 1.2 20 80
5 1.5 20 83 12 1.5 20 83
5 1.8 20 85 12 1.8 20 85
5 2.5 20 89 12 2.5 20 88
5 3.3 20 91 12 3.3 20 91
For currents higher than 20A, bigger mosfets should be selected (e.g. STS25NH3LL) both for the high side and
low side (depending on the duty cycle and input voltage).
OUT
(V) I
OUT
(A)
η (%)
V
(V) V
IN
OUT
(V) I
OUT
(A)
12 5 20 93
η (%)
7 6A DEMO BOARD DESCRIPTION
A compact demo board has been realized to manage currents in the range of 5A-6A .
The external power mosfets are included in a single SO8 package to save space and increase power density.
Two separate rails are provided, for V
The PGOOD signal is used as a logic level and it's been pulled up to V
voltage available on the demo board.
solute Rating) a 5V reference is required.
Figure 17. 6A Demo Board Schematic
VIN
VIN
GNDIN
GNDINGNDIN
VCC
VCC
GNDCC
GNDCC
J1
J1
R6
R6
C5
C5
C9
C9C9
C8
C8
R10
R10
and VIN. They can be connected together by shorting the jumper J1.
CC
because there's no other appropriate
IN
In case of input voltage higher than 7V (PGOOD Pin Maximum Ab-
R7
R7
C7
C7
D1
D1
VCC
VCC
GND
GND
OSC
OSC
EAREF
EAREF
OCSET
OCSET
BOOT
BOOT
12
12
3
U1
U1
L6910
L6910
5
5
C19
C19
C18
C18
3
R5
R5
15
15
7
7
SS
SS
4
4
2
2
8
8
COMP
COMP
C6
C6
R8
R8
UGATE
UGATE
11
11
PHASE
PHASE
10
10
LGATE
LGATE
14
14
PGND
PGND
13
13
PGOOD
PGOOD
9
9
VREF
VREF
1
1
6
6
VFB
VFB
Q1/Q1
Q1/Q1
R9
R9
Q2/Q1
Q2/Q1
R3
R3
C20
C20C20
R4
R4R4
R11
R11
D2
D2
C10
C10
C1- C2
C1- C2
L1
L1
C3-4
C3-4
VOUT
VOUT
R2
R2
GNDOUT
GNDOUT
PWRGD
PWRGD
R1
R1
15/26
L6910G
Table 9. Part List
Reference Description Manufacturer
Resistor
R1 2K7 Ohm 0805 5% 125mW NEOHM (Vout = 2.5V)
1K8 Ohm 0805 5% 125mW NEOHM (Vout = 3.3V)
1K Ohm 0805 5% 125mW NEOHM (Vout = 5V)
R2 10K 5% 125mW NEOHM SMD 0805
R3 4K7 5% 125mW NEOHM SMD 0805
R4 4K7 5% 125mW NEOHM SMD 0805
R5 2K7 5% 125mW NEOHM SMD 0805
R6 10 Ohm 5% 125mW NEOHM SMD 0805
R7 680 Ohm 5% 125mW NEOHM SMD 0805
R8 R9 2.2 Ohm 5% 125mW NEOHM SMD 0805
R10 N.C
R11 N.C
Capacitors
C1,C2 10µF 25V TOKIN C34Y5U1E106ZTE12
C3,C4 100µF - 6.3V POSCAP 6TPB100M SMD7343
C5,C6,C9 100nF KEMET SMD0805
C7,C8 1nF KEMET SMD0805
C10 N.C
C18 1.5nF KEMET SMD0805
C19 15nF KEMET SMD0805
C20 47nF KEMET SMD0805
Magnetics
L1 7µH (T50-52B Core, 12T AWG 21) MICROMETALS
Transistor
Q1 STS8DNF3LL ST
Diodes
D1 1N4148 SOT23
D2 STPS2L25U ST SMB
Device
U1 Device L6910G ST SO16Narrow
Table 10. Other inductor manufacturer
Manufacturer Series Inductor Value (µH) Saturation Current (A)
WÜRTH ELEKTRONIK 744 382 4.8 to 5.8 7.5 to 8
PANASONIC ETQP6F 4.6 to 6.4 9.3 to 7.9
SUMIDA CDEP134-H 6 to 8 7.2 to 9.6
COILCRAFT DO3316P-472HC 4.7 5.4
DO3340P 10 to 22 8 to 5.5
COILTRONICS DR125-8R2 8.2 7.8
16/26
L6910G
Figure 18. PCB and Components Layouts
Component Side Solder Side
7.1 Compact Demo Board Performances
Figures 19, 20 show the measured efficiency versus load current for different values of output voltage. The measure has been done at 5V and 12V input. Output voltage has been changed modifying the value of R1 in the
demo board as reported in the part list.
Figure 19. Efficiency vs. Output Current
100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
Vin=Vcc=5V
Vin=Vcc=5V
75
75
Fsw=200KHz
Fsw=200KHz
70
70
12345678
12345678
Figure 20. Efficiency vs. Output Current
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
Vin=Vcc=12V
75
75
70
70
Vin=Vcc=12V
Fsw=200KHz
Fsw=200KHz
12345678
12345678
Output Current (A)
Output Current (A)
Output Current (A)
Output Current (A)
Vo=5V
Vo=5V
Vo=3.3V
Vo=3.3V
Vo=2.5V
Vo=2.5V
Vo=1.8V
Vo=1.8V
Vo=1.5V
Vo=1.5V
Vo=1.2V
Vo=1.2V
Vo=3.3V
Vo=3.3V
Vo=2.5V
Vo=2.5V
Vo=1.8V
Vo=1.8V
Vo=1.5V
Vo=1.5V
Vo=1.2V
Vo=1.2V
17/26
L6910G
8 APPLICATION IDEA 1: DDR MEMORY AND TERMINATION SUPPLY
Double Data Rate (DDR) Memories require a particular Power Management Architecture. This is due to the fact
that the trace between the driving chipset and the memory input must be terminated with resistors.
Since the Chipset driving the Memory has a push pull output buffer, the Termination voltage must be capable
of sourcing and sinking current.
Moreover, the Termination voltage must be equal to one half of the memory supply (the input of the memory is
a differential stage requiring a reference bias midpoint) and in tracking with it. For DDRI the Memory Supply is
2.5V and the Termination voltage is 1.25V while, for DDRII, the Memory Supply is 1.8V and the Termination
voltage is 0.9V. Fig. 23 shows a complete DDRI Memory and Termination Power Supply realized by using 2 x
L6910G. The 2.5V section is powering the memory while the 1.25V section is providing the termination voltage.
The tracking between the two sections is realized by providing the EAREF voltage of the 1.25V section through
a resistor divider connected to the 2.5V.
Figure 21. Application idea : DDR Memory Supply
VIN
VIN
VIN
12V
12V
12V
BOOT
BOOT
BOOT
OCSET
OCSET
OCSET
12
12
12
3
3
VCC
VCC
VCC
GND
GND
GND
OSC
OSC
OSC
EAREF
EAREF
EAREF
3
UGATE
UGATE
UGATE
11
11
11
15
15
15
PHASE
PHASE
PHASE
10
10
10
7
7
7
SS
SS
SS
4
4
4
2
2
2
8
8
8
5
5
5
COMP
COMP
COMP
U1
U1
U1
L6910
L6910
L6910
VFB
VFB
VFB
LGATE
LGATE
LGATE
14
14
14
13
13
13
PGOOD
PGOOD
PGOOD
9
9
9
VREF
VREF
VREF
1
1
1
6
6
6
STS11NF3LL
STS11NF3LL
STS11NF3LL
PGND
PGND
PGND
STS11NF3LL
STS11NF3LL
STS11NF3LL
V
V
V
DDQ
DDQ
DDQ
2.5V@15A
2.5V@15A
2.5V@15A
PWRGD
PWRGD
PWRGD
MEMORY
MEMORY
MEMORY
TERMIN ATION
TERMIN ATION
TERMIN ATION
NETWORK
NETWORK
NETWORK
DDR
DDR
DDR
VREF
VREF
VREF
BUS
BUS
BUS
VIN
VIN
VIN
12V
12V
12V
STS8DNF3LL
STS8DNF3LL
BOOT
BOOT
BOOT
OCSET
OCSET
OCSET
3
3
3
12
12
12
VCC
VCC
VCC
15
15
15
GND
GND
GND
7
7
7
SS
SS
SS
4
4
EAREF
EAREF
EAREF
4
OSC
OSC
OSC
2
2
2
8
8
8
5
5
5
COMP
COMP
COMP
-
-
+
+
+
R
R
R
R
R
R
U2
U2
U2
L6910
L6910
L6910
UGATE
UGATE
UGATE
11
11
11
PHASE
PHASE
PHASE
10
10
10
LGATE
LGATE
LGATE
14
14
14
PGND
PGND
PGND
13
13
13
PGOOD
PGOOD
PGOOD
9
9
9
VREF
VREF
VREF
1
1
1
6
6
6
VFB
VFB
VFB
STS8DNF3LL
V
V
V
TT
TT
TT
1.25V@ - 5A
1.25V@ - 5A
1.25V@ - 5A
PWRGD
PWRGD
PWRGD
CHIPSET
CHIPSET
CHIPSET
+
+
+
The current required by the memory and the termination supply, depends on the memory type and size.
The figure 22, 23 shows the efficiency of the L6910G for the termination section of the application shown in fig.
21, in sink and source mode. The figures show the efficiency values also when the input voltage is coming directly from the 12V rail.
18/26
L6910G
Figure 22. Efficiency vs Output Current Source
Mode
95
95
95
90
90
90
85
85
85
80
80
80
75
75
75
Efficiency (%)
Efficiency (%)
Vcc=12V
Vcc=12V
70
70
70
Vout=1.25V
Vout=1.25V
Fsw=200KHz
Fsw=200KHz
65
65
65
60
60
60
1234567
1234567
1234567
Output Current (A)
Output Current (A)
Vin=12V
Vin=12V
Vin=2.5V
Vin=2.5V
8
8
8
Figure 23. Efficiency vs Output Current Sink
Mode
95
95
90
90
85
85
Vin=2.5V
Vin=2.5V
Vin=12V
Vin=12V
Vin=12V
Vin=2.5V
80
80
75
75
Efficiency (%)
Efficiency (%)
Efficiency (%)
70
70
Vcc=12V
Vcc=12V
Vcc=12V
Vout=1.25V
Vout=1.25V
Vout=1.25V
65
65
Fsw=200KHz
Fsw=200KHz
Fsw=200KHz
60
60
12345678
12345678
Output Current (A)
Output Current (A)
Output Current (A)
For very big systems (e.g. servers), the DDR memory
termination can require much higher currents, in the
range of 10A-15A and more.
Figures 24, 25 and 26, 27 show the efficiency of the
L6910G in sink and source mode, up to 17A both for
DDRI and DDRII memories.The measurements have
been realized with the 15A demo board. (See pag.11 )
Figure 24. Efficiency vs Output Current Sink
Mode
100
100
100
90
90
90
80
80
80
70
70
70
Efficiency (%)
Efficiency (%)
Efficiency (%)
Efficiency (%)
60
60
60
50
50
50
1 3 5 7 9 11 13 15 17
1 3 5 7 9 11 13 15 17
1 3 5 7 9 11 13 15 17
Vin=12V
Vin=12V
Vin=12V
Vin=12V
Vin=12V
Vin=12V
Vcc=12V
Vcc=12V
Vcc=12V
Vcc=12V
Vout=1.25V
Vout=1.25V
Vout=1.25V
Vout=1.25V
Fsw=200KHz
Fsw=200KHz
Fsw=200KHz
Fsw=200KHz
Output Current (A)
Output Current (A)
Output Current (A)
Output Current (A)
Vin=2.5V
Vin=2.5V
Vin=2.5V
Vin=2.5V
Figure 25. Efficiency vs Output Current Sink
Mode
100
100
100
100
90
90
90
90
Vin=1.8V
Vin=1.8V
Vin=12V
Vin=12V
Vin=12V
Vin=1.8V
80
80
80
80
70
70
70
70
60
60
60
60
Efficiency (%)
Efficiency (%)
Vcc=12V
Vcc=12V
Vcc=12V
Vout=0.9V
Vout=0.9V
Vout=0.9V
50
50
50
50
Fsw=200KHz
Fsw=200KHz
Fsw=200KHz
40
40
40
40
1357911131517
1357911131517
1357911131517
1357911131517
Output Current (A)
Output Current (A)
Figure 26. Efficiency vs Output Current Source
Mode
100
100
Vout=2.5V
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
Vcc=12V
Vcc=12V
Vout=1.25V
Vout=1.25V
60
60
Fsw=200KHz
Fsw=200KHz
50
50
1 3 5 7 9 11 13 15 17
1 3 5 7 9 11 13 15 17
Output Current (A)
Output Current (A)
Vout=2.5V
Vout=12V
Vout=12V
Figure 27. Efficiency vs Output Current Source
Mode
100
100
100
90
90
90
80
80
80
70
70
70
Efficiency (%)
Efficiency (%)
Vin=12V
Vin=12V
Vin=12V
60
60
60
Vout=0.9V
Vout=0.9V
Vout=0.9V
Fsw=200KHz
Fsw=200KHz
Fsw=200KHz
50
50
50
1357911131517
1357911131517
1357911131517
Output Current (A)
Output Current (A)
Vin=1.8V
Vin=1.8V
Vin=1.8V
Vin=12V
Vin=12V
Vin=12V
19/26
L6910G
9 APPLICATION IDEA 2: POSITIVE BUCK-BOOST REGULATOR 3V TO 13.2V
INPUT / 5V 2.5A OUTPUT
In some applications the input voltage changes in a very wide range while the output must be regulated to a
fixed value. In this case a Buck-Boost topology can be required in order to keep the output voltage in regulation.
The schematic below shows how to implement a Buck-Boost regulating 5V at the output from both 3.3V and 5V
and 12V input buses.
In a Buck-Boost topology the current is delivered to the output during the OFF phase only. So, for a given current
limit, the maximum output current depends strongly on the duty cycle. Assuming a 100% efficiency and neglecting the current ripple across the inductor, the relationship betweent the current limit and the maximum output
current is the following:
Where I
is the current limit and D is the duty cycle of the application.
LIM
The worst case is with D
The worst case is with V
I
OMAXILIM
. Since, in a Buck-Boost application, D is given by the following formula:
MAX
D
.
INMIN
V
-----------------------=
VINVO+
1D–()⋅=
O
Obviously, since the efficiency is lower than 100% and the ripple is usually not negligible, the maximum output
current is always lower than the value calculated in the above formula
Figure 28. Positive buck-boost regulator 3V to 13.2V input / 5V 2.5A Output Circuit
VIN (3.3V-5V-12V BUSES)
VIN (3.3V-5V-12V BUSES)
C3
C3
R1
GNDIN
GNDINGNDIN
VCC (12V BUS)
VCC (12V BUS)
GNDCC
GNDCCGNDCC
G1
G1
D1
D1
R7
R7
C6
C6
C8
C8
VCC
VCC
C5
C5
GND
GND
SS
SS
OSC
OSC
EAREF
EAREF
C7
C7C7
BOOT
BOOT
12
12
15
15
7
7
U1
U1
4
4
L6910/A
L6910/A
2
2
8
8
5
5
COMP
COMP
C9
C9
C10
C10
R1
C4
C4
OCSET
OCSET
3
3
R5
R5
UGATE
UGATE
11
11
PHASE
PHASE
10
10
LGATE
LGATE
14
14
PGND
PGND
13
13
PGOOD
PGOOD
9
9
VREF
VREF
1
1
6
6
VFB
VFB
C12
C12
Q1
Q1
D2
Q2
Q2Q2
D2
R3
R3
C11
C11
R4
R4
C1- C2
C1- C2
Q4
L1
L1
Q4
Q3
Q3
C13
C13
C13
VOUT ( 5V 2.5A )
VOUT ( 5V 2.5A )
R2
R2
-14
-14
-14
GNDOUT
GNDOUT
20/26
R6
R6
Table 11. Part List
Reference Description Manufacturer
R1 910 Ohm 5% 125mW NEOHM SMD 0805
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1K 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 1K1 NEOHM SMD 0805
R7 10 Ohm 125mW NEOHM SMD 0805
C1,C2 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C13,C14 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12,C5,C8 100nF KEMET SMD0805
C3 1nF KEMET SMD0805
C4 470nF KEMET SMD0805
C6 4.7µF - 16V AUX SMA6032
C7 100nF KEMET
C9 15nF KEMET SMD0805
C10 1.5nF KEMET SMD0805
C11 47nF KEMET SMD0805
G1 Open Jumper
L1 2.5µH
(77121A7 Core, Double winding 7 AWG16)
Q1,Q2,Q3 STS11NF30L ST SO8
Q4 STS5P30L ST SO8
D1 1N4148 SOT23
D2 STPS3L25U (STPS340U) ST SMB (D0144)
U1 Device L6910G ST SO16 Narrow
MAGNETICS
L6910G
Figure 29. Efficiency vs. Output Current
90
90
Vin=5V
85
85
80
80
75
75
Efficiency (%)
Efficiency (%)
Vcc=5V
Vcc=5V
70
70
Vout=5V
Vout=5V
Fsw=200KHz
Fsw=200KHz
65
65
11.522.533.5
11.522.533.5
Vin=5V
Vin=3.3V
Vin=3.3V
Output Current (A)
Output Current (A)
Vin=12V
Vin=12V
21/26
L6910G
10 APPLICATION IDEA 3: BUCK-BOOST REGULATOR 3V TO 5.5V INPUT/-5V
3A OUTPUT
In applications where a negative output voltage is required, a standard Buck-Boost topology can be implemented. The considerations related to the maximum output current are the same of the "Positive Buck-Boost" (Application Idea 2).
A particularity of this topology is that the device undergoes a voltage that is the sum of V
verting 5V to -5V, the device undergoes 10V voltage. It must be checked that the sum of the input and output
voltage is lower than the maximum operating input voltage of the device.
Figure 30. buck-boost regulator 3V to 5.5V input / -5V 3A Output Circuit
VIN (3V to 5.5V )
VIN (3V to 5.5V )
VIN (3V to 5.5V )
GNDIN=GNDOUT
GNDIN=GNDOUT
GNDIN=GNDOUT
VCC (5V)
VCC (5V)
VCC (5V)
GNDCC
GNDCC
GNDCC
G1
G1
G1
D1
D1
D1
R7
R7
R7
VCC
VCC
VCC
C5
C5
C6
C6
C6
C8
C8
C8C8
C5
GND
GND
GND
SS
SS
SS
OSC
OSC
OSC
EAREF
EAREF
EAREF
C7
C7
C7C7
BOOT
BOOT
BOOT
12
12
12
15
15
15
7
7
7
U1
U1
U1
4
4
4
L6910/A
L6910/A
L6910/A
2
2
2
8
8
8
5
5
5
COMP
COMP
COMP
C9
C9
C9
C10
C10
C10
R1
R1
R1
C3
C3
C3
C4
C4
C4
OCSET
OCSET
OCSET
3
3
3
R5
R5
R5
UGATE
UGATE
UGATE
11
11
11
PHASE
PHASE
PHASE
10
10
10
LGATE
LGATE
LGATE
14
14
14
PGND
PGND
PGND
13
13
13
PGOOD
PGOOD
PGOOD
9
9
9
VREF
VREF
VREF
1
1
1
6
6
6
VFB
VFB
VFB
C12
C12
C12C12
Q1
Q1
Q1
D2
D2
C11
C11
C11
D2
Q2
Q2
Q2
R3
R3
R3
R4
R4
R4
L1
L1
L1
C1- C2
C1- C2
C1- C2C1- C2
and V
IN
C13-14
C13-14
C13-14
. So, con-
OUT
GNDOUT
GNDOUT
GNDOUTGNDOUT
VOUT (-5V 3A)
VOUT (-5V 3A)
VOUT (-5V 3A)
R6
R6
R6
Table 12. Part List
Reference Description Manufacturer
R1 910 Ohm 5% 125mW NEOHM SMD 0805
R2 10K 5% 125mW NEOHM SMD 0805
R3 4.7K 5% 125mW NEOHM SMD 0805
R4 1K Ohm 5% 125mW NEOHM SMD 0805
R5 2.7K 5% 125mW NEOHM SMD 0805
R6 1K 5% 125mW NEOHM SMD 0805
R7 10 Ohm 5% 125mW NEOHM SMD 0805
C1,C2 100µF - 20V OSCON 20SA100M RADIAL 10X10.5
C13,C14 330µF - 6.3V POSCAP 6TPB330M SMD7343
C12,C4,C5,C8 100nF KEMET SMD0805
C3 1nF KEMET SMD0805
C6 4.7µF - 16V AUX SMA6032
C7 100nF KEMET
22/26
Table 12. Part List (continued)
C9 15nF KEMET SMD0805
C10 1.5nF KEMET SMD0805
Reference Description Manufacturer
C11 47nF KEMET SMD0805
G1 Open Jumper
L1 2.5µH (77121A7 Core, Double winding 7 AWG16) MAGNETICS
Q1,Q2 STS11NF30L ST SO8
D1 1N4148 SOT23
D2 STPS3L25U ( STPS340U) ST SMB (D0144)
U1 Device L6910G ST SO16 Narrow
Figure 31. Efficiency vs. Output Current
94
94
92
92
90
90
Vin=5V
Vin=5V
L6910G
88
88
Vin=3.3V
86
86
Efficiency (%)
Efficiency (%)
Vcc=5V
Vcc=5V
84
84
Vout=
Vout=
-5V
-5V
Fsw=200KHz
Fsw=200KHz
82
82
11.522.53
11.522.53
Output Current (A)
Output Current (A)
Vin=3.3V
23/26
L6910G
Figure 32. SO-16 (Narrow) Mechanical Data & Package Dimensions
DIM.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45° (typ.)
(1)
D
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
(1)
F
G 4.60 5.30 0.181 0.208
L 0.4 1.27 0.150 0.050
M 0.62 0.024
S8° (max.)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
9.8 10 0.386 0.394
3.8 4.0 0.150 0.157
OUTLINE AND
MECHANICAL DATA
SO16 (Narrow)
24/26
0016020 D
Table 1. Revision History
Date Revision Description of Changes
May 2005 1 First Issue
L6910G
25/26
L6910G
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