Features
■ Dual MOSFET driver for synchronous rectified
converters
■ High driving current for fast external MOSFET
switching
■ Integrated bootstrap diode
■ High frequency operation
■ Enable pin
■ Adaptive dead-time management
■ Flexible gate-drive: 5 V to 12 V compatible
■ High-impedance (HiZ) management for output
stage shutdown
■ Preliminary OV protection
■ SO-8 and DFN10 3x3 packages
Applications
■ High current VRM / VRD for desktop / server /
workstation CPUs
■ High current and high efficiency DC / DC
converters
Description
L6743, L6743Q is a flexible, high-frequency dualdriver specifically designed to drive N-channel
MOSFETs connected in synchronous-rectified
buck topology.
L6743
L6743Q
High current MOSFET driver
SO-8
Combined with ST PWM controllers, the driver
allows implementing complete voltage regulator
solutions for modern high-current CPUs and
DCDC conversion in general. L6743, L6743Q
embeds high-current drivers for both high-side
and low-side MOSFETS. The device accepts
flexible power supply (5 V to 12 V) to optimize the
gate-drive voltage for High-Side and Low-Side
maximizing the System Efficiency.
The Bootstrap diode is embedded saving the use
of external diodes. Anti shoot-through
management avoids high-side and low-side
MOSFET to conduct simultaneously and,
combined with Adaptive Dead-Time control,
minimizes the LS body diode conduction time.
L6743, L6743Q embeds Preliminary OV
Protection: after Vcc overcomes the UVLO and
while the device is in HiZ, the LS MOSFET is
turned ON to protect the load in case the output
voltage overcomes a warning threshold protecting
the output against HS failures.
The driver is available is SO-8 and DFN10 3x3
packages
DFN10 3x3
Table 1. Device summary
Order code Package Packaging
L6743 SO-8 Tube
L6743TR SO-8 Tape and reel
L6743Q DFN10 Tube
L6743QTR DFN10 Tape and reel
June 2008 Rev 2 1/17
www.st.com
1
Contents L6743, L6743Q
Contents
1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Preliminary OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3 Internal BOOT diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.5 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/17
L6743, L6743Q Typical application circuit and block diagram
1 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
VCC = 5V to 12V
C
PWM Input
DEC
PWM
VCC
BOOT
UGATE
HS
HF
C
VIN = 5V to 12V
C
BULK
EN Input
L6743 Reference Schematic
EN
GND
1.2 Block diagram
Figure 2. Block diagram
VCC
EN
PWM
15k
GND
PHASE
L6743
LGATE
NC*NC*
CONTROL LOGIC
& PROTECTIONS
L6743
PWM
LS
CROSS CONDUCTION
ADAPTIVE ANTI
HS
VCC
LS
L
Vout
C
OUT
BOOT
UGATE
PHASE
LGATE
GND
3/17
Pin description and connection diagrams L6743, L6743Q
2 Pin description and connection diagrams
Figure 3. Pin connection (top view)
BOOT
PWM
EN
VCC
1
2
3
4
2.1 Pin description
Table 2. Pin description
Pin n
DFN10 SO-8
11BOOT
22PWM
33 EN
4, 5 4 VCC
Name Function
High-side driver supply.
This pin supplies the high-side floating driver. Connect through a R
capacitor to the PHASE pin.
Internally connected to the cathode of the integrated bootstrap diode. See
Section 5.3 for guidance in designing the capacitor value.
Control input for the driver, 5 V compatible.
This pin controls the state of the driver and which external MOSFET have to be
turned-ON according to EN status. If left floating and in conjunction with EN
asserted, it causes the driver to enter the high-impedance (HiZ) state which causes
all MOSFETs to be OFF. See Section 5.1 for details about HiZ.
Enable input for the driver. Internally pulled low by 15 kΩ.
Pull high to enable the driver according to the PWM status. If pulled low will cause
the drive to enter HiZ state with all MOSFET OFF regardless of the PWM status.
See Section 5.1 for details about HiZ.
Device and LS driver power supply. Connect to any voltage between 5 V and 12 V.
Bypass with low-ESR MLCC capacitor to GND.
L6743
8
7
6
5
UGATE
PHASE
GND
LGATE
BOOT
PWM
EN
VCC
VCC
1
2
3
L6743Q
4
56
10
9
8
7
BOOT
UGATE
PHASE
GND
GND
LGATE
- C
BOOT
Low-side driver output.
65LGATE
7, 8 6 GND
9 7 PHASE
10 8 UGATE
PA D - T H . PA D
4/17
Connect directly to the low-side MOSFET gate. A small series resistor can be useful
to reduce dissipated power especially in high frequency applications.
All internal references, logic and drivers are referenced to this pin. Connect to the
PCB ground plane.
High-side driver return path. Connect to the high-side MOSFET source.
This pin is also monitored for the adaptive dead-time management and Pre-OV
Protection.
High-side driver output.
Connect to high-side MOSFET gate.
Thermal pad connects the Silicon substrate and makes good thermal contact with
the PCB. Connect to the PGND plane. (DFN10 only)
L6743, L6743Q Thermal data
3 Thermal data
Table 3. Thermal data
Val ue
Symbol Parameter
SO8 DFN10
Unit
Thermal resistance junction to ambient
(Device soldered on 2s2p, 67 mm x 69 mm board)
Thermal resistance junction to case - 5 °C/W
Maximum junction temperature 150 °C
Storage temperature range 0 to 150 °C
Junction temperature range 0 to 125 °C
Maximum power dissipation at 25°C
(Device soldered on 2s2p PC board)
R
R
T
T
P
thJA
thJC
MAX
STG
T
J
TOT
4 Electrical specifications
4.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Symbol Parameter Value Unit
V
CC,VPVCC
V
BOOT
V
V
V
PWM, VEN
V
CC,VPVCC
, V
UGATE
PHASE
LGATE
to GND -0.3 to 15 V
to GND
to PHASE
to GND -8 to 26 V
to GND -0.3 to VCC + 0.3 V
to GND -0.3 to 7 V
to GND -0.3 to 15 V
85 45 °C/W
1.15 2.25 W
41
15
V
5/17
Electrical specifications L6743, L6743Q
4.2 Electrical characteristics
Table 5. Electrical characteristics
(V
= 12 V±15 %, TJ = 0 °C to 70 °C unless otherwise specified).
CC
Symbol Parameter Test conditions Min. Typ. Max. Unit
Supply current and power-ON
I
CC
I
BOOT
VCC supply current
BOOT supply current
VCC turn-ON VCC rising 4.1 V
UVLO
VCC
VCC turn-OFF VCC falling 3.5 V
PWM and EN input
Input high - V
PWM
Input low - V
t
HiZ
HiZ hold-off time 150 ns
Input high - V
EN
Input low - V
Input resistance to GND 15 kΩ
Gate drivers
R
HIHS
I
UGATE
R
LOHS
R
HILS
I
LGATE
R
LOLS
HS source resistance BOOT - PHASE = 12 V; 100 mA 2.3 2.8 Ω
HS source current
HS sink resistance BOOT - PHASE = 12 V; 100 mA 2 2.5 Ω
LS source resistance 100 mA 1.3 1.8 Ω
LS source current
LS sink resistance 100 mA 1 1.5 Ω
Protections
PWM_IH
PWM_IL
EN_IH
EN_IH
(1)
(1)
C
UGATE and LGATE = OPEN
BOOT = 12 V
UGATE = OPEN;
PHASE to GND; BOOT = 12 V
5mA
2mA
PWM rising 2 V
PWM falling 0.8 V
EN rising 2 V
EN falling 0.8 V
BOOT - PHASE = 12 V;
C
to PHASE = 3.3 nF
UGATE
to GND = 5.6 nF 3 A
LGATE
2A
V
PRE_OV
1. Parameter(s) guaranteed by designed, not fully tested in production
Pre-OV threshold PHASE rising 1.8 V
6/17
L6743, L6743Q Device description and operation
5 Device description and operation
L6743, L6743Q provides high-current driving control for both high-side and low-side
N-channel MOSFETS connected as step-down DC-DC Converter driven by an external
PWM signal. The integrated high-current drivers allow using different types of power
MOSFETs (also multiple MOS to reduce the equivalent R
transition.
The driver for the high-side MOSFET use BOOT pin for supply and PHASE pin for return.
The driver for the low-side MOSFET use the VCC pin for supply and PGND pin for return.
The driver embodies a anti-shoot-through and adaptive dead-time control to minimize LowSide body diode conduction time maintaining good efficiency saving the use of Schottky
diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when
the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is suddenly applied.
When the low-side MOSFET turns off, the voltage at LGATE pin is sensed. When it drops
below about 1 V, the high-side MOSFET gate drive voltage is suddenly applied. If the
current flowing in the inductor is negative, the source of highside MOSFET will never drop.
To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is
enabled: if the source of the high-side MOSFET doesn't drop, the low-side MOSFET is
switched on so allowing the negative current of the inductor to recirculate. This mechanism
allows the system to regulate even if the current is negative.
), maintaining fast switching
DS(on)
Before VCC to overcome the UVLO threshold, L6743, L6743Q keeps firmly-OFF both highside and low-side MOSFETS then, after the UVLO has been crossed, the EN and PWM
inputs take the control over driver’s operations. EN pin enables the driver: if low will keep all
MOSFET OFF (HiZ) regardless of the status of PWM. When EN is high, the PWM input
takes the control: if left floating, the internal resistor divider sets the HiZ state: both
MOSFETS are kept in the OFF state until PWM transition.
After UVLO crossing and while in HiZ, the preliminary-OV protection is activated: if the
voltage senses through the PHASE pin overcomes about 1.8 V, the low-side MOSFET is
latched ON in order to protect the load from dangerous over-voltage. The driver status is
reset from a PWM transition.
Driver power supply as well as power conversion input are flexible: 5 V and 12 V can be
chosen for high-side and low-side MOSFET voltage drive.
Figure 4. Timing diagram (EN = High)
PWM
HiZ Window
HS Gate
LS Gate
HiZ
HiZ Window
HiZ
prop_L
t
dead_LH
t
prop_H
t
dead_HL
t
t
hold-off
prop_ L
t
t
hold-off
7/17
Device description and operation L6743, L6743Q
5.1 High-impedance (HiZ) management
The driver is able to manage high-impedance state by keeping all MOSFETs in off state in
two different ways.
● If the EN signal is pulled low, the device will keep all MOSFETs OFF careless of the
PWM status.
● When EN is asserted, if the PWM signal remains in the HiZ window for a time longer
than the hold-off time, the device detects the HiZ condition so turning off all the
MOSFETs. The HiZ window is defined as the PWM voltage range comprised between
V
PWM_IL
The device exits from the HiZ state only after a PWM transition to logic zero (V
V
PWM_IL
and V
).
PWM_IH
.
<
PWM
See Figure 4 for details about HiZ timings.
The implementation of the high-impedance state allows the controller that will be connected
to the driver to manage high-impedance state of its output, avoiding to produce negative
undershoot on the regulated voltage during the shut-down stage. Furthermore, different
power management states may be managed such as pre-bias start-up.
5.2 Preliminary OV protection
After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the
Preliminary-OV protection.
The intent of this protection is to protect the load especially from high-side MOSFET failures
during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12 V
bus compatible turn-on threshold and results to be non-operative if VCC is below that turnon thresholds (that results being in the range of about 10 V). In case of a high-side MOSFET
failure, the controller won’t recognize the over voltage until VCC = ~10 V (unless other
special features are implemented): but in that case the output voltage is already at the same
voltage (~10 V) and the load (CPU in most cases) already burnt.
L6743, L6743Q by-pass the PWM controller by latching on the low-side MOSFET in case
the PHASE pin voltage overcome
2 V during the HiZ state. When the PWM input exits form
the HiZ window, the protection is reset and the control of the output voltage is transferred to
the controller connected to the PWM input.
Since the driver has its own UVLO threshold, a simple way to provide protection to the
output in all conditions when the device is OFF consists in supplying the controller through
the 5 V
bus: 5 VSB is always present before any other voltage and, in case of High-Side
SB
short, the low-side MOSFET is driven with 5 V assuring a reliable protection of the load.
Preliminary OV is active after UVLO and while the driver is in HiZ state and it is disabled
after the first PWM transition. The controller will have to manage its output voltage from that
time on.
8/17
L6743, L6743Q Device description and operation
5.3 Internal BOOT diode
L6743, L6743Q embeds a boot diode to supply the high-side driver saving the use of an
external component. Simply connecting an external capacitor between BOOT and PHASE
complete the high-side supply connections.
To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,
an external series resistance R
BOOT pin.
Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the
high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side driver
during the MOSFET turn-on also minimizing the power dissipated by the embedded Boot
Diode. Figure 5 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected MOSFET.
Figure 5. Bootstrap capacitance design
(in the range of few ohms) may be required in series to
BOOT
5.4 Power dissipation
L6743, L6743Q embeds high current drivers for both high-side and low-side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power.
● Device power (P
supply pins and it is simply quantifiable as follow:
P
VCCI
DC
● Drivers' power is the power needed by the driver to continuously switch ON and OFF
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power P
dissipated to switch the MOSFETs dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the MOSFETs results:
P
SWFSWQGHS
) depends on the static consumption of the device through the
DC
CCVPVCCIPVCC
⋅+⋅=
PVCC⋅ Q
GLS
SW
VCC⋅+()⋅=
9/17
Device description and operation L6743, L6743Q
When designing an application based on L6743, L6743Q it is recommended to take into
consideration the effect of external gate resistors on the power dissipated by the driver.
External gate resistors helps the device to dissipate the switching power since the same
power P
will be shared between the internal driver impedance and the external resistor
SW
resulting in a general cooling of the device.
Referring to Figure 6, classical MOSFET driver can be represented by a push-pull output
stage with two different MOSFETs: P-MOSFET to drive the external gate high and NMOSFET to drive the external gate low (with their own R
R
). The external power MOSFET can be represented in this case as a capacitance
lo_LS
(C
G_HS
, C
) that stores the gate-charge (Q
G_LS
G_HS
, Q
G_LS
DS(on)
: R
hi_HS, Rlo_HS
, R
hi_LS,
) required by the external power
MOSFET to reach the driving voltage (PVCC for HS and VCC for LS). This capacitance is
charged and discharged at the driver switching frequency F
SW
.
The total power Psw is dissipated among the resistive components distributed along the
driving path. According to the external gate resistance and the power-MOSFET intrinsic
gate resistance, the driver dissipates only a portion of Psw as follow:
P
P
SW HS–
SW LS–
1
-- -
⋅⋅ ⋅⋅=
C
2
1
-- -
⋅⋅ ⋅⋅=
C
2
GHS
GLS
VCC2Fsw
PVCC2Fsw
⎛⎞
--------------------------------------------------------------- -
⎝⎠
R
⎛⎞
------------------------------------------------------------- -
⎝⎠
R
hiLSRGateLSRiLS
R
hiHS
++
hiHSRGateHSRiHS
R
hiLS
++
--------------------------------------------------------------- -+
R
------------------------------------------------------------- -+
R
loLSRGateLSRiLS
R
loHS
++
loHSRGateHSRiHS
R
loLS
++
The total power dissipated from the driver can then be determined as follow:
PP
DCPSW HS–
++=
P
SW LS–
Figure 6. Equivalent circuit for MOSFET drive
VCC
VCC
RhiLSRloLS
LGATE
LS DRIVER LS MOSFET
GND
RGATELS RILS
CGLS
RhiHSRloHS
HS DRIVER HS MOSFET
BOOT
RGATEHS
HGATE
PHASE
RIHS
CGHS
10/17
L6743, L6743Q Device description and operation
5.5 Layout guidelines
L6743, L6743Q provides driving capability to implement high-current step-down DC-DC
converters.
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (also EMI and losses) power connections must be a part
of a power plane and anyway realized by wide and thick copper traces: loop must be anyway
minimized. The critical components, such as the power MOSFETs, must be close one to the
other. However, some space between the power MOSFET is still required to assure good
thermal cooling and airflow.
Traces between the driver and the MOSFETS should be short and wide to minimize the
inductance of the trace so minimizing ringing in the driving signals. Moreover, VIAs count
needs to be minimized to reduce the related parasitic effect.
The use of multi-layer printed circuit board is recommended.
Small signal components and connections to critical nodes of the application as well as
bypass capacitors for the device supply are also important. Locate the bypass capacitor
(VCC, PVCC and BOOT capacitors) close to the device with the shortest possible loop and
use wide copper traces to minimize parasitic inductance.
Systems that do not use Schottky diodes in parallel to the Low-Side MOSFET might show
big negative spikes on the phase pin. This spike can be limited as well as the positive spike
but has an additional consequence: it causes the bootstrap capacitor to be over-charged.
This extra-charge can cause, in the worst case condition of maximum input voltage and
during particular transients, that boot-to-phase voltage overcomes the abs.max.ratings also
causing device failures. It is then suggested in this cases to limit this extra-charge by adding
a small resistor R
the limitation of the spike present on the BOOT pin.
in series to the boot capacitor. The use of R
BOOT
also contributes in
BOOT
For heat dissipation, place copper area under the IC. This copper area may be connected
with internal copper layers through several VIAs to improve the thermal conductivity. The
combination of copper pad, copper plane and VIAs under the driver allows the device to
reach its best thermal performances.
Figure 7. Driver turn-on and turn-off paths
VCC
VCC
C
R
BOOT
R
GATERINT
LGATE
C
BOOT
LS DRIVER LS MOSFET
GND
GD
C
GS
C
DS
HS DRIVER HS MOSFET
BOOT
R
BOOT
HGATE
C
BOOT
PHASE
R
GATERINT
C
GD
C
GS
C
DS
11/17
Device description and operation L6743, L6743Q
Figure 8. External components placement example
BOOT
PWM
EN
VCC
Rboot Cboot
1
2
3
L6743
4
8
7
6
5
UGATE
PHASE
GND
LGATE
BOOT
PWM
EN
VCC
VCC
Rboot Cboot
1
2
3
L6743Q
4
56
10
9
8
7
UGATE
PHASE
GND
GND
LGATE
12/17
L6743, L6743Q Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
13/17
Package mechanical data L6743, L6743Q
Table 6. SO-8 mechanical data
Dim.
Min Typ Max Min Typ Max
A 1.35 1.75 53.1 68.9
A1 0.10 0.25 3.9 9.8
A2 1.10 1.65 43.3 65.0
B 0.33 0.51 13.0 20.1
C 0.19 0.25 7.5 9.8
(1)
D
4.80 5.00
E 3.80 4.00 149.6 157.5
e 1.27 50.0
H 5.80 6.20 228.3 244.1
h 0.25 0.50 9.8 19.7
L 0.40 1.27 15.7 50.0
k 0° (min.), 8° (max.)
ddd 0.10 3.9
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm (.006inch) in total (both side).
mm mils
189.0 196.9
Figure 9. Package dimensions
14/17
L6743, L6743Q Package mechanical data
Table 7. DFN10 mechanical data
mm mils
Dim.
Min Typ Max Min Typ Max
A 0.80 0.90 1.00 31.5 35.4 39.4
A1 0.02 0.05 0.8 2.0
A2 0.70 27.6
A3 0.20 7.9
b 0.18 0.23 0.30 7.1 9.1 11.8
D 3.00 118.1
D2 2.21 2.26 2.31 87.0 89.0 90.9
E 3.00 118.1
E2 1.49 1.64 1.74 58.7 64.6 68.5
e 0.50 19.7
L 0.3 0.4 0.5 11.8 15.7 19.7
M 0.75 29.5
m 0.25 9.8
Figure 10. Package dimensions
M
m
15/17
Revision history L6743, L6743Q
7 Revision history
Table 8. Document revision history
Date Revision Changes
20-Aug-2007 1 Initial release
05-Jun-2008 2 Updated: Table 6 on page 15
16/17
L6743, L6743Q
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