ST L6732 User Manual

Adjustable step-down controller with synchronous rectification

Features

■ Input voltage range from 1.8 V to 14 V

■ Supply voltage range from 4.5 V to 14 V

■ Adjustable output voltage down to 0.6 V

with ± 0.8 % accuracy over line voltage and
temperature (0 °C~125 °C)

■ Fixed frequency voltage mode control

■ T

■ 0 % to 100 % duty cycle

■ External input voltage reference

■ Soft-start and inhibit

■ High current embedded drivers

■ Predictive anti-cross conduction control

■ Programmable high-side and low-side R

■ Selectable switching frequency

■ Pre-bias start up capability

■ Power good output

■ Master/slave synchronization with 180° phase

■ Over voltage protection

■ Thermal shutdown

■ Package: HTSSOP16

lower than 100 ns

ON

sense over-current-protection

250 kHz / 500 kHz

shift

DS(on)

L6732

HTSSOP16 (exposed pad)

Applications

■ LCD and PDP TV

■ High performance / high density DC-DC

modules

■ Low voltage distributed DC-DC

■ niPoL converters

■ DDR memory supply

■ Graphic cards

Table 1. Device summary

Order codes Package Packing

L6732 HTSSOP16 Tube

L6732TR HTSSOP16 Tape and reel

June 2008 Rev 6 1/37

www.st.com

37

Contents L6732

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Pin connection and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 11

5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.9 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.10 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.11 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.12 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.12.1 Fan's power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 L6732 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2/37

L6732 Contents

7.1 20 A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.2 5 A board description and PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3/37

Summary description L6732

1 Summary description

The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5)
fabrication that provides complete control logic and protection for high performance step­down DC-DC and niPoL converters.

It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The
output voltage of the converter can be precisely regulated down to 600 mV with a maximum
tolerance of ±0.8 % and it is also possible to use an external reference from 0 V to 2.5 V.

The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from

4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power
section, and the output current can be in excess of 20 A. The PWM duty cycle can range
from 0 % to 100 % with a minimum on-time (T
conversions with very low duty cycle at high switching frequency. The device provides
voltage-mode control that includes a selectable frequency oscillator (250 kHz or 500 kHz).

The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that
permits to realize high converter bandwidth for fast transient response. The device monitors
the current by using the R
the need for a current sensing resistor and guaranteeing an effective over-current-protection
in all the application conditions. When necessary, two different current limit protections can
be externally set through two external resistors.

of both the high-side and low-side MOSFET(s), eliminating

DS(on)

ON, MIN

) lower than 100 ns making possible

During the soft-start phase a constant current protection is provided while after the soft-start
the device enters in hiccup mode in case of over-current. During the soft-start, the sink
mode capability is disabled in order to allow a proper start-up also in pre-biased output
voltage conditions. After the soft-start the device can sink current. Other features are
power good, master/slave synchronization (with 180° phase shift), over-voltage-protection,
feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the
realization of really compact DC/DC converters.

4/37

L6732 Summary description

1.1 Functional description

Figure 1. Block diagram

=

-

Vin=1.8V-14V

OCH

Monitor

Monitor

+

+

-

-

OCH

0.6V

OSC

OSC

VCCDR

VCCDR

LDO

LDO

L6732

-

-

+

+

+

+-+

PWM

PWM

E/A

E/A

-

-

BOOT

BOOT

HGATE

HGATE

-

-

PHASE

PHASE

V

OUT

LGATE

LGATE

PGND

PGND

GND

GND

EAREF

EAREF

PGOOD

SYNCH

SS

SS

OCL

OCL

Protection and Ref

Protection and Ref

FB

FB

COMP

COMP

5/37

Electrical data L6732

2 Electrical data

2.1 Maximum rating

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

V

VCC to GND and PGND, OCH, PGOOD -0.3 to 18 V

CC

V

BOOT -

V

PHASE

V

HGATE -

V

PHASE

V

BOOT

Boot voltage 0 to 6 V

0 to V

BOOT

- V

PHASE

V

BOOT -0.3 to 24 V

PHASE -1 to 18

V

PHASE

PHASE spike, transient < 50 ns (F

SS, FB, EAREF, SYNC, OCL, LGATE, COMP,
V

CCDR

OCH pin

Maximum withstanding voltage range
test condition: CDF-AEC-Q100-002 “human body

Other pins ±2000

model” acceptance criteria: “normal performance”

2.2 Thermal data

Table 3. Thermal data

Symbol Description Value Unit

R

T

thJA

STG

T

T

Thermal resistance junction to ambient 50 °C/W

Storage temperature range -40 to +150 °C

Junction operating temperature range -40 to +125 °C

J

Ambient operating temperature range -40 to +85 °C

A

= 500 kHz)

SW

-3

+24

-0.3 to 6 V

±1500

V

VPGOOD pin ±1000

6/37

L6732 Pin connection and function

3 Pin connection and function

Figure 2. Pin connection (top view)

PGOOD

SYNCH

SGND

FB

COMP

SS/INH

EAREF

OCL

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

HTSSOP16

Table 4. Pin functions

Pin n. Name Function

This pin is an open collector output and it is pulled low if the output voltage

1 PGOOD

2 SYNCH

3 SGND All the internal references are referred to this pin.

is not within the specified thresholds (90 %-110 %). If not used it may be left
floating. Pull-up this pin to V
signal.

It is a Master-Slave pin. Two or more devices can be synchronized by
simply connecting the SYNCH pins together. The device operating with the
highest FSW will be the Master. The Slave devices will operate with 180°
phase shift from the Master. The best way to synchronize devices together
is to set their FSW at the same value. If it is not used the SYNCH pin can
be left floating.

with a 10 k resistor to obtain a logical

CCDR

VCC

VCCDR

LGATE

PGND

BOOT

HGATE

PHASE

OCH

4 FB

5 COMP

6 SS/INH

This pin is connected to the error amplifier inverting input. Connect it to

through the compensation network. This pin is also used to sense the

V

OUT

output voltage in order to manage the over voltage conditions and the
PGood signal.

This pin is connected to the error amplifier output and is used to
compensate the voltage control feedback loop.

The soft-start time is programmed connecting an external capacitor from
this pin and GND. The internal current generator forces a current of 10 A
through the capacitor. When the voltage at this pin is lower than 0.5 V the
device is disabled.

7/37

Pin connection and function L6732

Table 4. Pin functions (continued)

Pin n. Name Function

By setting the voltage at this pin is possible to select the internal/external
reference and the switching frequency:

7 EAREF

8 OCL

V
V
V
An internal clamp limits the maximum V

captures the analog value present at this pin at the start-up when V
meets the UVLO threshold.

A resistor connected from this pin to ground sets the valley- current-limit.
The valley current is sensed through the low-side MOSFET(s). The internal
current generator sources a current of 100 µA (I
through the external resistor (R
the following equation:

Connecting a capacitor from this pin to GND helps in reducing the noise
injected from V
high-frequency noise related to the GND. Connect a capacitor only to a
“clean” GND.

0-80 % of V

EAREF

= 80 %-95 % of V

EAREF

= 95 %-100 % of V

EAREF

-> external reference/F

CCDR

-> V

CCDR

CCDR -> VREF

OCL

I

VALLEY

to the device, but can be a low impedance path for the

CC

= 0.6 V/FSW = 500 kHz

REF

= 0.6 V/F

EAREF

). The over-current threshold is given by

I

•

OCLROCL

----------------------------------=

2R

•

DSONLS

= 250 kHz

SW

= 250 kHz

SW

at 2.5 V (typ.). The device

) from this pin to ground

OCL

CC

A resistor connected from this pin and the high-side MOSFET(s) drain sets
the peak-current-limit. The peak current is sensed through the high-side

9 OCH

MOSFET(s). The internal 100 µA current generator (I
from the drain through the external resistor (R
threshold is given by the following equation:

I

•

I

PEAK

OCHROCH

--------------------------------- -=

R

DSONHS

OCH

). The over-current

OCH

This pin is connected to the source of the high-side MOSFET(s) and

10 PHASE

provides the return path for the high-side driver. This pin monitors the drop
across both the upper and lower MOSFET(s) for the current limit together
with OCH and OCL.

11 HGATE This pin is connected to the high-side MOSFET(s) gate.

Through this pin is supplied the high-side driver. Connect a capacitor from

12 BOOT

this pin to the PHASE pin and a diode from V

to this pin (cathode

CCDR

versus BOOT).

13 PGND

This pin has to be connected closely to the low-side MOSFET(s) source in
order to reduce the noise injection into the device.

14 LGATE This pin is connected to the low-side MOSFET(s) gate.

15 V

16 V

CCDR

CC

5 V internally regulated voltage. It is used to supply the internal drivers.
Filter it to ground with at least 1 µF ceramic cap.

Supply voltage pin.
The operative supply voltage range is from 4.5 V to 14 V.

) sinks a current

8/37

L6732 Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

(V

= 12 V, TA = 25 °C, unless otherwise specified)

CC

Symbol Parameter Test condition Min Typ Max Unit

V

supply current

CC

VCC stand by current OSC = open; SS to GND 7 9

I

CC

quiescent current

V

CC

OSC = open;
HG = open, LG = open,

8.5 10

mA

PH = open

Power-ON

V

CCDR

V

CC

V

IN OK

V

IN OK

regulation

Tu r n -O N VCC threshold V

Tu r n -O F F V

Tu r n -O N V

Tu r n -O F F V

V

voltage

CCDR

threshold V

CC

threshold 1.1 1.25 1.47 V

OCH

threshold 0.9 1.05 1.27 V

OCH

= 1.7 V 4.0 4.2 4.4 V

OCH

= 1.7 V 3.6 3.8 4.0 V

OCH

VCC = 5.5 V to 14 V
IDR = 1 mA to 100 mA

4.555.5V

Soft-start and inhibit

I

SS

Soft-start current

SS = 0 to 0.5 V 20 30 45

Oscillator

237 250 263 kHz

SS = 2 V 7 10 13

∆V

f

OSC

OSC

Accuracy

450 500 550 kHz

Ramp amplitude 2.1 V

Output voltage

V

FB

Output voltage V

= 0 to Vth 0.597 0.6 0.603 V

DIS

Error amplifier

R

EAREF

I

FB

Ext ref

clamp

V

OFFSET

G

V

EAREF input resistance Vs GND 70 100 150 kΩ

I.I. bias current VFΒ = 0 V 0.290 0.5 µA

2.3 V

Error amplifier offset Vref = 0.6 V -5 +5 mV

Open loop voltage gain Guaranteed by design 100 dB

GBWP Gain-bandwidth product Guaranteed by design 10 MHz

SR Slew-rate

COMP = 10 pF
Guaranteed by design

5V/µs

µA

9/37

Electrical characteristics L6732

Table 5. Electrical characteristics

(V

= 12 V, TA = 25 °C, unless otherwise specified) (continued)

CC

Symbol Parameter Test condition Min Typ Max Unit

Gate drivers

R

HGATE_ON

R

HGATE_OFF

R

LGATE_ON

R

LGATE_OFF

Protections

I

OCH

I

OCL

OVP

Power good

V

B

B

PGOOD

High side source resistance V

High side sink resistance V

Low side source resistance V

Low side sink resistance V

OCH current source V

- V

BOOT

- V

BOOT

= 5 V 1.15 Ω

CCDR

= 5 V 0.6 Ω

CCDR

= 1.7 V 90 100 110 µΑ

OCH

= 5 V 1.7 Ω

PHASE

= 5 V 1.12 Ω

PHASE

OCL current source 90 100 110 µΑ

rising

V

Over voltage trip
(VFB / VEAREF)

Under voltage threshold
(V

B

FB

/ VB

B

EAREF

)

B

Upper threshold
(V

B

FB

/ VB

B

EAREF

)

B

Lower threshold
(V

B

FB

/ VB

B

EAREF

)

B

PGOOD voltage low IB

FB

V

V
V

VB

VB

VB

= 0.6 V

EAREF

falling

FB

= 0.6 V

EAREF

falling 80 %

B

FB

rising 108 110 112 %

B

FB

falling 88 90 92 %

B

FB

= -5 mA 0.5 V

B

PGOOD

120 %

117 %

Table 6. Thermal characteristics (VCC = 12 V)

Symbol Parameter Test condition Min Typ Max Unit

Output voltage

T

= 0 °C ~ 125 °C 0.596 0.6 0.605

V

FB

Output voltage

10/37

J

= -40 °C ~ 125 °C 0.593 0.6 0.605

T

J

V

L6732 Device description

5 Device description

5.1 Oscillator

The switching frequency can be fixed to two values: 250 kHz or 500 kHz by setting the
proper voltage at the EAREF pin (see Table 4. pins function and section 4.3 Internal and
external reference).

5.2 Internal LDO

An internal LDO supplies the internal circuitry of the device. The input of this stage is the
V

pin and the output (5 V) is the V

CC

Figure 3. LDO block diagram

pin (Figure 3.).

CCDR

4.5÷14V

The LDO can be by-passed, providing directly a 5 V voltage to V
V

pins must be shorted together as shown in Figure 4. V

CCDR

LDO

. In this case VCC and

CCDR

pin must be filtered with

CCDR

at least 1 µF capacitor to sustain the internal LDO during the recharge of the bootstrap
capacitor. V

also represents a voltage reference for PGOOD pin (see Table 4. pins

CCDR

function).

11/37

Device description L6732

5.3 Bypassing the LDO to avoid the voltage drop with low Vcc

If V

≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω. The

CC

maximum LDO output current is about 100 mA and so the output voltage drop is 100 mV, to
avoid this the LDO can be by passed.

Figure 4. Bypassing the LDO

5.4 Internal and external references

It is possible to set the internal/external reference and the switching frequency by setting the
proper voltage at the EAREF pin. The maximum value of the external reference depends on
the V
5V the maximum external reference is 2.5 V (typ.).

Providing an external reference from 0 V to 450 mV the output voltage will be regulated but
some restrictions must be considered:

To set the resistor divider it must be considered that a 100 k pull-down resistor is integrated
into the device (see Figure 5.). Finally it must be taken into account that the voltage at the
EAREF pin is captured by the device at the start-up when V

: with V

CC

● V

● V

● V

● OV threshold saturates to a minimum value of 300 mV (OV is tracking the

= 4 V the clamp operates at about 2 V (typ.), while with VCC greater than

CC

from 0 % to 80 % of V

EAREF

from 80 % to 95 % of V

EAREF

from 95 % to 100 % of V

EAREF

CCDR

CCDR

reference; tracking small references will result in a narrow threshold reducing
noise immunity)

● The under-voltage-protection doesn't work;

● The PGOOD signal remains low;

-> External reference/Fsw = 250 kHz

CCDR

-> V

-> V

= 0.6V/Fsw = 500 kHz

REF

= 0.6V/Fsw = 250 kHz

REF

is about 4 V.

CC

12/37